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2026-01-24 - 15:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Sat Jan 24, 2026 00:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3082380999053,18cyclictest101550irq/39-eno2-TxRx-019:50:167
3082376998142,39cyclictest0-21swapper/320:55:163
3082380997638,19cyclictest871ktimers/721:11:497
3082380997618,39cyclictest3188464-21ntpq22:20:187
3082380997536,38cyclictest0-21swapper/720:00:127
3082380997517,39cyclictest3181208-21taskset22:08:577
3082380997233,39cyclictest0-21swapper/723:03:357
3082380997133,38cyclictest0-21swapper/723:22:107
3082380997132,39cyclictest0-21swapper/721:40:037
3082380996727,39cyclictest3199312-21ntpq22:40:177
308238099668,39cyclictest3140507-21cpuspeed_turbos20:55:137
3082375996627,38cyclictest0-21swapper/219:30:142
308238099656,19cyclictest0-21swapper/719:18:087
308238099645,19cyclictest0-21swapper/722:58:387
308238099635,0cyclictest0-21swapper/723:35:017
308238099624,0cyclictest0-21swapper/722:50:297
308238099623,19cyclictest0-21swapper/720:40:147
308238099613,0cyclictest0-21swapper/723:07:477
308238099613,0cyclictest0-21swapper/721:08:197
308238099613,0cyclictest0-21swapper/720:07:127
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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