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2026-01-31 - 14:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Sat Jan 31, 2026 00:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3436561997112,39cyclictest3505878-21kworker/u32:4+flush-8:021:56:147
3436561996931,38cyclictest3590996-21kworker/u32:2+events_unbound00:32:257
3436561995939,20cyclictest3515382-21kworker/u32:0+events_unbound21:50:147
343656199590,59cyclictest1095306-21kworker/u32:0+flush-8:019:56:067
3436561995638,18cyclictest0-21swapper/720:26:077
3436552995314,19cyclictest0-21swapper/121:20:151
3436561995233,19cyclictest0-21swapper/721:05:147
3436553995214,0cyclictest0-21swapper/222:40:152
3436553995213,39cyclictest0-21swapper/219:10:162
343655299529,19cyclictest0-21swapper/100:00:151
3436559995114,18cyclictest0-21swapper/623:25:166
3436552995113,19cyclictest0-21swapper/123:05:151
3436552995112,39cyclictest0-21swapper/121:55:131
3436561995012,19cyclictest0-21swapper/723:50:167
3436559995012,19cyclictest0-21swapper/623:50:156
3436552995012,38cyclictest0-21swapper/119:50:161
3436558994931,18cyclictest0-21swapper/521:35:165
3436558994810,19cyclictest0-21swapper/522:40:145
3436554994810,19cyclictest0-21swapper/320:05:143
343655399489,39cyclictest0-21swapper/219:45:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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