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2026-02-07 - 03:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Sat Feb 07, 2026 00:46:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3629766991220,0cyclictest0-21swapper/721:55:127
362976699990,0cyclictest0-21swapper/722:35:157
3629762999112,59cyclictest3662632-21cat20:10:013
3629762997717,39cyclictest3724132-21meminfo22:00:173
3629762997615,40cyclictest3687627-21/usr/sbin/munin20:55:193
3629762997113,39cyclictest3751517-21hddtemp_smartct22:50:143
3629762997112,40cyclictest3692234-21unixbench_multi21:00:223
3629762997112,19cyclictest0-21swapper/322:58:573
3629762997031,38cyclictest0-21swapper/321:53:423
3629762997030,39cyclictest3796444-21/usr/sbin/munin00:15:153
3629762997012,39cyclictest3717304-21munin-run21:50:013
3629762997012,19cyclictest0-21swapper/320:49:033
3629762996932,18cyclictest3756942-21perl23:00:143
3629762996932,18cyclictest319-21ice-ptp-0000:f4:00.022:15:163
3629762996830,19cyclictest0-21swapper/323:17:033
3629762996728,39cyclictest0-21swapper/322:38:013
3629762996647,19cyclictest511ktimers/320:40:193
3629762996628,19cyclictest0-21swapper/319:21:163
3629762996626,39cyclictest0-21swapper/323:54:433
3629762996626,39cyclictest0-21swapper/323:23:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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