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2026-02-09 - 06:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Mon Feb 09, 2026 00:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1911601999131,58cyclictest1961287-21/usr/sbin/munin20:40:233
191160199889,59cyclictest1-21systemd20:55:003
1911601997436,19cyclictest781-21mta-sts-daemon00:04:493
1911599997474,0cyclictest0-21swapper/123:35:151
1911601997131,19cyclictest0-21swapper/322:44:263
191160199635,39cyclictest236199-21snmpd22:59:333
191160199635,39cyclictest236199-21snmpd22:59:333
191160199624,58cyclictest0-21swapper/321:30:233
191160199613,39cyclictest871-21mta-sts-daemon19:19:583
1911599995921,19cyclictest331ktimers/120:40:171
1911601995839,19cyclictest511ktimers/320:55:093
1911601995517,19cyclictest1937107-21/usr/sbin/munin19:55:153
1911601995516,39cyclictest781-21mta-sts-daemon23:48:493
1911601995516,39cyclictest2020173-21proc_pri22:25:233
1911602995415,39cyclictest0-21swapper/421:40:164
1911601995436,18cyclictest0-21swapper/320:25:013
1911601995432,19cyclictest0-21swapper/300:21:413
1911601995416,19cyclictest2002000-21munin-run21:55:013
1911601995331,19cyclictest0-21swapper/323:50:573
1911601995331,19cyclictest0-21swapper/319:25:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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