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2026-02-08 - 16:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Sun Feb 08, 2026 12:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3363621996040,1cyclictest511ktimers/309:51:193
336362099590,40cyclictest3500253-21taskset11:15:162
3363621995533,19cyclictest0-21swapper/312:31:533
3363621995533,19cyclictest0-21swapper/311:39:593
3363621995533,19cyclictest0-21swapper/311:30:583
3363621995533,0cyclictest0-21swapper/308:00:533
3363621995433,19cyclictest0-21swapper/310:41:373
3363621995414,39cyclictest1-21systemd08:00:013
3363621995414,39cyclictest0-21swapper/310:25:473
3363621995414,39cyclictest0-21swapper/309:34:133
3363621995414,39cyclictest0-21swapper/309:34:133
3363621995414,39cyclictest0-21swapper/308:23:593
3363621995414,39cyclictest0-21swapper/308:06:433
3363621995414,39cyclictest0-21swapper/307:37:343
3363621995314,39cyclictest0-21swapper/310:18:313
3363621995314,39cyclictest0-21swapper/310:00:313
3363621995314,39cyclictest0-21swapper/307:44:313
3363621995314,39cyclictest0-21swapper/307:20:213
3363621995314,20cyclictest0-21swapper/307:25:163
3363621995313,39cyclictest0-21swapper/312:07:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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