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2026-02-09 - 18:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Mon Feb 09, 2026 12:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
452193999052,19cyclictest457252-21taskset07:16:214
45219399888,79cyclictest628152-21ntpq12:30:214
452193998585,0cyclictest631635-21taskset12:37:134
45219399855,79cyclictest0-21swapper/412:25:154
45219399830,82cyclictest615255-21taskset12:06:594
452193997416,58cyclictest601ktimers/412:18:414
452193997232,20cyclictest0-21swapper/408:30:214
452193996930,39cyclictest0-21swapper/411:18:094
452193996526,39cyclictest0-21swapper/410:13:534
452193996526,19cyclictest0-21swapper/407:34:454
45219399634,59cyclictest601ktimers/411:55:404
452193996222,39cyclictest0-21swapper/410:46:214
452193996117,40cyclictest572012-21/usr/sbin/munin10:50:184
45219399611,60cyclictest6043542sleep411:47:084
45219399590,19cyclictest0-21swapper/409:58:394
45219399590,18cyclictest0-21swapper/407:25:344
452193995737,19cyclictest533471-21cpu09:40:124
45219399570,17cyclictest0-21swapper/412:02:314
452191995613,38cyclictest0-21swapper/210:30:172
452193995519,20cyclictest0-21swapper/409:15:194
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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