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2025-12-06 - 03:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Fri Dec 05, 2025 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71614699653,59cyclictest743335-21kworker/u32:4+events_unbound09:40:123
716146996425,39cyclictest0-21swapper/310:16:283
716146996344,18cyclictest0-21swapper/310:00:203
716146996323,39cyclictest0-21swapper/309:10:423
71614699624,39cyclictest789143-21kworker/u32:1+flush-8:010:35:203
716146996223,39cyclictest0-21swapper/307:11:563
71614699613,39cyclictest105-21kcompactd009:20:063
716146996121,39cyclictest0-21swapper/309:09:433
71614699602,39cyclictest0-21swapper/311:00:513
71614699602,39cyclictest0-21swapper/311:00:503
716146996021,39cyclictest52-21ksoftirqd/312:22:513
716146996021,19cyclictest0-21swapper/310:59:533
716146996020,39cyclictest0-21swapper/312:05:443
71614699591,39cyclictest743335-21kworker/u32:4+events_unbound11:37:493
716146995838,19cyclictest726959-21ntpq07:40:193
716146995817,40cyclictest804855-21ntpq10:40:193
71614699580,58cyclictest781035-21kworker/u32:3+events_unbound10:47:253
71614699580,57cyclictest854256-21kworker/u32:2+events_unbound12:32:253
71614699580,39cyclictest828746-21/usr/sbin/munin11:25:123
71614699580,39cyclictest362-21jbd2/sda2-807:35:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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