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2026-03-04 - 04:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Wed Mar 04, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
943407997436,38cyclictest16-21ksoftirqd/023:55:180
943411996161,0cyclictest0-21swapper/400:10:344
943411996060,0cyclictest1056292-21systemd-run22:35:004
943411996060,0cyclictest0-21swapper/420:08:304
94341299590,40cyclictest0-21swapper/522:20:155
943411995959,0cyclictest0-21swapper/419:46:344
943411995959,0cyclictest0-21swapper/419:11:304
943411995959,0cyclictest0-21swapper/400:00:084
943411995858,0cyclictest0-21swapper/421:53:264
943411995858,0cyclictest0-21swapper/421:44:144
943411995819,19cyclictest0-21swapper/422:28:404
94341199570,38cyclictest954920-21kworker/u32:2+events_unbound20:14:104
943409995756,1cyclictest421ktimers/220:05:162
943412995638,0cyclictest0-21swapper/520:50:145
943411995636,19cyclictest1020747-21latency_hist21:30:024
943411995619,18cyclictest571irq_work/420:38:044
943411995618,19cyclictest1012920-21munin-run21:15:024
943411995618,0cyclictest191rcu_preempt00:36:544
94341199560,54cyclictest917591-21kworker/u32:4+events_unbound19:53:104
943411995537,0cyclictest0-21swapper/423:10:344
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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