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2026-01-15 - 22:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Thu Jan 15, 2026 12:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2767166995436,18cyclictest0-21swapper/011:05:160
2767168995214,19cyclictest0-21swapper/210:05:142
2767171995132,19cyclictest0-21swapper/512:00:155
2767171995113,19cyclictest0-21swapper/511:30:155
2767168995011,39cyclictest0-21swapper/210:00:152
2767168994912,18cyclictest411rcuc/211:10:162
2767168994810,19cyclictest0-21swapper/210:25:152
2767168994729,18cyclictest421ktimers/212:35:162
276717099466,39cyclictest0-21swapper/410:10:154
276716999466,39cyclictest0-21swapper/312:37:263
276716699468,19cyclictest0-21swapper/009:25:140
276716999456,38cyclictest90650irq/68-eno6-TxRx-609:01:393
276716999455,39cyclictest0-21swapper/312:05:073
276716999455,39cyclictest0-21swapper/311:05:513
276716999455,39cyclictest0-21swapper/308:24:283
276716999455,39cyclictest0-21swapper/308:06:433
276716999455,19cyclictest874-21mta-sts-daemon12:20:233
276716999454,39cyclictest2868186-21meminfo10:05:173
2767169994525,19cyclictest0-21swapper/310:55:373
2767166994537,0cyclictest0-21swapper/008:05:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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