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2026-03-05 - 18:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Thu Mar 05, 2026 12:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73871599600,60cyclictest0-21swapper/409:50:574
73871599600,0cyclictest0-21swapper/407:12:084
73871599590,59cyclictest0-21swapper/412:27:314
73871599590,59cyclictest0-21swapper/411:54:594
73871599590,59cyclictest0-21swapper/407:25:314
73871599590,19cyclictest0-21swapper/412:05:424
73871599590,19cyclictest0-21swapper/410:48:424
73871599590,18cyclictest0-21swapper/410:58:294
73871599580,58cyclictest0-21swapper/410:05:514
73871599580,18cyclictest0-21swapper/411:38:264
73871599580,0cyclictest0-21swapper/411:07:194
73871599570,57cyclictest0-21swapper/410:24:474
73871599570,0cyclictest0-21swapper/408:31:594
738715995617,39cyclictest236199-21snmpd12:39:094
738715995517,38cyclictest236199-21snmpd12:00:354
738712995214,38cyclictest0-21swapper/108:15:171
738712995214,19cyclictest0-21swapper/109:40:161
738712995133,0cyclictest0-21swapper/109:00:161
738712995113,19cyclictest0-21swapper/109:30:161
738712995113,19cyclictest0-21swapper/109:30:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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