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2026-02-24 - 07:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Tue Feb 24, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3764586991056,60cyclictest3811667-21systemd-run20:35:023
3764586997837,19cyclictest3933742-21meminfo00:15:203
3764586997635,18cyclictest3920343-21ntpq23:50:203
3764586997311,39cyclictest3903860-21ntpq23:20:203
3764586997131,39cyclictest38552112sleep321:53:583
3764586997111,19cyclictest0-21swapper/320:38:043
3764584997131,38cyclictest873-21mta-sts-daemon20:55:151
3764588997068,1cyclictest3855767-21chrt21:55:115
3764586997011,19cyclictest0-21swapper/300:20:033
3764586996910,19cyclictest0-21swapper/321:48:323
376458699622,59cyclictest3791227-21sensors19:55:223
3764586996225,18cyclictest3766203-21ntp_states19:10:203
3764586996224,18cyclictest0-21swapper/320:57:423
3764590996142,19cyclictest0-21swapper/700:05:167
376458699602,39cyclictest3783054-21timerwakeupswit19:40:243
3764586996019,20cyclictest873-21mta-sts-daemon22:57:523
3764586995818,19cyclictest0-21swapper/300:30:043
3764586995736,20cyclictest3829728-21ntpq21:05:203
3764586995717,19cyclictest511ktimers/300:29:283
3764586995717,19cyclictest0-21swapper/320:29:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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