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2026-05-30 - 01:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Fri May 29, 2026 12:46:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27031799911112,99cyclictest0-21swapper/108:50:151
2703179995314,39cyclictest0-21swapper/111:35:151
2703194995214,19cyclictest0-21swapper/409:15:154
2703179995112,39cyclictest0-21swapper/110:20:151
2703194994931,18cyclictest0-21swapper/412:20:144
2703199994810,19cyclictest0-21swapper/508:35:145
2703183994810,19cyclictest0-21swapper/212:05:152
270319999479,19cyclictest0-21swapper/508:55:165
270318399479,19cyclictest0-21swapper/209:15:152
270317999478,39cyclictest0-21swapper/109:00:151
270317799479,19cyclictest0-21swapper/010:20:150
270319999469,18cyclictest0-21swapper/511:10:145
2703199994627,19cyclictest0-21swapper/511:30:175
270319999457,19cyclictest0-21swapper/510:35:165
270319999457,19cyclictest0-21swapper/508:15:145
270319999457,19cyclictest0-21swapper/508:15:145
270319999450,2cyclictest0-21swapper/512:05:155
270319499456,38cyclictest0-21swapper/411:20:164
270319999446,19cyclictest0-21swapper/512:25:155
270318399447,18cyclictest0-21swapper/207:50:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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