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2026-01-26 - 16:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Mon Jan 26, 2026 12:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4121058996931,38cyclictest0-21swapper/207:55:152
4121062995214,18cyclictest0-21swapper/611:05:166
4121061995032,18cyclictest0-21swapper/510:05:165
4121056995012,19cyclictest0-21swapper/008:45:150
4121056995012,19cyclictest0-21swapper/008:35:170
4121060994948,1cyclictest0-21swapper/410:20:004
4121056994829,19cyclictest0-21swapper/012:35:150
412106299457,19cyclictest0-21swapper/607:10:146
412106099454,40cyclictest4133668-21head07:30:214
412106099445,39cyclictest0-21swapper/410:43:514
412106099445,39cyclictest0-21swapper/408:49:214
412106099445,39cyclictest0-21swapper/408:42:104
412106099444,39cyclictest786-21systemd-logind11:20:014
412106099444,39cyclictest0-21swapper/410:37:464
412106099444,39cyclictest0-21swapper/409:16:524
412106099444,39cyclictest0-21swapper/409:00:074
4121060994443,0cyclictest0-21swapper/410:55:134
4121060994425,19cyclictest0-21swapper/410:51:134
4121060994425,19cyclictest0-21swapper/409:37:214
4121060994424,19cyclictest0-21swapper/412:37:444
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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