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2025-12-03 - 15:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Wed Dec 03, 2025 00:46:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
381577699635,19cyclictest0-21swapper/622:55:176
381577499624,19cyclictest0-21swapper/420:45:024
381577499591,19cyclictest0-21swapper/419:55:394
381577499580,21cyclictest0-21swapper/419:51:514
381577499580,20cyclictest0-21swapper/420:37:024
381577499580,19cyclictest0-21swapper/419:21:264
3815776995736,20cyclictest3844052-21kworker/6:220:05:156
3815775995519,35cyclictest3815769-21cyclictest21:51:055
381577499550,55cyclictest0-21swapper/423:49:374
381577499550,17cyclictest0-21swapper/421:27:434
381577499550,16cyclictest0-21swapper/421:02:264
381577499540,15cyclictest0-21swapper/423:15:304
381577499540,15cyclictest0-21swapper/421:49:064
381577499540,15cyclictest0-21swapper/419:15:554
3815776995312,39cyclictest3816102-21kworker/u32:3+events_unbound19:59:146
3815777995233,19cyclictest0-21swapper/723:25:157
3815777995233,19cyclictest0-21swapper/719:40:187
3815776995233,19cyclictest0-21swapper/619:53:146
3815776995213,39cyclictest0-21swapper/619:45:156
3815772995214,19cyclictest0-21swapper/220:20:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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