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2026-02-19 - 05:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Thu Feb 19, 2026 00:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1756292991500,148cyclictest0-21swapper/520:30:125
175628999970,97cyclictest0-21swapper/223:55:162
1756296997637,38cyclictest871ktimers/723:50:417
1756296997618,39cyclictest1-21systemd19:20:017
1756296997315,39cyclictest1774488-21gunzip19:40:217
1756296997313,59cyclictest1826132-21sed21:15:177
1756296996527,18cyclictest0-21swapper/722:03:457
1756296996527,18cyclictest0-21swapper/722:03:457
1756296996325,19cyclictest0-21swapper/723:16:417
175629699613,39cyclictest1935800-21cstates00:35:137
1756296995718,19cyclictest877-21mta-sts-daemon19:55:357
1756296995619,36cyclictest0-21swapper/723:57:057
1756296995613,40cyclictest1848270-21ntpq21:55:197
1756296995613,40cyclictest1848270-21ntpq21:55:197
1756296995517,19cyclictest1779421-21irqstats19:50:177
1756296995435,0cyclictest871ktimers/722:18:477
1756296995319,34cyclictest0-21swapper/721:13:457
1756296995319,34cyclictest0-21swapper/720:28:137
1756296995319,15cyclictest0-21swapper/700:14:297
1756296995314,39cyclictest0-21swapper/722:57:257
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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