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2026-01-25 - 03:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Sun Jan 25, 2026 00:46:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1119849911597,18cyclictest0-21swapper/123:40:151
111990998628,39cyclictest291971-21grep00:35:177
111990998628,39cyclictest291971-21grep00:35:167
111990998343,0cyclictest191rcu_preempt19:21:247
11199099790,60cyclictest230317-21chrt22:42:067
111990997717,21cyclictest1086-21runrttasks22:51:567
111988997517,40cyclictest70-21ksoftirqd/523:55:165
111990997134,18cyclictest30750irq/60-ahci[0000:00:07.0]19:49:307
111990997133,38cyclictest0-21swapper/723:56:347
111990997133,19cyclictest30750irq/60-ahci[0000:00:07.0]21:17:307
111984997031,38cyclictest0-21swapper/100:15:141
111990996831,19cyclictest113606-21ntp_states19:10:207
111990996828,39cyclictest197644-21unin-run21:45:027
111990996810,39cyclictest260847-21sendmail-msp23:40:007
11199099679,39cyclictest170403-21sed20:55:027
111990996728,20cyclictest243596-21sed23:05:227
11199099657,39cyclictest160115-21uniq20:35:147
111990996426,38cyclictest215923-21cat22:15:247
111984996224,19cyclictest877-21mta-sts-daemon19:40:161
11199099610,59cyclictest105-21kcompactd021:31:487
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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