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2026-02-28 - 02:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Fri Feb 27, 2026 12:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1656125997272,0cyclictest0-21swapper/110:30:141
1656129997113,19cyclictest0-21swapper/511:35:155
1656121997049,20cyclictest171ktimers/009:25:150
1656129996425,38cyclictest875-21mta-sts-daemon10:55:165
165612199613,19cyclictest0-21swapper/009:05:150
165612199580,18cyclictest0-21swapper/009:30:160
1656121995712,20cyclictest0-21swapper/007:55:160
1656126995314,39cyclictest0-21swapper/212:35:152
1656125995315,19cyclictest0-21swapper/107:30:151
1656125995314,39cyclictest0-21swapper/109:00:171
1656125995133,0cyclictest0-21swapper/109:10:151
1656121995132,19cyclictest0-21swapper/009:20:160
1656121995113,38cyclictest0-21swapper/011:25:160
1656125994911,38cyclictest0-21swapper/108:35:151
1656121994912,18cyclictest0-21swapper/012:25:150
1656121994911,38cyclictest0-21swapper/011:20:150
165613099488,39cyclictest0-21swapper/610:35:166
1656125994810,19cyclictest0-21swapper/107:50:151
1656121994728,19cyclictest0-21swapper/007:35:150
1656121994728,0cyclictest0-21swapper/012:00:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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