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2026-01-29 - 11:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Thu Jan 29, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
951423998528,38cyclictest1011663-21latency_hist21:00:017
951423998325,39cyclictest1064174-21cut22:35:007
951423997735,40cyclictest1094041-21taskset23:25:467
951423997416,39cyclictest875-21mta-sts-daemon00:30:097
951423997333,19cyclictest0-21swapper/700:03:397
951423997233,20cyclictest0-21swapper/723:38:237
951423997233,19cyclictest0-21swapper/720:10:597
951423997232,19cyclictest0-21swapper/720:20:117
951423997214,39cyclictest1126027-21grep00:25:147
951423997214,19cyclictest0-21swapper/721:59:027
951423997214,0cyclictest0-21swapper/700:07:187
95142399718,40cyclictest1032138-21hddtemp_smartct21:35:157
95142399718,40cyclictest1032138-21hddtemp_smartct21:35:147
951423997133,18cyclictest0-21swapper/722:44:347
951423997132,19cyclictest874-21mta-sts-daemon00:19:307
951423997132,19cyclictest0-21swapper/721:04:077
951423997031,39cyclictest0-21swapper/723:14:197
951423997031,19cyclictest0-21swapper/723:18:027
951423997031,19cyclictest0-21swapper/720:04:317
951423997031,19cyclictest0-21swapper/719:21:517
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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