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2026-01-29 - 23:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Thu Jan 29, 2026 12:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
367361699117116,0cyclictest0-21swapper/012:30:160
3673620997314,19cyclictest0-21swapper/411:35:154
3673623997030,39cyclictest0-21swapper/707:58:117
3673623996929,39cyclictest0-21swapper/708:37:007
3673623996830,38cyclictest0-21swapper/709:55:117
3673623996829,39cyclictest0-21swapper/712:33:507
3673623996810,39cyclictest3838817-21/usr/sbin/munin12:10:137
3673623996426,19cyclictest3831810-21ntpq11:55:197
3673623996225,18cyclictest0-21swapper/711:45:207
3673623995919,39cyclictest0-21swapper/711:10:087
3673623995919,39cyclictest0-21swapper/711:10:077
367361799590,0cyclictest0-21swapper/110:10:141
3673623995819,39cyclictest0-21swapper/707:43:407
3673623995819,19cyclictest0-21swapper/710:40:437
367362399570,56cyclictest0-21swapper/709:25:187
367362399570,37cyclictest0-21swapper/710:10:597
3673623995637,19cyclictest871ktimers/709:52:117
3673623995619,17cyclictest0-21swapper/707:21:397
3673623995619,17cyclictest0-21swapper/707:21:397
3673623995618,19cyclictest3782290-21ntpq10:25:217
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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