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2025-11-27 - 05:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Thu Nov 27, 2025 00:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
285067999411,44cyclictest0-21swapper/723:25:197
285066997232,19cyclictest0-21swapper/620:38:256
285066997231,19cyclictest0-21swapper/620:33:306
285066997132,39cyclictest0-21swapper/621:48:096
285066997131,40cyclictest0-21swapper/620:56:416
285066997131,19cyclictest0-21swapper/623:43:486
285066997131,19cyclictest0-21swapper/621:16:346
285066997131,19cyclictest0-21swapper/600:36:046
285066997031,39cyclictest0-21swapper/621:20:416
285066997031,39cyclictest0-21swapper/600:34:526
285066997031,19cyclictest0-21swapper/622:56:366
285066997031,18cyclictest0-21swapper/623:25:366
285066997030,40cyclictest0-21swapper/623:04:366
285064997049,20cyclictest0-21swapper/420:50:154
285066996727,19cyclictest0-21swapper/623:32:166
285064995214,19cyclictest0-21swapper/400:15:164
285063995214,19cyclictest0-21swapper/321:15:163
285061995214,19cyclictest0-21swapper/122:30:201
285060995233,19cyclictest0-21swapper/019:55:190
285066995132,19cyclictest0-21swapper/620:21:556
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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