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2026-01-22 - 01:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Wed Jan 21, 2026 12:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1957888999012,59cyclictest2075146-21ntpq10:40:192
1957888998140,0cyclictest191rcu_preempt11:38:292
195788899760,57cyclictest324-21ice-ptp-0000:f4:00.209:06:402
1957888997013,38cyclictest875-21mta-sts-daemon08:18:492
1957888997011,58cyclictest2057972-21/usr/sbin/munin10:10:142
195788899699,20cyclictest2110893-21ldconfig11:45:212
195788899699,20cyclictest2110893-21ldconfig11:45:202
1957888996930,39cyclictest0-21swapper/211:55:012
1957888996930,39cyclictest0-21swapper/211:55:002
1957888996830,38cyclictest421ktimers/207:27:212
1957888996830,38cyclictest421ktimers/207:27:202
1957892996628,19cyclictest0-21swapper/610:10:156
1957888996627,39cyclictest1-21systemd07:35:012
1957888996627,39cyclictest1-21systemd07:35:002
195788899646,39cyclictest2135822-21pluginstate12:30:202
1957888996425,39cyclictest0-21swapper/208:55:002
1957888996243,0cyclictest20646982chrt10:20:532
195788899623,20cyclictest43-21ksoftirqd/208:29:212
1957888996142,0cyclictest105-21kcompactd009:39:452
195788899612,0cyclictest191rcu_preempt11:10:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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