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2026-02-27 - 14:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Fri Feb 27, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318593599927,20cyclictest0-21swapper/522:30:155
3185936997557,18cyclictest0-21swapper/622:15:176
318593799670,2cyclictest0-21swapper/719:45:167
3185930996126,17cyclictest221rcuc/022:05:150
3185935995512,19cyclictest0-21swapper/500:00:165
3185934995535,19cyclictest3219084-21idleruntime-cro20:10:004
3185935995214,19cyclictest0-21swapper/500:20:155
318593499528,39cyclictest3327028-21fschecks_count23:25:144
3185934995229,20cyclictest0-21swapper/420:17:504
3185934995229,19cyclictest0-21swapper/419:47:464
3185934995128,20cyclictest0-21swapper/422:31:024
3185934995128,19cyclictest0-21swapper/422:22:344
3185934995128,19cyclictest0-21swapper/420:48:184
318593499506,39cyclictest0-21swapper/421:57:424
3185934995028,0cyclictest0-21swapper/420:56:264
3185934995027,20cyclictest601ktimers/423:10:464
3185934994929,19cyclictest877-21mta-sts-daemon22:18:554
3185934994929,19cyclictest225-1kworker/4:1H+kblockd20:10:524
3185934994929,19cyclictest0-21swapper/423:36:284
3185934994929,19cyclictest0-21swapper/423:06:164
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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