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2026-02-10 - 18:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Tue Feb 10, 2026 12:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
174773399970,18cyclictest0-21swapper/209:55:152
1747733996324,38cyclictest873-21mta-sts-daemon11:25:162
1747737995921,0cyclictest0-21swapper/308:07:523
1747733995939,19cyclictest421ktimers/210:45:152
1747742995436,1cyclictest691ktimers/510:30:155
1747749995214,19cyclictest0-21swapper/611:40:176
1747739995213,19cyclictest0-21swapper/411:00:154
1747749995112,39cyclictest0-21swapper/612:00:136
1747729994910,39cyclictest0-21swapper/109:50:171
1747739994810,19cyclictest0-21swapper/409:30:154
174773399489,19cyclictest0-21swapper/211:30:162
174773399478,39cyclictest0-21swapper/211:40:172
1747739994426,18cyclictest873-21mta-sts-daemon10:10:164
174772799446,19cyclictest0-21swapper/008:45:160
174774999424,19cyclictest0-21swapper/610:05:146
174774999413,19cyclictest0-21swapper/612:15:146
174774299413,19cyclictest0-21swapper/507:45:155
174772999402,19cyclictest0-21swapper/111:10:151
174772999400,39cyclictest0-21swapper/112:15:151
1747754993938,1cyclictest1744496-21kworker/7:1+events10:05:017
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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