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2026-01-14 - 20:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Wed Jan 14, 2026 12:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
147595499141139,1cyclictest0-21swapper/311:00:113
1475953998020,59cyclictest0-21swapper/211:35:152
1475957997516,58cyclictest1617863-21if_eno211:20:136
1475957997515,19cyclictest1493098-21munin-run07:40:006
1475958997314,59cyclictest0-21swapper/710:05:157
1475957997335,19cyclictest1505134-21cpu08:00:126
1475957997333,19cyclictest0-21swapper/610:08:036
1475957997314,19cyclictest0-21swapper/610:55:166
1475957997314,19cyclictest0-21swapper/610:55:156
1475957997233,39cyclictest0-21swapper/610:47:426
1475957997233,18cyclictest1475950-21cyclictest07:28:066
1475957997233,18cyclictest0-21swapper/612:18:116
1475957997233,18cyclictest0-21swapper/609:59:156
1475957997233,18cyclictest0-21swapper/608:58:146
1475957996931,19cyclictest1525655-21if_eno508:35:156
147595799678,39cyclictest0-21swapper/611:30:256
1475957996526,19cyclictest0-21swapper/608:30:266
1475957996325,18cyclictest0-21swapper/610:11:386
1475957996324,20cyclictest0-21swapper/607:17:586
1475957996324,19cyclictest0-21swapper/610:19:316
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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