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2026-02-17 - 16:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Tue Feb 17, 2026 12:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1987732991260,124cyclictest0-21swapper/309:05:123
1987732999235,38cyclictest2016171-21/usr/sbin/munin08:00:143
1987732999012,61cyclictest0-21swapper/307:32:253
1987732998810,59cyclictest1995463-21users07:20:253
1987732997618,39cyclictest1086-21runrttasks07:47:503
198773899740,73cyclictest0-21swapper/709:05:127
1987732997419,15cyclictest0-21swapper/311:30:063
198772999740,73cyclictest0-21swapper/011:50:180
1987738997213,19cyclictest0-21swapper/710:35:167
1987732997233,39cyclictest0-21swapper/312:22:313
1987732997233,39cyclictest0-21swapper/312:22:303
1987732997032,38cyclictest0-21swapper/308:26:323
1987732997012,39cyclictest1086-21runrttasks09:18:073
198773299697,61cyclictest0-21swapper/310:35:493
1987732996830,19cyclictest2169518-21cat12:40:013
1987732996425,39cyclictest0-21swapper/309:58:033
1987732996020,39cyclictest0-21swapper/310:49:123
198773299590,18cyclictest0-21swapper/312:16:193
1987732995738,19cyclictest511ktimers/312:26:033
1987732995738,19cyclictest511ktimers/312:26:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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