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2026-01-31 - 00:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Fri Jan 30, 2026 12:46:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
730329997514,39cyclictest867229-21sed11:15:210
730329997254,18cyclictest0-21swapper/010:58:470
730329997254,0cyclictest0-21swapper/009:02:310
730329997234,19cyclictest737798-21kworker/0:2+ice07:39:190
730329997214,39cyclictest817344-21ntpq09:45:190
730329997214,19cyclictest0-21swapper/007:32:050
730329997112,39cyclictest779526-21vmstat08:35:230
730329996931,19cyclictest891708-21systemctl12:00:230
730329996910,58cyclictest815344-21chrt09:41:190
730329996829,39cyclictest0-21swapper/009:53:220
730329996627,19cyclictest801317-21timerandwakeup09:15:220
730329996525,39cyclictest872-21mta-sts-daemon10:40:130
730329996446,18cyclictest0-21swapper/010:47:290
730331996344,19cyclictest421ktimers/208:55:162
730329996324,39cyclictest0-21swapper/011:29:470
73032999602,39cyclictest795441-21ntpq09:05:190
730329996020,39cyclictest171ktimers/007:17:360
730329995921,38cyclictest731517-21if_err_eno407:10:170
730329995920,19cyclictest1750ktimers/011:00:250
73033399580,39cyclictest0-21swapper/410:30:144
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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