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2026-03-06 - 11:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Fri Mar 06, 2026 00:46:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
345326999171169,1cyclictest3561159-21cat22:25:010
3453270991260,125cyclictest0-21swapper/123:00:011
345327499740,73cyclictest0-21swapper/523:00:025
3453273995838,20cyclictest601ktimers/421:51:414
3453273995353,0cyclictest3579974-21latency_hist23:00:004
3453273995331,19cyclictest0-21swapper/423:31:484
3453273995331,19cyclictest0-21swapper/423:31:484
3453273995330,19cyclictest0-21swapper/422:32:204
3453273995230,19cyclictest0-21swapper/422:47:564
3453273995230,19cyclictest0-21swapper/422:22:404
3453273995230,19cyclictest0-21swapper/421:36:444
3453273995230,19cyclictest0-21swapper/420:00:284
3453273995229,20cyclictest0-21swapper/400:05:004
3453273995229,19cyclictest0-21swapper/421:50:004
3453272995213,39cyclictest0-21swapper/323:10:153
3453273995131,19cyclictest0-21swapper/423:14:224
3453273995131,19cyclictest0-21swapper/421:18:144
3453273995131,19cyclictest0-21swapper/420:34:064
3453273995130,18cyclictest0-21swapper/419:15:564
3453273995130,18cyclictest0-21swapper/419:15:564
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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