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2026-02-16 - 11:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Mon Feb 16, 2026 00:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2283193999820,59cyclictest2301453-21ntpq19:40:194
2283193999335,39cyclictest1-21systemd22:55:014
2283193999012,61cyclictest0-21swapper/420:09:094
2283196998750,18cyclictest88-21ksoftirqd/722:35:167
2283193997638,19cyclictest2303247-21cat19:45:134
2283193997437,18cyclictest61-21ksoftirqd/421:55:494
2283193997414,58cyclictest2374092-21kworker/u32:0+events_unbound22:02:024
2283193997355,18cyclictest0-21swapper/422:35:534
2283193997314,39cyclictest191rcu_preempt23:43:434
2283193997153,0cyclictest0-21swapper/419:57:534
2283193997133,38cyclictest61-21ksoftirqd/420:26:394
2283193997132,19cyclictest191rcu_preempt21:19:144
2283193997112,59cyclictest2409842-21kworker/u32:0+events_unbound23:09:144
2283193997052,18cyclictest61-21ksoftirqd/420:30:124
2283193996911,39cyclictest0-21swapper/422:27:344
2283193996849,19cyclictest2381181-21timerandwakeup22:05:214
228319399668,39cyclictest2369808-21needreboot21:45:194
228319399668,19cyclictest0-21swapper/423:10:144
2283193996022,19cyclictest2311200-21aten2.4-expect20:00:134
2283195995921,38cyclictest0-21swapper/600:35:166
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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