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2026-02-20 - 06:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Fri Feb 20, 2026 00:46:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
302662099131130,0cyclictest0-21swapper/120:10:021
3026624997538,18cyclictest691ktimers/521:25:165
302662499740,73cyclictest0-21swapper/520:10:025
302662399687,60cyclictest3074117-21munin-run20:35:014
3026623996728,39cyclictest0-21swapper/421:28:354
302662399668,39cyclictest3186191-21taskset23:56:414
302662399635,39cyclictest3156623-21latency_hist23:05:004
302662399623,59cyclictest3135556-21awk22:25:154
3026623996223,39cyclictest0-21swapper/423:14:424
302662399610,60cyclictest3044392-21memory19:40:164
3026623996022,38cyclictest0-21swapper/423:15:094
3026623995958,1cyclictest3098876-21unin-run21:20:014
3026623995921,19cyclictest3064508-21ntpq20:15:224
302662399591,39cyclictest0-21swapper/400:10:344
3026623995738,18cyclictest870-21mta-sts-daemon20:50:154
3026623995720,18cyclictest601ktimers/420:08:464
3026623995619,37cyclictest0-21swapper/420:44:174
3026623995617,39cyclictest3124921-21awk22:05:204
3026623995616,39cyclictest3166116-21lpstat23:20:164
3026623995516,19cyclictest3104715-21ls21:30:124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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