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2025-11-16 - 00:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Sat Nov 15, 2025 12:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180335998729,39cyclictest282779-21kworker/2:210:40:072
180340997820,19cyclictest0-21swapper/711:19:217
18034099770,58cyclictest250610-21cat09:10:247
180340997618,39cyclictest326292-21cat11:25:197
180340997618,38cyclictest185687-21unixbench_singl07:15:247
180340997313,20cyclictest0-21swapper/709:30:207
180340997232,19cyclictest364739-21munin-run12:35:017
180340997232,19cyclictest364739-21munin-run12:35:017
180340997214,19cyclictest0-21swapper/711:49:217
180340997213,19cyclictest0-21swapper/707:26:467
180340997133,19cyclictest328621-21fschecks_time11:30:197
180340997011,59cyclictest0-21swapper/711:03:577
180340996911,0cyclictest0-21swapper/707:45:587
180340996810,19cyclictest0-21swapper/710:32:457
180340996810,19cyclictest0-21swapper/707:32:387
18034099679,19cyclictest0-21swapper/710:13:337
18034099679,19cyclictest0-21swapper/707:54:437
180340996627,39cyclictest8750ktimers/711:40:277
180340996527,19cyclictest0-21swapper/707:10:167
180340996423,40cyclictest0-21swapper/711:00:017
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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