You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-22 - 20:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Thu Jan 22, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
506272998810,39cyclictest643414-21idleruntime-cro23:19:594
50627499800,78cyclictest0-21swapper/619:35:116
506272997676,0cyclictest627611-21tail22:50:124
50627299750,73cyclictest0-21swapper/419:45:164
506272997415,40cyclictest560521-21/usr/sbin/munin20:45:224
506272997318,15cyclictest0-21swapper/421:40:124
506272997315,39cyclictest604594-21taskset22:05:284
506272997233,18cyclictest0-21swapper/420:00:144
506272997131,19cyclictest0-21swapper/400:15:014
506272997012,39cyclictest626693-21chrt22:45:334
506272996928,19cyclictest876-21mta-sts-daemon22:00:144
506272996829,39cyclictest0-21swapper/400:03:164
506272996828,39cyclictest0-21swapper/423:41:234
50627299668,39cyclictest657853-21cstates23:45:144
506272996021,19cyclictest0-21swapper/422:11:234
506272996021,19cyclictest0-21swapper/420:44:314
506272995919,22cyclictest0-21swapper/419:50:144
50627299590,40cyclictest638385-21/usr/sbin/munin23:10:124
506273995838,19cyclictest0-21swapper/523:25:165
506272995819,39cyclictest0-21swapper/421:20:124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional