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2026-08-30 - 06:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Sun Aug 30, 2026 00:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1243114997714,60cyclictest1248511-21cron19:20:003
1243114997335,19cyclictest511ktimers/321:51:543
1243114997333,19cyclictest0-21swapper/319:41:383
1243111997335,18cyclictest872-21mta-sts-daemon22:05:162
1243114997233,18cyclictest0-21swapper/322:45:163
1243114996930,38cyclictest1274789-21ntpq20:05:213
1243114996930,38cyclictest1274789-21ntpq20:05:203
1243114996829,19cyclictest0-21swapper/322:00:573
1243114996829,19cyclictest0-21swapper/300:21:413
1243114996829,19cyclictest0-21swapper/300:06:133
1243114996828,19cyclictest0-21swapper/323:26:013
124311499675,40cyclictest1387047-21df23:30:123
1243114996730,18cyclictest511ktimers/319:51:023
1243114996728,19cyclictest0-21swapper/323:15:573
1243114996728,19cyclictest0-21swapper/321:06:303
124311499668,39cyclictest1244722-21ntpq19:10:193
124311499666,58cyclictest511ktimers/320:47:463
1243114996424,19cyclictest0-21swapper/320:56:523
124311499635,39cyclictest1345679-21smartctl22:15:163
1243114996323,19cyclictest0-21swapper/320:25:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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