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2026-01-19 - 11:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Mon Jan 19, 2026 00:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
891267991560,156cyclictest0-21swapper/222:05:102
891266998224,39cyclictest1078-21lldpd20:50:371
891266997818,59cyclictest1053400-21chrt00:02:381
891266997333,39cyclictest957351-21cat21:10:001
891266997113,39cyclictest908025-21sed19:40:011
891266997112,40cyclictest1010976-21ntpq22:45:191
891266996829,38cyclictest1003938-21latency_hist22:35:001
891266996810,39cyclictest236199-21snmpd22:55:231
89126699679,19cyclictest0-21swapper/121:03:411
89126699667,40cyclictest960867-21diskstats21:15:151
89126699644,59cyclictest1043973-21ntpq23:45:191
89126799624,0cyclictest191rcu_preempt23:15:162
89126699613,39cyclictest1025143-21systemctl23:10:271
89126699610,42cyclictest994592-21ntpq22:15:181
891269995516,39cyclictest987337-21kworker/0:0-events_power_efficient23:10:514
891266995517,38cyclictest929225-21sed20:15:221
891266995517,19cyclictest932163-21chrt20:22:171
891266995517,19cyclictest932163-21chrt20:22:161
89126699550,55cyclictest0-21swapper/123:19:521
891271995314,39cyclictest0-21swapper/620:25:156
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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