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2025-12-26 - 18:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Fri Dec 26, 2025 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136277599134132,1cyclictest876-21mta-sts-daemon11:10:186
136275799134132,1cyclictest874-21mta-sts-daemon11:10:180
1362774999921,59cyclictest1494069-21meminfo11:00:185
1362774999314,58cyclictest1422362-21latency_hist08:55:015
1362774997456,18cyclictest0-21swapper/510:00:175
1362774997416,39cyclictest1393676-21runrttasks08:03:275
1362774997335,19cyclictest681rcuc/508:55:235
1362774996930,20cyclictest0-21swapper/508:46:215
1362772996912,18cyclictest0-21swapper/311:30:143
1362774996829,39cyclictest0-21swapper/511:18:265
1362774996829,39cyclictest0-21swapper/508:18:205
1362774996829,19cyclictest0-21swapper/510:51:245
1362774996728,39cyclictest0-21swapper/510:58:265
1362774996728,39cyclictest0-21swapper/510:14:275
1362774996728,39cyclictest0-21swapper/508:24:195
1362774996728,19cyclictest0-21swapper/509:31:505
1362774996727,22cyclictest0-21swapper/509:47:445
1362774996727,22cyclictest0-21swapper/509:47:445
1362774996627,39cyclictest0-21swapper/509:05:345
1362774996627,21cyclictest0-21swapper/512:07:415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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