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2025-12-25 - 17:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Thu Dec 25, 2025 12:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4183264991860,185cyclictest0-21swapper/008:15:120
4183271991690,168cyclictest0-21swapper/708:17:317
4183265991240,123cyclictest0-21swapper/109:31:141
4183266991210,120cyclictest0-21swapper/211:13:382
4183266991210,120cyclictest0-21swapper/209:31:152
418327099850,84cyclictest0-21swapper/608:17:316
4183271997416,39cyclictest792-21rs:main7
4183271997336,37cyclictest131172-21kworker/u32:3+writeback11:22:297
4183271997335,38cyclictest0-21swapper/710:10:177
418327199679,39cyclictest158253-21basename12:05:217
4183271996729,19cyclictest30750irq/60-ahci[0000:00:07.0]12:15:487
418327199667,59cyclictest160814-21ntpq12:10:197
418326999669,38cyclictest70-21ksoftirqd/511:25:145
4183271996344,18cyclictest0-21swapper/711:40:157
4183271996224,38cyclictest0-21swapper/709:25:297
4183271996118,24cyclictest0-21swapper/710:58:177
418327199600,1cyclictest191rcu_preempt07:15:017
418327199592,38cyclictest74514-21kworker/u32:2+events_unbound10:29:577
4183271995819,39cyclictest0-21swapper/712:35:567
4183271995719,38cyclictest0-21swapper/712:22:317
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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