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2026-01-26 - 04:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Mon Jan 26, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1403556997333,39cyclictest0-21swapper/723:09:557
1403556997313,59cyclictest1479408-21ld21:25:207
1403556997232,39cyclictest0-21swapper/722:53:207
1403556997214,19cyclictest0-21swapper/723:26:307
1403556997132,39cyclictest0-21swapper/720:32:357
1403556997132,19cyclictest0-21swapper/700:15:017
1403556997131,39cyclictest0-21swapper/722:39:567
1403556997131,39cyclictest0-21swapper/720:52:527
1403556997032,19cyclictest0-21swapper/721:01:207
1403556997031,39cyclictest0-21swapper/719:32:117
1403556997030,39cyclictest0-21swapper/721:52:047
1403556997030,39cyclictest0-21swapper/720:29:167
1403556997030,39cyclictest0-21swapper/720:23:037
1403556997011,19cyclictest0-21swapper/722:55:177
1403556996930,19cyclictest0-21swapper/723:46:327
140355599689,40cyclictest1477190-21kworker/5:021:35:156
1403556996728,39cyclictest0-21swapper/723:02:047
140355199654,60cyclictest43-21ksoftirqd/222:45:162
140355699624,19cyclictest0-21swapper/720:00:267
1403556996222,39cyclictest1512660-21ldconfig22:25:207
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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