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2026-02-11 - 19:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Wed Feb 11, 2026 12:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29933269911134,18cyclictest0-21swapper/308:35:233
2993326998525,20cyclictest1-21systemd10:35:003
299332699852,40cyclictest3103121-21sh10:30:013
299332699824,59cyclictest3166136-21/usr/sbin/munin12:20:213
2993326998223,19cyclictest0-21swapper/312:05:313
299332699810,59cyclictest3087074-21/usr/sbin/munin10:00:173
299332899780,59cyclictest61-21ksoftirqd/412:30:174
2993326997333,19cyclictest31255272sleep311:10:053
2993326997230,40cyclictest0-21swapper/309:49:523
2993326997132,39cyclictest0-21swapper/309:14:553
2993326997132,19cyclictest0-21swapper/308:40:053
2993326997131,19cyclictest0-21swapper/311:27:573
2993326997112,59cyclictest3057133-21/usr/sbin/munin09:05:153
2993326997032,19cyclictest194598rtkit-daemon09:53:153
2993326997030,20cyclictest5150ktimers/312:37:243
2993326996931,18cyclictest0-21swapper/307:10:493
2993326996930,39cyclictest0-21swapper/307:35:113
2993326996929,19cyclictest0-21swapper/310:40:093
2993326996828,19cyclictest5150ktimers/308:13:133
2993326996810,19cyclictest0-21swapper/311:07:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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