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2026-01-21 - 01:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Tue Jan 20, 2026 12:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
658013998912,58cyclictest815971-21df11:55:144
65801399846,59cyclictest658110-21kworker/4:0+events07:20:124
658013997312,39cyclictest786525-21ld11:00:204
658013996728,39cyclictest601ktimers/411:07:544
65801399668,39cyclictest236199-21snmpd11:29:544
65801399666,39cyclictest724797-21cat09:10:024
65801399657,39cyclictest824475-21fschecks_count12:10:144
658013996526,39cyclictest695147-21meminfo08:15:184
65801399624,19cyclictest0-21swapper/411:37:164
658013995921,38cyclictest0-21swapper/408:53:024
65801399590,21cyclictest0-21swapper/407:40:524
658013995856,2cyclictest601ktimers/411:20:204
658013995839,19cyclictest601ktimers/408:21:224
658013995817,19cyclictest6050ktimers/407:25:204
65801399580,20cyclictest0-21swapper/408:12:444
658013995717,19cyclictest734075-21/usr/sbin/munin09:25:164
658013995636,20cyclictest601ktimers/412:15:084
658013995616,19cyclictest702807-21diskstats08:30:164
658013995615,19cyclictest0-21swapper/409:55:044
658013995519,15cyclictest0-21swapper/409:31:284
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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