You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-08 - 03:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Sun Feb 08, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
69159699740,55cyclictest733390-21kworker/u32:0+events_unbound20:34:021
691603997212,19cyclictest0-21swapper/500:10:145
691596997032,19cyclictest0-21swapper/120:50:161
691596997032,19cyclictest0-21swapper/120:50:151
691603996910,39cyclictest0-21swapper/522:30:165
69159699666,59cyclictest843350-21taskset23:40:441
691596996425,20cyclictest787481-21chrt22:00:191
69159699634,40cyclictest801395-21ntpq22:25:191
691596995920,39cyclictest331ktimers/122:49:571
691590995958,1cyclictest171ktimers/019:55:170
691605995818,40cyclictest88-21ksoftirqd/720:50:177
691605995818,40cyclictest88-21ksoftirqd/720:50:167
69159699580,58cyclictest686374-21kworker/u32:1+events_unbound19:14:111
691596995738,19cyclictest331ktimers/121:39:131
691596995717,20cyclictest362-21jbd2/sda2-823:30:171
69159699570,38cyclictest746546-21kworker/u32:0+events_unbound23:26:121
69159699570,36cyclictest791332-21kworker/u32:4+events_unbound22:35:481
69159699570,18cyclictest0-21swapper/121:05:161
691596995637,19cyclictest331ktimers/100:10:411
69159699560,55cyclictest686374-21kworker/u32:1+events_unbound19:47:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional