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2026-01-16 - 10:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Fri Jan 16, 2026 00:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1322781998545,39cyclictest421ktimers/221:07:512
132278199813,59cyclictest1499471-21sed00:20:012
1322781998121,39cyclictest1400900-21/usr/sbin/munin21:25:172
1322781997638,18cyclictest101850irq/42-eno2-TxRx-320:05:252
1322781997556,19cyclictest421ktimers/221:40:332
1322781997435,38cyclictest0-21swapper/223:24:092
1322781997316,18cyclictest101850irq/42-eno2-TxRx-319:27:572
1322781997214,19cyclictest0-21swapper/221:38:302
1322781997113,39cyclictest1364325-21ntpq20:20:212
1322781997052,18cyclictest101850irq/42-eno2-TxRx-300:27:252
1322781996931,19cyclictest1458207-21ld23:05:212
1322781996850,0cyclictest0-21swapper/222:31:032
1322781996810,39cyclictest1362620-21munin-run20:20:012
1322781996727,39cyclictest0-21swapper/200:23:432
1322781996526,39cyclictest0-21swapper/220:27:392
132278199646,39cyclictest1380565-21fschecks_count20:50:152
132278199646,39cyclictest1337413-21/usr/sbin/munin19:35:172
132278199645,39cyclictest1441034-21cut22:35:192
1322781996426,19cyclictest1453845-21munin-run23:00:012
1322781996425,39cyclictest0-21swapper/221:58:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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