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2026-02-01 - 14:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7.osadl.org (updated Sun Feb 01, 2026 00:46:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
504723999432,40cyclictest595953-21latency_hist21:55:036
504723997435,38cyclictest870-21mta-sts-daemon20:20:166
504723997251,20cyclictest590588-21cat21:45:026
504723997213,39cyclictest0-21swapper/619:33:586
504723997213,39cyclictest0-21swapper/619:33:586
504723996910,38cyclictest1-21systemd22:55:006
504723996810,39cyclictest614858-21sensors22:25:256
50472399646,0cyclictest0-21swapper/620:40:026
50472399633,19cyclictest0-21swapper/623:35:156
504723995819,38cyclictest585143-21munin-run21:35:026
504723995818,39cyclictest587864-21cat21:40:026
504723995818,19cyclictest560602-21munin-run20:50:026
50472399580,39cyclictest539783-21awk20:10:206
504723995718,0cyclictest520262-21meminfo19:35:186
504723995617,38cyclictest0-21swapper/620:18:246
50472399560,56cyclictest0-21swapper/622:14:306
504723995517,38cyclictest504716-21cyclictest21:18:516
504723995419,15cyclictest0-21swapper/621:28:526
504723995416,19cyclictest676815-21chrt00:22:066
504723995416,19cyclictest643756-21/usr/sbin/munin23:20:126
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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