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2025-09-16 - 16:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackfslot7.osadl.org (updated Tue Sep 16, 2025 12:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36153979910568,19cyclictest171ktimers/011:15:180
361539799678,59cyclictest0-21swapper/008:05:160
361539799678,59cyclictest0-21swapper/008:05:160
361540099635,39cyclictest3765617-21grep11:30:303
3615400996324,19cyclictest0-21swapper/309:52:143
361540099624,39cyclictest3617219-21/usr/sbin/munin07:10:233
3615400996222,39cyclictest3660630-21systemctl08:30:023
3615400996020,39cyclictest0-21swapper/311:14:323
361540099590,58cyclictest0-21swapper/309:47:563
3615400995719,19cyclictest0-21swapper/310:27:363
3615400995717,39cyclictest3670510-21meminfo08:45:213
3615400995717,39cyclictest3662334-21ntp_states08:30:233
3615399995719,38cyclictest0-21swapper/209:20:162
3615400995615,39cyclictest3644846-21/usr/sbin/munin08:00:153
3615400995536,18cyclictest3793202-21/usr/sbin/munin12:20:203
3615400995536,18cyclictest3725918-21perf10:25:013
3615400995535,19cyclictest3781759-21irqstats12:00:193
3615400995414,39cyclictest0-21swapper/312:18:483
3615400995414,39cyclictest0-21swapper/311:43:043
3615400995414,39cyclictest0-21swapper/309:22:433
3615400995413,19cyclictest3629525-21munin-run07:35:013
3615400995333,19cyclictest0-21swapper/311:20:223
3615400995314,39cyclictest0-21swapper/310:05:163
3615400995314,39cyclictest0-21swapper/309:44:403
3615400995314,39cyclictest0-21swapper/309:29:023
3615400995314,39cyclictest0-21swapper/308:10:073
3615400995313,39cyclictest0-21swapper/312:11:093
3615400995313,39cyclictest0-21swapper/311:45:123
3615400995313,39cyclictest0-21swapper/309:05:283
3615400995313,39cyclictest0-21swapper/307:22:463
3615400995214,19cyclictest0-21swapper/310:31:093
3615400995213,39cyclictest0-21swapper/311:56:363
3615400995213,39cyclictest0-21swapper/310:44:243
3615400995132,19cyclictest0-21swapper/308:42:423
3615400995131,19cyclictest0-21swapper/311:01:483
3615400995113,19cyclictest1-21systemd08:25:013
3615400995113,19cyclictest0-21swapper/310:15:173
3615400995113,19cyclictest0-21swapper/309:55:253
3615400995112,39cyclictest0-21swapper/307:37:153
3615400995111,39cyclictest783-21mta-sts-daemon12:28:363
3615400995111,39cyclictest0-21swapper/311:18:213
3615400995111,39cyclictest0-21swapper/310:59:543
3615400995111,39cyclictest0-21swapper/310:01:143
3615400995111,39cyclictest0-21swapper/307:47:203
3615400995111,39cyclictest0-21swapper/307:47:193
3615399995113,19cyclictest0-21swapper/208:25:162
3615400995032,18cyclictest0-21swapper/310:54:203
3615400995011,38cyclictest0-21swapper/310:45:023
3615400995010,39cyclictest0-21swapper/312:05:263
3615400995010,39cyclictest0-21swapper/307:41:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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