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2025-12-07 - 11:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackfslot7.osadl.org (updated Sun Dec 07, 2025 00:46:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
538998997638,38cyclictest540369-21latency19:10:185
538998997618,39cyclictest692298-21cat23:40:025
538998997556,18cyclictest0-21swapper/522:05:185
538998997415,39cyclictest619765-21idleruntime21:30:185
538998997133,19cyclictest718161-21diskstats00:25:185
538998997113,39cyclictest716160-21ld00:20:225
538998997032,19cyclictest627292-21munin-run21:45:015
538998997011,21cyclictest0-21swapper/500:04:185
538998996810,19cyclictest0-21swapper/521:18:545
538998996810,19cyclictest0-21swapper/520:54:465
538998996810,19cyclictest0-21swapper/520:49:105
53899899679,39cyclictest710629-21pmu-power00:10:285
53899899679,19cyclictest0-21swapper/521:58:065
538998996729,38cyclictest362-21jbd2/sda2-820:02:305
538998996728,39cyclictest0-21swapper/522:40:245
538998996726,19cyclictest688875-21chrt23:32:405
538998996726,19cyclictest688875-21chrt23:32:405
53899899668,39cyclictest615165-21users21:20:245
53899899668,19cyclictest0-21swapper/519:28:385
53899899668,19cyclictest0-21swapper/519:28:375
538998996647,18cyclictest0-21swapper/522:00:205
538998996525,39cyclictest0-21swapper/521:25:185
53899899646,19cyclictest0-21swapper/521:54:315
53899899632,59cyclictest604720-21kworker/u32:4+events_unbound21:10:285
538998996325,19cyclictest681rcuc/523:45:145
538998996325,19cyclictest681rcuc/523:45:145
538998996324,19cyclictest538992-21cyclictest20:20:325
53899899624,39cyclictest630257-21kworker/u32:2+events_unbound22:30:145
538998996223,21cyclictest0-21swapper/522:45:045
538998996124,18cyclictest573041-21kworker/u32:3+events_unbound20:15:185
53899899602,39cyclictest658361-21kworker/u32:4+events_unbound23:12:165
538998996020,39cyclictest0-21swapper/519:21:025
538998995922,18cyclictest567429-21kworker/u32:0-flush-8:021:00:065
538998995920,39cyclictest0-21swapper/522:26:175
538998995920,19cyclictest691ktimers/521:39:205
538998995919,39cyclictest0-21swapper/519:43:365
538998995918,39cyclictest878-21mta-sts-daemon22:56:305
538998995820,19cyclictest0-21swapper/520:35:065
538998995820,19cyclictest0-21swapper/520:09:025
538998995819,39cyclictest0-21swapper/520:33:105
53899899580,57cyclictest567429-21kworker/u32:0+events_unbound22:38:385
53899899580,39cyclictest574371-21ld20:10:235
538998995719,38cyclictest0-21swapper/500:19:215
538998995719,18cyclictest0-21swapper/500:38:485
538998995718,21cyclictest691ktimers/521:08:285
538998995718,21cyclictest0-21swapper/519:50:465
538998995518,18cyclictest0-21swapper/523:20:025
538998995516,38cyclictest691ktimers/519:46:035
538998995514,40cyclictest0-21swapper/523:01:545
538998995514,40cyclictest0-21swapper/519:36:005
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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