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2026-02-02 - 03:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackfslot7.osadl.org (updated Sun Feb 01, 2026 12:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318126899740,55cyclictest3305027-21aten2.4-expect10:55:114
3181268997315,19cyclictest1086-21runrttasks07:58:554
3181269996910,39cyclictest0-21swapper/509:15:165
318126899668,39cyclictest3293155-21sed10:30:234
318126899590,40cyclictest3279985-21/usr/sbin/munin10:10:014
3181268995738,19cyclictest601ktimers/407:17:554
3181268995738,19cyclictest601ktimers/407:17:554
3181268995617,19cyclictest236199-21snmpd12:13:454
318126899560,37cyclictest3225542-21kworker/u32:3+events_unbound08:45:114
3181268995436,18cyclictest0-21swapper/412:39:274
3181268995419,35cyclictest0-21swapper/411:54:114
3181268995419,35cyclictest0-21swapper/411:54:114
3181268995419,35cyclictest0-21swapper/409:29:434
3181268995419,35cyclictest0-21swapper/408:08:314
3181268995419,15cyclictest0-21swapper/412:08:144
3181268995419,15cyclictest0-21swapper/412:00:354
3181268995419,15cyclictest0-21swapper/412:00:354
3181268995419,15cyclictest0-21swapper/409:19:364
3181268995415,19cyclictest3318049-21sed11:15:234
3181268995319,34cyclictest0-21swapper/407:34:154
3181268995319,15cyclictest0-21swapper/409:20:434
3181268995314,39cyclictest3230466-21taskset08:39:034
3181268995314,39cyclictest0-21swapper/411:33:594
3181268995314,39cyclictest0-21swapper/410:40:394
3181268995314,39cyclictest0-21swapper/410:12:554
3181268995314,39cyclictest0-21swapper/409:44:504
3181268995314,39cyclictest0-21swapper/408:43:204
3181268995314,39cyclictest0-21swapper/408:12:354
3181268995314,19cyclictest0-21swapper/411:24:254
3181268995313,39cyclictest0-21swapper/411:38:474
3181268995313,19cyclictest3308123-21aten2.4_rfpower11:00:134
3181268995233,19cyclictest0-21swapper/412:31:394
3181268995233,19cyclictest0-21swapper/412:21:314
3181268995233,19cyclictest0-21swapper/412:17:594
3181268995233,19cyclictest0-21swapper/410:23:194
3181268995233,19cyclictest0-21swapper/409:38:314
3181268995233,19cyclictest0-21swapper/408:50:114
3181268995233,19cyclictest0-21swapper/408:15:114
3181268995233,19cyclictest0-21swapper/407:20:354
3181268995214,19cyclictest0-21swapper/411:09:234
3181268995213,39cyclictest0-21swapper/410:49:154
3181268995213,39cyclictest0-21swapper/410:00:134
3181268995213,39cyclictest0-21swapper/408:27:314
3181268995213,39cyclictest0-21swapper/408:22:434
3181268995213,0cyclictest0-21swapper/409:05:014
3181267995214,19cyclictest0-21swapper/309:40:173
3181264995214,19cyclictest0-21swapper/008:45:150
3181268995133,18cyclictest0-21swapper/411:47:314
3181268995133,18cyclictest0-21swapper/411:47:304
3181268995133,18cyclictest0-21swapper/409:54:114
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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