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2026-02-22 - 17:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #f, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot7s.osadl.org (updated Sun Feb 22, 2026 00:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
171281099284913,2832cyclictest1809973-21kworker/0:2+events00:15:130
171282099283713,2822cyclictest1766811-21kworker/3:3+events22:05:133
171281599279913,2783cyclictest1766876-21kworker/1:1+events22:25:211
171282099276413,2746cyclictest1781416-21kworker/3:1+events22:55:183
171281799270813,2691cyclictest1752905-21kworker/2:0+events21:20:142
171281799270413,2687cyclictest1751206-21kworker/2:1+events21:10:132
171281799258513,2566cyclictest1752905-21kworker/2:0+events21:15:162
171281599256113,2545cyclictest1744953-21kworker/1:0+events20:50:411
171281599255612,2541cyclictest1713989-21kworker/1:2+events19:15:001
171281599253612,2521cyclictest1741365-21kworker/1:1+events20:40:021
17128209925079,2494cyclictest1762300-21kworker/3:0+events21:44:353
171281599249312,2477cyclictest1755780-21kworker/1:0+events21:43:501
171281099249312,2478cyclictest1746518-21kworker/0:0+events20:55:160
171281599248911,2475cyclictest1755780-21kworker/1:0+events21:28:381
171281099248912,2473cyclictest1779889-21kworker/0:0+events23:08:370
17128159924889,2476cyclictest1759195-21kworker/1:2+events21:38:551
171281099248811,2474cyclictest1762271-21kworker/0:2+events22:04:020
171281099248612,2470cyclictest1808313-21kworker/0:1+events00:20:560
171281099248611,2471cyclictest1805482-21kworker/0:0+events00:06:290
171281099248512,2470cyclictest1758894-21kworker/0:0+events21:33:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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