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2026-02-15 - 01:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackaslot4.osadl.org (updated Sat Feb 14, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
65453399110,7cyclictest0-21swapper/22
6545379981,3cyclictest0-21swapper/22
6545339981,5cyclictest0-21swapper/22
6545339980,6cyclictest0-21swapper/22
6545379973,3cyclictest0-21swapper/22
6545379971,5cyclictest0-21swapper/22
6545379971,5cyclictest0-21swapper/22
6545379971,4cyclictest0-21swapper/22
6545379971,4cyclictest0-21swapper/22
6545379971,4cyclictest0-21swapper/22
6545379971,4cyclictest0-21swapper/22
6545379971,4cyclictest0-21swapper/22
6545379971,4cyclictest0-21swapper/22
6545379971,4cyclictest0-21swapper/22
6545379971,4cyclictest0-21swapper/22
6545379971,4cyclictest0-21swapper/22
6545339973,3cyclictest0-21swapper/22
6545339972,4cyclictest0-21swapper/22
6545339971,5cyclictest0-21swapper/22
6545339971,5cyclictest0-21swapper/22
6545339971,4cyclictest0-21swapper/22
6545339971,4cyclictest0-21swapper/22
6545339971,4cyclictest0-21swapper/22
6545339971,4cyclictest0-21swapper/22
6545339971,4cyclictest0-21swapper/22
6545339971,4cyclictest0-21swapper/22
6545339971,4cyclictest0-21swapper/22
6545339971,2cyclictest0-21swapper/22
6545339971,2cyclictest0-21swapper/22
6545379961,4cyclictest0-21swapper/22
6545379961,4cyclictest0-21swapper/22
6545379961,4cyclictest0-21swapper/22
6545379961,4cyclictest0-21swapper/22
6545379961,2cyclictest0-21swapper/22
6545379961,2cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
6545339961,4cyclictest0-21swapper/22
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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