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2026-01-16 - 00:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackaslot4.osadl.org (updated Thu Jan 15, 2026 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
234812699111,2cyclictest0-21swapper/22
234813099101,6cyclictest0-21swapper/22
23481309991,5cyclictest0-21swapper/22
23481269992,5cyclictest0-21swapper/22
23481269992,5cyclictest0-21swapper/22
23481269992,5cyclictest0-21swapper/22
23481269992,5cyclictest0-21swapper/22
23481269992,5cyclictest0-21swapper/22
23481269992,5cyclictest0-21swapper/22
23481309981,5cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269982,4cyclictest0-21swapper/22
23481269981,5cyclictest0-21swapper/22
23481269981,5cyclictest0-21swapper/22
23481309971,5cyclictest0-21swapper/22
23481309971,4cyclictest0-21swapper/22
23481309971,2cyclictest0-21swapper/22
23481309971,2cyclictest0-21swapper/22
23481309970,5cyclictest0-21swapper/22
23481269972,4cyclictest0-21swapper/22
23481269972,4cyclictest0-21swapper/22
23481269972,4cyclictest0-21swapper/22
23481269972,4cyclictest0-21swapper/22
23481269972,4cyclictest0-21swapper/22
23481269972,4cyclictest0-21swapper/22
23481269972,3cyclictest0-21swapper/22
23481269972,3cyclictest0-21swapper/22
23481269972,2cyclictest0-21swapper/22
23481269972,2cyclictest0-21swapper/22
23481269972,2cyclictest0-21swapper/22
23481269972,2cyclictest0-21swapper/22
23481269972,2cyclictest0-21swapper/22
23481269972,2cyclictest0-21swapper/22
23481269972,2cyclictest0-21swapper/22
23481269971,5cyclictest0-21swapper/22
23481269971,5cyclictest0-21swapper/22
23481269971,4cyclictest0-21swapper/22
23481269971,4cyclictest0-21swapper/22
23481269971,4cyclictest0-21swapper/22
23481269971,4cyclictest0-21swapper/22
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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