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2026-01-28 - 18:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Wed Jan 28, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3093099693,8cyclictest0-21swapper/306:51:143
3093099693,8cyclictest0-21swapper/306:51:143
30930996110,45cyclictest0-21swapper/310:30:323
2900725811,16sleep10-21swapper/106:39:551
3093099564,46cyclictest0-21swapper/310:12:573
3093099563,46cyclictest14565-21ssh09:30:223
3092299564,15cyclictest0-21swapper/209:47:382
3092299554,45cyclictest0-21swapper/212:12:152
3092299554,45cyclictest0-21swapper/211:09:062
30910995514,6cyclictest5376-21aten_rbpower_cu10:44:580
3093099542,46cyclictest4749-21/usr/sbin/munin07:00:223
3092299544,45cyclictest0-21swapper/211:44:302
3092299544,43cyclictest0-21swapper/210:45:492
3092299544,43cyclictest0-21swapper/210:28:272
3091099544,24cyclictest0-21swapper/011:00:380
3091099544,24cyclictest0-21swapper/011:00:380
3093099536,41cyclictest0-21swapper/310:05:343
3093099534,43cyclictest0-21swapper/310:24:333
3093099533,44cyclictest0-21swapper/311:49:453
3093099533,44cyclictest0-21swapper/311:49:453
30930995320,28cyclictest382-21systemd-journal10:38:083
30930995311,7cyclictest10731-21processes08:40:143
3092299535,42cyclictest0-21swapper/211:48:152
3092299535,42cyclictest0-21swapper/211:48:152
3092299534,43cyclictest0-21swapper/209:03:392
30922995314,35cyclictest4635-21timerandwakeup10:00:182
30910995322,27cyclictest20199-21grep08:55:150
3093099524,9cyclictest0-21swapper/311:56:053
3093099524,42cyclictest0-21swapper/310:47:473
3093099524,42cyclictest0-21swapper/309:18:493
3093099524,42cyclictest0-21swapper/307:45:043
3093099524,11cyclictest0-21swapper/308:46:493
3093099523,5cyclictest0-21swapper/310:55:103
3093099523,42cyclictest0-21swapper/308:05:113
30930995211,12cyclictest0-21swapper/309:48:403
3093099521,46cyclictest37-21ksoftirqd/310:28:173
3092299524,42cyclictest0-21swapper/211:32:262
3093099516,39cyclictest0-21swapper/309:51:133
3093099514,41cyclictest0-21swapper/309:05:093
3093099513,9cyclictest0-21swapper/311:25:463
3093099513,43cyclictest0-21swapper/309:03:233
3093099513,22cyclictest0-21swapper/308:53:243
30930995113,33cyclictest5743-21ssh12:10:043
3092299514,40cyclictest0-21swapper/209:55:012
3091099513,42cyclictest0-21swapper/009:53:080
3093099506,38cyclictest0-21swapper/310:41:103
3093099504,39cyclictest0-21swapper/308:55:293
3093099504,39cyclictest0-21swapper/308:30:173
3093099504,39cyclictest0-21swapper/308:30:173
30930995015,30cyclictest37-21ksoftirqd/309:10:053
30930995012,5cyclictest0-21swapper/310:54:073
30930995012,32cyclictest0-21swapper/309:37:563
30930995011,33cyclictest0-21swapper/311:38:493
3092299504,40cyclictest0-21swapper/211:21:312
3092299504,40cyclictest0-21swapper/210:51:042
30922995035,10cyclictest0-21swapper/209:44:082
3092299503,41cyclictest0-21swapper/210:43:072
3093099494,39cyclictest0-21swapper/307:05:223
3093099493,41cyclictest0-21swapper/309:29:483
3093099493,41cyclictest0-21swapper/309:29:483
3093099492,6cyclictest10687-21latency_hist11:34:473
30930994911,32cyclictest0-21swapper/309:56:333
3092299495,38cyclictest0-21swapper/211:50:082
3092299494,6cyclictest0-21swapper/208:58:092
3092299494,39cyclictest0-21swapper/212:07:512
3092299494,39cyclictest0-21swapper/208:46:592
3092299494,39cyclictest0-21swapper/207:24:512
3092299493,40cyclictest0-21swapper/212:00:352
3092299493,40cyclictest0-21swapper/209:37:482
3092299492,42cyclictest17394-21ls11:00:062
3092299492,42cyclictest17394-21ls11:00:062
30922994917,26cyclictest11548-21diskmemload10:35:382
3091099499,33cyclictest0-21swapper/009:10:500
3091099495,38cyclictest0-21swapper/008:45:550
3091099494,11cyclictest0-21swapper/009:45:100
3091099493,40cyclictest0-21swapper/011:30:170
3093099487,35cyclictest0-21swapper/312:06:233
3093099486,37cyclictest0-21swapper/309:22:253
3093099484,39cyclictest0-21swapper/310:15:483
3093099484,38cyclictest0-21swapper/311:40:053
3093099484,38cyclictest0-21swapper/311:20:443
3093099484,38cyclictest0-21swapper/311:15:383
3093099484,38cyclictest0-21swapper/311:06:553
3093099484,38cyclictest0-21swapper/308:35:143
3093099484,38cyclictest0-21swapper/307:40:213
3093099484,38cyclictest0-21swapper/307:35:183
3093099484,38cyclictest0-21swapper/307:24:523
3093099484,37cyclictest0-21swapper/310:00:333
3093099484,37cyclictest0-21swapper/307:19:523
3093099484,37cyclictest0-21swapper/307:14:523
3093099483,8cyclictest0-21swapper/312:00:453
3093099483,40cyclictest0-21swapper/309:41:283
3093099483,39cyclictest0-21swapper/311:11:363
3093099483,39cyclictest0-21swapper/311:04:143
3093099483,39cyclictest0-21swapper/311:04:143
3092299484,39cyclictest0-21swapper/209:06:092
3092299484,38cyclictest0-21swapper/211:54:482
3092299484,38cyclictest0-21swapper/211:18:502
3092299484,38cyclictest0-21swapper/208:00:102
3092299483,9cyclictest0-21swapper/208:51:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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