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2026-03-02 - 00:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Sun Mar 01, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1869899584,46cyclictest0-21swapper/209:41:472
1869899574,48cyclictest0-21swapper/210:23:362
1869899574,46cyclictest0-21swapper/211:10:152
1869899573,48cyclictest0-21swapper/210:50:102
18698995625,25cyclictest11795-21grep10:08:082
1869899554,46cyclictest0-21swapper/207:08:052
1869899553,46cyclictest0-21swapper/210:15:062
18698995515,34cyclictest25749-21processes06:43:072
1869899544,43cyclictest0-21swapper/209:50:072
1869199544,44cyclictest0-21swapper/110:31:061
18686995445,5cyclictest3-21ksoftirqd/011:57:340
183352549,15sleep30-21swapper/306:26:203
1869899538,8cyclictest0-21swapper/210:07:372
1869899533,45cyclictest0-21swapper/207:01:412
1869899531,47cyclictest281ktimersoftd/207:58:072
1869899531,47cyclictest281ktimersoftd/207:58:072
1869199535,41cyclictest0-21swapper/110:16:361
1869199534,42cyclictest0-21swapper/111:02:051
1869899524,42cyclictest0-21swapper/211:54:542
1869899524,42cyclictest0-21swapper/211:00:552
1869899524,41cyclictest0-21swapper/210:33:562
1869899524,41cyclictest0-21swapper/210:33:562
1869899523,8cyclictest0-21swapper/209:08:082
1869899523,6cyclictest14593-21latency_hist08:47:392
1869899523,44cyclictest0-21swapper/210:54:552
1869899522,27cyclictest26110-21ssh09:02:462
1870299512,6cyclictest25089-21cat09:43:073
1870299512,6cyclictest25089-21cat09:43:073
1869899515,40cyclictest0-21swapper/210:42:472
1869899514,41cyclictest0-21swapper/211:43:442
1869899514,40cyclictest0-21swapper/211:22:162
1869899514,14cyclictest0-21swapper/207:43:022
1869899513,41cyclictest0-21swapper/207:05:092
18698995112,34cyclictest27018-21fschecks_count06:47:552
1869199518,15cyclictest31598-21diskmemload08:43:501
1869199514,41cyclictest0-21swapper/109:49:111
1869199514,41cyclictest0-21swapper/109:24:101
1869199514,41cyclictest0-21swapper/108:49:381
1869199514,10cyclictest0-21swapper/111:27:551
1869199514,10cyclictest0-21swapper/111:27:551
18691995112,33cyclictest4503-21awk10:42:361
18702995018,26cyclictest32193-21missed_timers09:52:573
1869899504,40cyclictest0-21swapper/209:57:512
1869899504,40cyclictest0-21swapper/206:53:052
1869899503,41cyclictest0-21swapper/209:25:072
1869899503,40cyclictest0-21swapper/209:54:372
1869899501,43cyclictest27-21rcuc/211:23:002
1869899501,43cyclictest27-21rcuc/211:23:002
1869199504,6cyclictest0-21swapper/109:55:071
1869199504,41cyclictest0-21swapper/110:54:451
1869199504,40cyclictest0-21swapper/111:22:301
1869199503,42cyclictest0-21swapper/109:18:181
1869199502,5cyclictest11815-21ssh10:52:051
1868699504,41cyclictest0-21swapper/011:08:050
1870299494,39cyclictest0-21swapper/309:41:303
1869899496,37cyclictest0-21swapper/209:34:452
1869899496,37cyclictest0-21swapper/209:28:382
1869899494,39cyclictest0-21swapper/211:34:432
1869899494,39cyclictest0-21swapper/208:27:422
1869899494,39cyclictest0-21swapper/208:23:112
1869899494,38cyclictest0-21swapper/211:41:342
1869899494,12cyclictest0-21swapper/209:00:122
1869899494,12cyclictest0-21swapper/209:00:122
1869899493,41cyclictest0-21swapper/211:48:142
1869899493,41cyclictest0-21swapper/209:18:272
1869899493,40cyclictest0-21swapper/211:17:252
1869899493,40cyclictest0-21swapper/207:47:542
1869199495,38cyclictest0-21swapper/106:32:581
1869199494,9cyclictest0-21swapper/111:43:341
1869199494,40cyclictest0-21swapper/111:06:451
1869199494,39cyclictest0-21swapper/111:54:191
1869199494,39cyclictest0-21swapper/111:14:551
1869199493,42cyclictest0-21swapper/109:34:371
1869199493,41cyclictest0-21swapper/111:37:541
1869199493,41cyclictest0-21swapper/110:33:461
1869199493,41cyclictest0-21swapper/110:33:461
1869199493,41cyclictest0-21swapper/110:07:461
18691994912,31cyclictest0-21swapper/109:14:141
18691994910,34cyclictest21-21ksoftirqd/109:37:521
1869899487,36cyclictest0-21swapper/210:19:022
1869899484,38cyclictest0-21swapper/208:56:002
1869899484,38cyclictest0-21swapper/208:33:072
1869899484,37cyclictest0-21swapper/211:03:022
1869899484,37cyclictest0-21swapper/208:40:402
1869899483,39cyclictest0-21swapper/211:27:452
1869899483,39cyclictest0-21swapper/211:27:452
18698994813,30cyclictest25839-21aten_rbpower_po10:27:482
18698994811,30cyclictest2460-21sshd09:13:062
1869199484,6cyclictest0-21swapper/111:25:151
1869199484,6cyclictest0-21swapper/111:25:151
1869199484,39cyclictest0-21swapper/110:46:371
1869199484,38cyclictest0-21swapper/109:44:021
1869199484,38cyclictest0-21swapper/109:44:021
1869199484,10cyclictest0-21swapper/111:08:351
1869199483,40cyclictest0-21swapper/109:29:171
1869199483,39cyclictest0-21swapper/106:28:021
1869199482,40cyclictest23396-21ssh11:48:351
18691994812,5cyclictest0-21swapper/110:26:591
18691994811,31cyclictest0-21swapper/110:04:191
1869199481,42cyclictest2247-21ssh08:30:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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