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2026-02-05 - 04:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Thu Feb 05, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201742710,3sleep1201ktimersoftd/122:43:271
10734997113,33cyclictest4507-21aten_rbpower_en21:40:590
274942700,4sleep1201ktimersoftd/122:52:491
10750996210,45cyclictest0-21swapper/321:38:373
10739995950,5cyclictest21-21ksoftirqd/121:40:471
104092598,17sleep20-21swapper/218:39:492
1075099575,46cyclictest0-21swapper/321:51:463
10739995646,5cyclictest21-21ksoftirqd/121:50:471
1073999564,7cyclictest0-21swapper/100:02:431
1073999564,46cyclictest0-21swapper/120:40:581
1075099554,45cyclictest0-21swapper/323:28:243
1075099553,47cyclictest0-21swapper/323:53:463
1075099553,47cyclictest0-21swapper/323:53:463
10750995513,36cyclictest6014-21sshd23:06:473
1073999555,6cyclictest0-21swapper/121:24:171
1075099548,40cyclictest0-21swapper/320:49:143
1075099544,43cyclictest0-21swapper/322:57:053
1073999545,44cyclictest0-21swapper/123:40:301
1073999544,44cyclictest0-21swapper/121:26:291
1075099534,43cyclictest0-21swapper/323:15:043
1075099534,24cyclictest0-21swapper/321:59:383
1075099534,24cyclictest0-21swapper/321:59:383
10750995316,32cyclictest15793-21sshd21:11:203
10750995316,32cyclictest15793-21sshd21:11:203
1073999533,44cyclictest0-21swapper/122:11:461
1073999533,44cyclictest0-21swapper/122:04:171
1075099524,6cyclictest0-21swapper/323:50:443
1075099523,43cyclictest0-21swapper/322:45:563
10750995213,33cyclictest30759-21sshd21:31:193
1073999524,42cyclictest0-21swapper/122:21:061
1073999524,42cyclictest0-21swapper/121:07:071
1073999523,44cyclictest0-21swapper/122:59:521
1073999523,26cyclictest0-21swapper/123:20:151
181872510,7sleep218191-21unixbench_singl18:56:222
1075099515,21cyclictest0-21swapper/320:42:343
1075099513,26cyclictest0-21swapper/322:35:583
1075099513,26cyclictest0-21swapper/322:35:583
10750995110,36cyclictest0-21swapper/321:42:043
1074299518,37cyclictest0-21swapper/223:22:242
1073999514,42cyclictest0-21swapper/120:36:011
1073999514,42cyclictest0-21swapper/100:07:461
1075099509,35cyclictest0-21swapper/322:33:033
1075099504,41cyclictest0-21swapper/320:55:383
1075099504,40cyclictest0-21swapper/322:25:583
1075099504,40cyclictest0-21swapper/320:56:353
1075099503,42cyclictest0-21swapper/319:54:553
1075099503,41cyclictest0-21swapper/323:21:143
1075099503,41cyclictest0-21swapper/322:53:053
1075099503,41cyclictest0-21swapper/322:22:563
1075099503,41cyclictest0-21swapper/321:04:173
1075099503,24cyclictest0-21swapper/323:34:093
10750995013,32cyclictest7546-21if_eth219:56:063
1073999506,38cyclictest0-21swapper/122:18:051
1073999506,38cyclictest0-21swapper/122:06:401
1073999504,40cyclictest0-21swapper/122:49:351
1073999504,40cyclictest0-21swapper/122:32:461
1073999504,40cyclictest0-21swapper/121:01:271
1073999503,42cyclictest0-21swapper/121:44:561
1073999502,42cyclictest24821-21kworker/1:123:45:341
1075099499,34cyclictest0-21swapper/323:41:563
1075099494,8cyclictest0-21swapper/323:56:433
1075099494,38cyclictest0-21swapper/321:07:363
1075099493,40cyclictest0-21swapper/322:20:363
1075099493,40cyclictest0-21swapper/322:06:363
1075099493,40cyclictest0-21swapper/321:49:173
1075099492,25cyclictest0-21swapper/322:05:473
1073999496,38cyclictest0-21swapper/121:55:121
1073999496,38cyclictest0-21swapper/120:58:281
1073999496,37cyclictest0-21swapper/121:30:491
1073999493,40cyclictest0-21swapper/120:47:481
10739994912,5cyclictest0-21swapper/121:20:351
10739994911,32cyclictest0-21swapper/123:33:171
1073999491,44cyclictest16189-21ssh22:38:051
1073999491,44cyclictest16189-21ssh22:38:051
1073499493,41cyclictest0-21swapper/022:45:050
1075099485,37cyclictest0-21swapper/321:28:043
1075099484,39cyclictest0-21swapper/321:24:233
1075099484,38cyclictest0-21swapper/323:38:363
1075099483,40cyclictest0-21swapper/300:06:023
1073999488,35cyclictest0-21swapper/120:54:071
1073999486,37cyclictest0-21swapper/123:58:051
1073999486,37cyclictest0-21swapper/121:56:311
1073999486,37cyclictest0-21swapper/121:56:311
1073999484,39cyclictest0-21swapper/119:06:051
1073999483,41cyclictest0-21swapper/123:51:141
1073999483,41cyclictest0-21swapper/123:51:141
1073999483,41cyclictest0-21swapper/123:04:551
1073999483,40cyclictest0-21swapper/123:12:141
1073999483,40cyclictest0-21swapper/123:07:551
1073499486,35cyclictest0-21swapper/022:16:060
1075099479,32cyclictest0-21swapper/321:16:463
1075099474,38cyclictest0-21swapper/323:01:333
1075099474,38cyclictest0-21swapper/319:41:073
1075099474,37cyclictest0-21swapper/323:17:033
1075099474,37cyclictest0-21swapper/322:42:073
1075099474,17cyclictest0-21swapper/322:14:283
10750994732,10cyclictest0-21swapper/300:02:433
10742994716,26cyclictest773-21aten_rbpower_en21:35:582
1073999478,33cyclictest0-21swapper/123:27:311
1073999477,34cyclictest0-21swapper/120:22:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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