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2026-01-14 - 17:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Wed Jan 14, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
843699804,69cyclictest0-21swapper/109:12:001
843699728,58cyclictest0-21swapper/111:40:301
843699728,58cyclictest0-21swapper/111:40:301
843699728,5cyclictest0-21swapper/110:53:571
843699719,56cyclictest0-21swapper/110:58:321
843699719,56cyclictest0-21swapper/110:21:391
843699715,7cyclictest0-21swapper/109:19:121
843699715,7cyclictest0-21swapper/109:14:261
843699715,7cyclictest0-21swapper/109:06:241
843699714,8cyclictest0-21swapper/109:39:371
843699714,7cyclictest0-21swapper/111:57:261
843699712,7cyclictest23503-21find10:22:431
843699705,7cyclictest0-21swapper/111:56:081
843699705,59cyclictest0-21swapper/111:26:021
843699705,59cyclictest0-21swapper/109:33:561
843699705,58cyclictest0-21swapper/109:49:071
843699705,58cyclictest0-21swapper/109:49:071
843699705,58cyclictest0-21swapper/109:23:511
843699704,7cyclictest0-21swapper/110:03:381
843699704,7cyclictest0-21swapper/109:43:541
843699704,60cyclictest0-21swapper/110:28:021
843699704,60cyclictest0-21swapper/109:00:551
843699704,60cyclictest0-21swapper/109:00:551
843699703,61cyclictest0-21swapper/111:16:171
843699696,5cyclictest0-21swapper/110:35:001
843699695,58cyclictest0-21swapper/111:50:291
843699695,58cyclictest0-21swapper/110:50:521
843699695,58cyclictest0-21swapper/108:54:541
843699695,57cyclictest0-21swapper/110:13:221
843699694,8cyclictest0-21swapper/110:12:071
843699694,7cyclictest0-21swapper/111:34:521
843699694,59cyclictest0-21swapper/111:46:091
843699694,58cyclictest0-21swapper/111:05:251
843699694,58cyclictest0-21swapper/110:38:161
843699694,58cyclictest0-21swapper/109:55:171
843699693,33cyclictest0-21swapper/108:11:511
843699684,7cyclictest0-21swapper/112:15:131
843699684,6cyclictest0-21swapper/112:08:571
843699684,58cyclictest0-21swapper/112:04:581
843699684,58cyclictest0-21swapper/111:22:121
843699684,58cyclictest0-21swapper/109:28:281
843699683,7cyclictest0-21swapper/108:22:011
843699683,59cyclictest0-21swapper/111:08:481
843699674,7cyclictest0-21swapper/111:29:071
843699674,7cyclictest0-21swapper/110:45:131
843699674,7cyclictest0-21swapper/110:45:131
843699674,56cyclictest0-21swapper/112:20:081
843699664,27cyclictest0-21swapper/109:59:551
843699663,32cyclictest0-21swapper/108:51:491
8436996527,9cyclictest0-21swapper/107:05:431
843699643,34cyclictest12285-21/usr/sbin/munin08:27:321
843699643,33cyclictest0-21swapper/107:21:571
843699634,31cyclictest0-21swapper/107:41:231
843699634,28cyclictest0-21swapper/108:16:501
843699633,8cyclictest0-21swapper/108:37:531
843699632,7cyclictest10587-21/usr/sbin/munin08:22:351
8436996310,26cyclictest21944-21latency_hist07:27:241
843699623,7cyclictest0-21swapper/108:33:061
843699623,52cyclictest0-21swapper/107:47:221
843699623,30cyclictest0-21swapper/108:42:481
843699622,6cyclictest23817-21latency_hist07:32:241
843699614,27cyclictest0-21swapper/107:47:481
843699604,49cyclictest0-21swapper/107:37:231
843699594,27cyclictest0-21swapper/107:54:161
844399585,47cyclictest0-21swapper/211:05:472
843699583,9cyclictest0-21swapper/108:07:041
843699583,49cyclictest0-21swapper/107:08:461
843699583,29cyclictest0-21swapper/107:16:101
843199574,46cyclictest0-21swapper/010:19:180
791925712,16sleep30-21swapper/306:49:073
843199565,45cyclictest0-21swapper/012:21:460
843199564,45cyclictest0-21swapper/009:06:000
844399553,46cyclictest25430-21ssh11:08:472
845099544,43cyclictest0-21swapper/311:39:373
845099544,43cyclictest0-21swapper/311:39:373
843199544,44cyclictest0-21swapper/009:23:500
843199543,46cyclictest0-21swapper/009:01:100
843199543,46cyclictest0-21swapper/009:01:100
844399534,10cyclictest0-21swapper/207:27:422
844399533,44cyclictest0-21swapper/209:17:462
8431995342,6cyclictest3-21ksoftirqd/008:42:210
843199534,9cyclictest0-21swapper/011:15:170
843199534,43cyclictest0-21swapper/010:02:300
843199534,24cyclictest0-21swapper/008:07:360
843199533,44cyclictest28812-21ssh10:30:220
845099524,42cyclictest0-21swapper/312:08:463
845099524,41cyclictest0-21swapper/309:26:593
844399524,19cyclictest0-21swapper/208:19:092
844399523,44cyclictest0-21swapper/209:55:522
844399523,43cyclictest0-21swapper/209:46:292
843199523,44cyclictest0-21swapper/011:26:570
843199522,7cyclictest11015-21aten_rbpower_vo06:57:330
844399514,41cyclictest0-21swapper/211:22:482
844399514,41cyclictest0-21swapper/210:29:082
844399514,40cyclictest0-21swapper/212:17:062
844399514,40cyclictest0-21swapper/209:02:382
844399513,42cyclictest0-21swapper/211:53:462
844399513,42cyclictest0-21swapper/210:07:392
843199515,39cyclictest0-21swapper/012:13:400
843199514,42cyclictest0-21swapper/008:49:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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