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2026-02-25 - 19:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Wed Feb 25, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
403996051,5cyclictest21-21ksoftirqd/109:39:461
41499584,49cyclictest0-21swapper/308:06:393
40999584,48cyclictest0-21swapper/210:39:242
40999584,48cyclictest0-21swapper/209:30:222
323212579,17sleep00-21swapper/006:26:130
41499562,48cyclictest17073-21unixbench_multi10:00:153
40999565,44cyclictest0-21swapper/209:45:362
409995647,5cyclictest29-21ksoftirqd/210:49:452
40999563,6cyclictest0-21swapper/211:34:412
40999561,49cyclictest30363-21kworker/2:209:28:292
39899566,44cyclictest0-21swapper/011:34:150
398995641,10cyclictest0-21swapper/011:03:240
398995641,10cyclictest0-21swapper/011:03:240
40999553,7cyclictest544-21ssh09:39:462
409995516,34cyclictest14213-21aten_rbpower_cu07:05:032
409995516,34cyclictest14213-21aten_rbpower_cu07:05:032
3227425512,36sleep10-21swapper/106:25:421
41499544,43cyclictest0-21swapper/309:16:063
40999545,43cyclictest0-21swapper/210:52:542
40999544,44cyclictest0-21swapper/210:10:062
40999543,6cyclictest0-21swapper/210:00:052
40999543,45cyclictest29135-21ssh10:17:052
40999543,45cyclictest29135-21ssh10:17:052
41499534,42cyclictest0-21swapper/310:47:233
40999534,43cyclictest0-21swapper/209:01:072
40999534,42cyclictest0-21swapper/211:47:432
40999534,42cyclictest0-21swapper/211:47:432
40999532,5cyclictest12720-21memory09:55:062
39899533,43cyclictest0-21swapper/009:57:360
40999524,9cyclictest0-21swapper/211:00:142
40999524,9cyclictest0-21swapper/211:00:142
40999523,44cyclictest0-21swapper/209:12:142
40999523,43cyclictest11330-21sendmail_mailqu06:55:152
409995214,33cyclictest4604-21latency_hist06:39:512
40399523,9cyclictest0-21swapper/110:58:041
39899524,43cyclictest0-21swapper/010:16:550
39899524,43cyclictest0-21swapper/010:16:550
39899523,5cyclictest0-21swapper/009:40:160
39899523,43cyclictest0-21swapper/011:23:200
41499515,40cyclictest0-21swapper/311:05:243
40999515,39cyclictest0-21swapper/206:45:042
409995114,32cyclictest29-21ksoftirqd/209:50:062
409995112,34cyclictest27111-21crond07:39:492
39899515,38cyclictest0-21swapper/009:33:570
39899513,10cyclictest0-21swapper/008:21:100
398995113,7cyclictest16754-21sshd07:10:110
41499504,40cyclictest0-21swapper/309:32:323
41499503,42cyclictest0-21swapper/310:35:053
41499503,41cyclictest0-21swapper/310:39:553
41499502,42cyclictest2954-21ssh11:52:013
414995010,33cyclictest0-21swapper/310:50:143
40999504,40cyclictest0-21swapper/211:25:422
40999504,40cyclictest0-21swapper/208:46:062
40999504,39cyclictest0-21swapper/211:40:042
40999504,19cyclictest0-21swapper/209:40:262
40999503,41cyclictest0-21swapper/210:09:152
409995012,5cyclictest0-21swapper/209:07:532
409995010,33cyclictest0-21swapper/211:05:122
39899504,39cyclictest0-21swapper/011:42:530
39899503,40cyclictest0-21swapper/006:40:100
398995012,32cyclictest0-21swapper/008:49:110
41499494,39cyclictest0-21swapper/311:30:463
41499494,39cyclictest0-21swapper/309:41:123
41499494,39cyclictest0-21swapper/309:08:253
41499494,39cyclictest0-21swapper/308:45:273
41499494,38cyclictest0-21swapper/311:58:043
41499493,41cyclictest0-21swapper/310:05:543
41499493,41cyclictest0-21swapper/308:40:173
41499493,10cyclictest0-21swapper/310:29:053
414994912,5cyclictest0-21swapper/311:22:173
40999496,37cyclictest0-21swapper/208:51:012
40999495,38cyclictest0-21swapper/210:21:432
40999494,39cyclictest0-21swapper/211:38:292
40999494,39cyclictest0-21swapper/211:12:412
40999494,38cyclictest0-21swapper/211:20:042
40999494,38cyclictest0-21swapper/210:30:522
40999494,38cyclictest0-21swapper/209:15:252
40999494,37cyclictest0-21swapper/210:40:202
40999494,37cyclictest0-21swapper/208:31:072
40999493,41cyclictest0-21swapper/207:50:412
40999493,40cyclictest0-21swapper/211:50:112
409994911,32cyclictest0-21swapper/208:41:322
39899499,15cyclictest0-21swapper/008:50:130
39899496,37cyclictest0-21swapper/010:57:430
39899496,37cyclictest0-21swapper/009:02:080
39899496,37cyclictest0-21swapper/008:58:110
39899495,38cyclictest0-21swapper/007:05:100
39899495,38cyclictest0-21swapper/007:05:100
39899494,40cyclictest0-21swapper/011:11:540
39899494,40cyclictest0-21swapper/010:35:250
39899494,40cyclictest0-21swapper/010:21:550
39899494,38cyclictest0-21swapper/009:51:170
41499489,33cyclictest0-21swapper/309:20:573
41499484,39cyclictest0-21swapper/307:25:033
41499484,38cyclictest0-21swapper/311:45:503
41499484,38cyclictest0-21swapper/311:45:503
41499484,38cyclictest0-21swapper/311:36:023
41499484,38cyclictest0-21swapper/311:12:253
41499484,38cyclictest0-21swapper/310:20:143
41499484,38cyclictest0-21swapper/310:15:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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