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2026-03-04 - 21:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot8.osadl.org (updated Wed Mar 04, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
587506758330irq/54-eth00-21swapper/107:09:161
1858727860sleep00-21swapper/007:08:190
18866996125cyclictest0-21swapper/011:40:120
18866995923cyclictest0-21swapper/012:15:050
18866995923cyclictest0-21swapper/008:00:540
18866995822cyclictest0-21swapper/010:05:060
18866995721cyclictest0-21swapper/011:32:040
18866995721cyclictest0-21swapper/009:16:240
18867995638cyclictest0-21swapper/107:51:201
18867995638cyclictest0-21swapper/107:51:201
18866995620cyclictest3001-21runrttasks11:55:390
18866995620cyclictest0-21swapper/008:08:210
58750550irq/54-eth00-21swapper/108:10:171
58750550irq/54-eth00-21swapper/010:39:340
58750550irq/54-eth00-21swapper/009:40:190
1999550migration/17138-21taskset11:31:121
1999550migration/12984-21taskset07:59:371
1999550migration/125010-21taskset12:26:431
1999550migration/122217-21runrttasks08:58:311
1999550migration/122217-21runrttasks08:58:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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