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2025-08-30 - 03:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Sat Aug 30, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3136327056,8sleep00-21swapper/019:05:360
253002680,1sleep00-21swapper/023:40:370
3148626754,8sleep10-21swapper/119:06:541
312912660,1sleep031289-21seq23:02:410
287782610,0sleep028779-21ssh23:45:380
84152560,2sleep13171399cyclictest00:02:411
31713994510,29cyclictest0-21swapper/100:27:401
31713994510,25cyclictest0-21swapper/123:26:331
31713994410,33cyclictest0-21swapper/122:31:571
31713994310,32cyclictest0-21swapper/121:13:331
31713994110,30cyclictest12039-21ls00:07:451
31713994110,30cyclictest0-21swapper/123:50:091
31713994110,30cyclictest0-21swapper/122:46:541
31713994110,30cyclictest0-21swapper/120:05:571
31713994110,30cyclictest0-21swapper/100:36:291
31713994010,8cyclictest0-21swapper/121:47:361
31713994010,29cyclictest0-21swapper/121:41:441
31713994010,29cyclictest0-21swapper/100:00:241
31713993910,28cyclictest0-21swapper/122:33:011
31713993910,28cyclictest0-21swapper/120:27:411
31713993910,28cyclictest0-21swapper/100:13:411
31713993810,4cyclictest0-21swapper/122:56:191
31713993810,27cyclictest0-21swapper/123:46:531
31713993810,27cyclictest0-21swapper/122:47:381
31713993810,27cyclictest0-21swapper/122:17:131
31713993810,27cyclictest0-21swapper/122:04:251
31713993810,27cyclictest0-21swapper/122:01:341
31713993721,15cyclictest0-21swapper/122:59:241
31713993710,26cyclictest0-21swapper/123:13:151
31713993710,26cyclictest0-21swapper/123:09:021
31713993710,26cyclictest0-21swapper/121:17:401
31713993610,26cyclictest0-21swapper/120:43:101
31713993610,25cyclictest0-21swapper/120:24:211
31713993610,25cyclictest0-21swapper/119:39:531
31713993610,25cyclictest0-21swapper/100:17:521
31713993510,25cyclictest0-21swapper/123:34:041
31713993510,25cyclictest0-21swapper/122:42:151
31713993510,25cyclictest0-21swapper/119:18:001
31713993510,24cyclictest0-21swapper/123:37:341
31713993510,24cyclictest0-21swapper/122:09:521
31713993510,24cyclictest0-21swapper/120:07:251
31713993510,22cyclictest0-21swapper/121:23:561
31712993510,2cyclictest0-21swapper/023:16:040
31713993413,20cyclictest97750irq/106-eth1-rx21:42:511
31713993410,24cyclictest0-21swapper/122:18:391
31713993410,23cyclictest0-21swapper/123:27:481
31713993410,23cyclictest0-21swapper/122:23:001
31713993410,23cyclictest0-21swapper/120:37:431
31713993410,23cyclictest0-21swapper/100:25:241
31713993313,19cyclictest0-21swapper/119:32:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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