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2026-02-18 - 17:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Wed Feb 18, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
126112940,0sleep00-21swapper/012:14:470
2392127155,8sleep00-21swapper/007:09:100
2357226956,8sleep10-21swapper/107:05:341
24140993910,2cyclictest0-21swapper/112:24:371
24139992826,1cyclictest6556-21sshd09:53:420
24140992617,6cyclictest1689-21apache211:28:401
2414099260,25cyclictest18059-21kworker/u4:110:32:431
24139992619,5cyclictest1689-21apache207:49:450
2413999261,1cyclictest28463-21ssh12:34:570
2414099252,22cyclictest0-21swapper/110:39:431
24140992520,4cyclictest231ktimersoftd/107:59:451
24140992516,6cyclictest1689-21apache211:13:501
24140992510,6cyclictest0-21swapper/110:23:351
24139992511,4cyclictest0-21swapper/010:54:500
24140992410,10cyclictest0-21swapper/111:48:391
2414099240,3cyclictest0-21swapper/112:04:531
2414099240,19cyclictest0-21swapper/111:00:131
24140992322,1cyclictest1689-21apache210:51:151
24140992317,3cyclictest590-21rs:main1
24140992311,6cyclictest19113-21awk10:09:541
24140992310,5cyclictest0-21swapper/112:19:461
24140992310,5cyclictest0-21swapper/112:01:461
24140992310,12cyclictest0-21swapper/109:02:231
2414099230,14cyclictest744-21snmpd07:54:371
24139992321,1cyclictest636-21nscd11:48:240
24139992310,5cyclictest0-21swapper/011:20:300
24139992310,3cyclictest0-21swapper/011:10:090
2414099227,8cyclictest0-21swapper/108:49:531
2414099224,13cyclictest0-21swapper/107:39:481
2414099224,12cyclictest0-21swapper/110:34:461
2414099224,11cyclictest0-21swapper/108:29:491
2414099224,11cyclictest0-21swapper/108:14:521
24140992218,3cyclictest1666-21apache211:23:131
24140992217,3cyclictest1666-21apache209:18:321
24140992210,6cyclictest0-21swapper/111:18:591
24139992217,4cyclictest1689-21apache211:42:500
24139992217,4cyclictest1689-21apache210:23:250
24139992216,5cyclictest1666-21apache211:07:460
24139992210,7cyclictest0-21swapper/010:29:500
2413999220,1cyclictest15040-21latency_hist08:09:340
2413999220,1cyclictest0-21swapper/012:19:350
2413999220,14cyclictest0-21swapper/011:28:330
2414099214,6cyclictest1199-21runrttasks08:25:221
2414099212,13cyclictest0-21swapper/109:59:491
24140992121,0cyclictest0-21swapper/109:47:361
24140992120,1cyclictest1666-21apache211:39:071
24140992118,3cyclictest1689-21apache210:17:031
24140992110,7cyclictest0-21swapper/111:05:451
24140992110,6cyclictest0-21swapper/110:56:021
24140992110,1cyclictest0-21swapper/108:48:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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