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2026-07-17 - 03:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Thu Jul 16, 2026 12:49:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
250799358161,1cyclictest151rcu_preempt11:48:1311
3273913150,307ptp4l0-21swapper/107:09:371
25029928689,1cyclictest151rcu_preempt11:55:0710
25139918053,126cyclictest0-21swapper/2110:48:5514
25279916919,97cyclictest0-21swapper/2411:05:2117
25279916918,109cyclictest0-21swapper/2408:30:2117
25139915931,111cyclictest0-21swapper/2112:33:4114
330891158148,7phc2sys0-21swapper/207:05:2112
25139915831,77cyclictest0-21swapper/2109:44:4714
245299158155,0cyclictest76-21ksoftirqd/1011:22:252
25139915729,98cyclictest0-21swapper/2112:35:1814
25139915729,98cyclictest0-21swapper/2112:35:1714
24049915522,65cyclictest151rcu_preempt09:10:180
25279915118,92cyclictest0-21swapper/2410:55:1117
25139915123,97cyclictest0-21swapper/2111:41:5014
24529915154,68cyclictest0-21swapper/1009:25:232
25139914832,73cyclictest0-21swapper/2110:54:4314
25139914828,67cyclictest0-21swapper/2110:22:4414
250799148145,2cyclictest151rcu_preempt11:50:5111
25279914718,78cyclictest0-21swapper/2409:35:0217
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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