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2026-04-30 - 01:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Wed Apr 29, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491233166,22phc2sys0-21swapper/307:09:143
137412233190,33sleep20-21swapper/207:06:002
139032210182,18sleep10-21swapper/107:07:591
138812200167,22sleep00-21swapper/007:07:420
207621730,3sleep31435299cyclictest07:50:163
275672600,6sleep327570-21df_abs12:05:143
139391600,1ptp4l401ktimersoftd/311:26:413
281712540,5sleep11435099cyclictest11:00:011
139391510,1ptp4l401ktimersoftd/307:15:033
288532500,1sleep30-21swapper/308:45:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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