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2026-03-01 - 13:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Feb 28, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181692230162,23sleep20-21swapper/207:09:062
139491206172,23phc2sys0-21swapper/307:06:193
182342204170,23sleep00-21swapper/007:09:520
182432203171,21sleep10-21swapper/107:09:571
97921450,5sleep11853999cyclictest11:00:261
1853999566,8cyclictest24957-21unixbench_singl11:50:271
1853999557,7cyclictest21475-21grep07:15:151
1853999546,6cyclictest14925-21sh12:40:001
230342530,4sleep123032-21perf11:50:011
1853999535,6cyclictest0-21swapper/112:15:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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