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2025-12-14 - 03:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sun Dec 14, 2025 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
194642214180,22sleep20-21swapper/219:07:342
193152211178,22sleep00-21swapper/019:05:430
193132211177,23sleep30-21swapper/319:05:433
194632208176,21sleep10-21swapper/119:07:341
11432790,2sleep30-21swapper/319:35:303
311452640,5sleep11994199cyclictest20:40:201
110532610,2sleep30-21swapper/322:10:313
1394916040,11phc2sys0-21swapper/319:10:013
112032560,1sleep00-21swapper/000:25:350
26342510,3sleep3391rcuc/319:40:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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