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2025-11-16 - 23:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sun Nov 16, 2025 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191203169,22phc2sys0-21swapper/307:06:353
279362202168,23sleep00-21swapper/007:09:040
279332201168,22sleep20-21swapper/207:09:022
279072200167,22sleep10-21swapper/107:08:411
2375921560,3sleep32831799cyclictest12:35:283
298792600,5sleep329877-21tail09:25:463
28316995825,4cyclictest33-21ksoftirqd/207:25:002
297092550,2sleep20-21swapper/209:25:452
28316995322,4cyclictest33-21ksoftirqd/208:45:002
136991530,1ptp4l401ktimersoftd/311:05:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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