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2026-03-06 - 03:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Mar 06, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304162230162,22sleep20-21swapper/219:05:572
305982204171,21sleep00-21swapper/019:08:120
303952204171,22sleep10-21swapper/119:05:401
139491203169,23phc2sys0-21swapper/319:09:163
96472720,2sleep00-21swapper/000:00:280
96472720,2sleep00-21swapper/000:00:280
139391680,1ptp4l4027-21irqstats23:50:203
134391620,1getstats0-21swapper/323:40:283
3102899570,17cyclictest4331-21/usr/sbin/munin21:35:232
3102899570,17cyclictest21610-21/usr/sbin/munin19:55:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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