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2026-04-16 - 23:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Apr 16, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491205170,24phc2sys0-21swapper/307:08:153
139491205170,24phc2sys0-21swapper/307:08:153
26252204171,22sleep20-21swapper/207:06:222
26252204171,22sleep20-21swapper/207:06:222
26192203170,22sleep10-21swapper/107:06:161
26192203170,22sleep10-21swapper/107:06:161
28922201168,22sleep00-21swapper/007:09:410
28922201168,22sleep00-21swapper/007:09:410
3210997510,19cyclictest13831-21date12:00:012
321099710,31cyclictest29040-21sshd11:21:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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