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2026-03-28 - 09:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Mar 28, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491230164,22phc2sys0-21swapper/319:07:523
42762203171,21sleep10-21swapper/119:06:271
23732203169,23sleep20-21swapper/219:05:122
23662201168,22sleep00-21swapper/019:05:060
45502163124,13sleep10-21swapper/119:10:011
1961021540,6sleep0484199cyclictest00:10:100
1454521500,6sleep3484499cyclictest00:00:143
1454521500,6sleep3484499cyclictest00:00:133
1570421460,7sleep2484399cyclictest22:55:132
1394918262,11phc2sys0-21swapper/319:10:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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