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2026-01-05 - 07:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Jan 05, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2025422350,5sleep30-21swapper/319:05:273
206552205172,22sleep20-21swapper/219:07:042
208382201168,22sleep00-21swapper/019:09:270
206842199166,22sleep10-21swapper/119:07:271
21176997531,9cyclictest25-21ksoftirqd/100:09:591
21177996729,4cyclictest33-21ksoftirqd/223:25:222
21176996230,3cyclictest25-21ksoftirqd/121:15:141
21176996219,5cyclictest25-21ksoftirqd/119:20:271
21175996227,7cyclictest9-21ksoftirqd/021:10:240
21176996131,3cyclictest25-21ksoftirqd/120:15:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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