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2026-06-15 - 12:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Jun 15, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491237171,22phc2sys0-21swapper/319:08:513
189252206172,22sleep10-21swapper/119:07:081
188602203170,22sleep20-21swapper/219:06:252
188582200166,22sleep00-21swapper/019:06:230
57212630,2sleep00-21swapper/000:15:270
19437996130,6cyclictest9-21ksoftirqd/020:15:250
19437996130,6cyclictest9-21ksoftirqd/020:15:240
1944099605,18cyclictest19684-21unixbench_singl22:30:293
1944099605,18cyclictest19684-21unixbench_singl22:30:293
19437996027,7cyclictest9-21ksoftirqd/022:00:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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