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2026-05-02 - 01:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri May 01, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491205172,22phc2sys0-21swapper/307:07:313
139772202169,22sleep20-21swapper/207:07:332
139762202169,22sleep10-21swapper/107:07:331
140632198165,22sleep00-21swapper/007:08:390
139391750,1ptp4l391rcuc/309:20:223
1446799700,2cyclictest0-21swapper/110:16:131
14466996812,16cyclictest18340-21cat07:15:260
66412620,2sleep00-21swapper/009:05:250
1446899621,58cyclictest21363-21kworker/2:109:05:242
1446799620,60cyclictest0-21swapper/110:21:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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