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2026-02-25 - 19:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Wed Feb 25, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491220192,19phc2sys0-21swapper/307:09:593
172752208175,22sleep10-21swapper/107:08:201
171062200168,21sleep20-21swapper/207:06:082
171242195161,22sleep00-21swapper/007:06:220
2932721470,6sleep01770599cyclictest10:55:240
2932721470,6sleep01770599cyclictest10:55:230
17705997527,4cyclictest9-21ksoftirqd/011:05:000
17708996330,3cyclictest41-21ksoftirqd/308:50:003
17708996322,7cyclictest41-21ksoftirqd/312:15:193
17705996316,3cyclictest9-21ksoftirqd/009:05:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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