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2026-07-09 - 23:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Jul 09, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491235168,22phc2sys0-21swapper/307:09:013
64852232168,22sleep20-21swapper/207:06:032
67242202169,22sleep00-21swapper/007:09:100
64892202169,22sleep10-21swapper/107:06:051
2049821310,2sleep20-21swapper/212:05:242
80712640,3sleep10-21swapper/107:10:181
7092996334,3cyclictest41-21ksoftirqd/312:05:233
7092996025,4cyclictest41-21ksoftirqd/311:00:013
7092995820,8cyclictest41-21ksoftirqd/311:25:003
32362580,3sleep30-21swapper/310:25:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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