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2025-10-23 - 12:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Oct 23, 2025 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191207170,25phc2sys0-21swapper/319:08:413
168752202168,23sleep00-21swapper/019:07:460
169532201167,22sleep10-21swapper/119:08:491
167262201168,22sleep20-21swapper/219:05:522
1760021340,3sleep21734399cyclictest20:15:242
1704828262,11sleep10-21swapper/119:10:021
17344996832,10cyclictest41-21ksoftirqd/322:40:003
17344996529,10cyclictest41-21ksoftirqd/319:45:013
17344996130,8cyclictest41-21ksoftirqd/300:20:013
17344996129,9cyclictest41-21ksoftirqd/300:25:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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