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2026-02-27 - 10:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Feb 27, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184012234168,22sleep00-21swapper/019:06:520
139491206172,23phc2sys0-21swapper/319:06:403
185872205172,22sleep10-21swapper/119:09:181
182962203171,21sleep20-21swapper/219:05:372
240292920,4sleep30-21swapper/323:50:123
240292920,4sleep30-21swapper/323:50:113
139391900,1ptp4l17014-21sed21:20:143
139391900,1ptp4l17014-21sed21:20:133
1893799700,29cyclictest13391-21date00:35:013
1893799671,23cyclictest5055-21df_abs20:55:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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