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2025-11-18 - 03:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Nov 18, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
45112206173,22sleep10-21swapper/119:07:281
44312204171,22sleep30-21swapper/319:06:263
43802201168,22sleep20-21swapper/219:05:452
45902199165,23sleep00-21swapper/019:08:200
3216321630,5sleep2501399cyclictest22:20:012
274302660,1sleep20-21swapper/200:25:022
501399605,23cyclictest29928-21cat20:00:182
5012996032,3cyclictest25-21ksoftirqd/121:25:311
5012995426,4cyclictest25-21ksoftirqd/120:45:191
5012995421,8cyclictest25-21ksoftirqd/123:45:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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