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2026-03-26 - 08:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Mar 26, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
133372203170,22sleep10-21swapper/119:06:411
134932202169,22sleep20-21swapper/219:08:432
134642202169,22sleep00-21swapper/019:08:200
133392202168,23sleep30-21swapper/319:06:433
1394918261,11phc2sys0-21swapper/319:10:003
139391650,2ptp4l401ktimersoftd/323:00:143
139391650,1ptp4l401ktimersoftd/321:24:313
13888996312,49cyclictest30316-21kworker/2:100:15:332
1388699625,16cyclictest0-21swapper/021:55:010
13886996010,10cyclictest29634-21grep21:55:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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