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2026-03-02 - 02:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sun Mar 01, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
213412230163,22sleep00-21swapper/007:08:090
212592213170,32sleep10-21swapper/107:07:061
139491203169,23phc2sys0-21swapper/307:08:453
212252197164,22sleep20-21swapper/207:06:382
139491164125,13phc2sys0-21swapper/307:10:013
309932630,1sleep30-21swapper/312:00:113
2178499628,16cyclictest8277-21sh07:50:020
2178499608,14cyclictest6090-21awk08:50:240
2178799593,18cyclictest14185-21irqstats08:00:173
21786995819,5cyclictest33-21ksoftirqd/210:45:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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