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2025-12-08 - 06:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Dec 08, 2025 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1216723890,10sleep125-21ksoftirqd/119:07:021
1216723890,10sleep125-21ksoftirqd/119:07:021
137191205170,23phc2sys0-21swapper/319:09:073
137191205170,23phc2sys0-21swapper/319:09:073
123742204170,22sleep20-21swapper/219:09:382
123742204170,22sleep20-21swapper/219:09:382
121982202168,22sleep00-21swapper/019:07:190
121982202168,22sleep00-21swapper/019:07:190
2233921410,7sleep21269899cyclictest23:59:452
136991800,1ptp4l8193-21fschecks_count21:15:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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