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2026-02-28 - 11:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Feb 28, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491233167,22phc2sys0-21swapper/319:06:033
318382203169,23sleep20-21swapper/219:08:082
317282203169,23sleep00-21swapper/019:06:410
316512202168,22sleep10-21swapper/119:05:411
6892820,4sleep3401ktimersoftd/321:25:153
139391780,1ptp4l391rcuc/322:20:163
32424997514,19cyclictest23735-21awk00:25:273
32424997114,17cyclictest32587-21awk22:30:203
32424997012,18cyclictest14945-21sort23:00:243
32424997012,13cyclictest24480-21cpuspeed_turbos00:30:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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