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2026-04-10 - 05:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Apr 10, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299422213179,22sleep20-21swapper/219:08:512
299422213179,22sleep20-21swapper/219:08:512
139491206173,22phc2sys0-21swapper/319:05:483
139491206173,22phc2sys0-21swapper/319:05:473
300022202169,22sleep00-21swapper/019:09:370
300022202169,22sleep00-21swapper/019:09:370
296992200166,22sleep10-21swapper/119:05:481
296992200166,22sleep10-21swapper/119:05:471
499321310,4sleep23032599cyclictest20:30:212
92832670,4sleep341-21ksoftirqd/321:45:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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