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2026-02-26 - 21:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Feb 26, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
309852226164,51sleep00-21swapper/007:08:020
139491205171,23phc2sys0-21swapper/307:09:213
309912200168,21sleep10-21swapper/107:08:081
309102200168,21sleep20-21swapper/207:07:032
3114529470,13sleep20-21swapper/207:10:012
286692750,2sleep10-21swapper/110:25:151
139391730,1ptp4l12580-21awk12:05:213
206462700,3sleep220609-21cron10:10:002
3143899596,10cyclictest8773-21latency_hist12:00:012
3143899594,16cyclictest0-21swapper/210:35:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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