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2026-03-19 - 17:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Mar 19, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491227199,19phc2sys0-21swapper/307:08:583
210552206171,23sleep20-21swapper/207:06:042
199032206166,30sleep10-21swapper/107:05:191
211062202169,22sleep00-21swapper/007:06:420
199721400,7sleep12165799cyclictest09:50:171
3112821390,5sleep02165699cyclictest07:30:010
139391760,1ptp4l391rcuc/311:25:223
21659996625,8cyclictest41-21ksoftirqd/308:10:003
21659996529,4cyclictest41-21ksoftirqd/312:40:003
21659996428,8cyclictest41-21ksoftirqd/311:20:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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