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2026-02-21 - 07:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Feb 21, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491231164,23phc2sys0-21swapper/319:08:023
296052206172,23sleep20-21swapper/219:07:512
296032203168,23sleep00-21swapper/019:07:490
295172202170,21sleep10-21swapper/119:06:421
1442221530,6sleep23007099cyclictest21:59:592
307062610,3sleep1231rcuc/121:25:131
239842600,2sleep20-21swapper/221:10:182
295582590,7sleep03006899cyclictest23:35:260
33092550,2sleep30-21swapper/323:50:163
231642530,5sleep223165-21ptp4l22:15:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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