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2026-03-29 - 05:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sun Mar 29, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
178512233166,22sleep20-21swapper/219:09:162
176832205172,22sleep10-21swapper/119:07:091
175952205172,22sleep00-21swapper/019:06:010
139491204170,22phc2sys0-21swapper/319:07:423
1664621860,7sleep11820299cyclictest20:10:271
2514421790,6sleep01820199cyclictest21:35:270
1393911120,88ptp4l0-21swapper/319:10:003
224762650,2sleep30-21swapper/321:30:243
139391640,1ptp4l401ktimersoftd/323:43:043
199042630,7sleep01820199cyclictest22:35:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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