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2026-02-03 - 16:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Feb 03, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205392208175,22sleep20-21swapper/207:07:042
205392208175,22sleep20-21swapper/207:07:042
206312204171,22sleep10-21swapper/107:08:151
206312204171,22sleep10-21swapper/107:08:151
206032203170,22sleep30-21swapper/307:07:533
206032203170,22sleep30-21swapper/307:07:533
204442202169,22sleep00-21swapper/007:05:490
204442202169,22sleep00-21swapper/007:05:490
2872221230,1sleep20-21swapper/208:35:212
2872221230,1sleep20-21swapper/208:35:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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