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2026-03-22 - 17:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sun Mar 22, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491211177,22phc2sys0-21swapper/307:07:043
141492207174,22sleep10-21swapper/107:08:291
140292202168,22sleep00-21swapper/007:06:540
140882201168,22sleep20-21swapper/207:07:402
2014921600,1sleep00-21swapper/010:45:010
14571996628,10cyclictest33-21ksoftirqd/208:30:182
14571996432,5cyclictest33-21ksoftirqd/210:15:232
14571996330,4cyclictest33-21ksoftirqd/207:50:272
14571996232,4cyclictest33-21ksoftirqd/208:40:182
14571996230,6cyclictest33-21ksoftirqd/207:15:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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