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2026-01-19 - 08:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Jan 19, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491230163,22phc2sys0-21swapper/319:07:573
118812205170,23sleep20-21swapper/219:09:102
117712201169,21sleep10-21swapper/119:07:461
117922197164,22sleep00-21swapper/019:08:000
1594521150,1sleep00-21swapper/022:40:130
1594521150,1sleep00-21swapper/022:40:130
1223899719,60cyclictest0-21swapper/123:55:531
181942490,2sleep10-21swapper/120:30:001
57898460,2rtkit-daemon0-21swapper/320:25:183
139391440,0ptp4l401ktimersoftd/321:52:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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