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2026-01-31 - 15:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Jan 31, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
107402227200,18sleep10-21swapper/119:09:591
139491208173,24phc2sys0-21swapper/319:08:433
104802203169,23sleep00-21swapper/019:06:360
104222203170,22sleep20-21swapper/219:05:582
986621290,3sleep20-21swapper/220:15:012
227202740,3sleep022721-21dump-pmu-power19:35:010
185742630,6sleep218576-21switchtime22:45:242
139391530,1ptp4l401ktimersoftd/320:07:363
134391530,2getstats0-21swapper/300:20:013
270972500,1sleep00-21swapper/000:10:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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