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2025-07-12 - 12:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Jul 12, 2025 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39892206172,22sleep10-21swapper/119:07:381
137191205170,23phc2sys0-21swapper/319:07:013
39832202168,23sleep00-21swapper/019:07:320
39532202169,22sleep20-21swapper/219:07:102
192992720,2sleep00-21swapper/020:45:240
169352630,8sleep1446499cyclictest00:05:001
446499555,3cyclictest244822chrt20:56:051
4464995145,3cyclictest25813-21sh19:55:011
27312510,2sleep30-21swapper/321:20:183
446699501,16cyclictest27478-21/usr/sbin/munin21:05:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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