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2025-11-21 - 04:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Nov 21, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191228164,52phc2sys0-21swapper/319:06:593
325032202169,22sleep20-21swapper/219:06:012
325362201168,22sleep00-21swapper/019:06:270
325322201168,22sleep10-21swapper/119:06:241
1561821760,6sleep392699cyclictest23:00:133
2932521580,6sleep292499cyclictest23:25:282
3090621350,5sleep392699cyclictest21:15:273
2180721240,2sleep10-21swapper/122:05:151
621621180,3sleep30-21swapper/319:20:143
924997412,25cyclictest25076-21sed00:25:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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