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2025-12-22 - 15:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Dec 22, 2025 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33392203168,23sleep30-21swapper/307:06:203
33392203168,23sleep30-21swapper/307:06:203
33372203170,22sleep10-21swapper/107:06:181
33372203170,22sleep10-21swapper/107:06:181
33292202169,22sleep00-21swapper/007:06:140
33292202169,22sleep00-21swapper/007:06:140
34972200167,22sleep20-21swapper/207:08:252
34972200167,22sleep20-21swapper/207:08:252
36192162123,13sleep10-21swapper/107:10:001
139391760,0ptp4l391rcuc/310:15:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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