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2026-02-24 - 13:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Feb 24, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491221156,22phc2sys0-21swapper/319:06:483
208952203169,23sleep10-21swapper/119:06:471
210452202170,22sleep20-21swapper/219:08:372
210112198166,22sleep00-21swapper/019:08:110
1218921820,4sleep32158699cyclictest21:05:153
2769621370,6sleep02158299cyclictest22:45:000
139391840,1ptp4l23025-21cpuspeed22:35:133
139391570,1ptp4l401ktimersoftd/321:46:303
2158499480,46cyclictest0-21swapper/100:36:041
2158499470,45cyclictest0-21swapper/119:35:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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