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2025-12-05 - 04:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Dec 05, 2025 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
109922209162,35sleep00-21swapper/019:07:590
90122203169,23sleep10-21swapper/119:05:061
90152202168,22sleep30-21swapper/319:05:083
109942202168,23sleep20-21swapper/219:08:012
1764721170,4sleep21144399cyclictest19:20:232
11441996432,3cyclictest9-21ksoftirqd/020:20:000
11442996228,9cyclictest25-21ksoftirqd/122:15:011
11442996228,10cyclictest25-21ksoftirqd/122:30:231
263992600,3sleep31144499cyclictest00:10:053
263992600,3sleep31144499cyclictest00:10:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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