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2026-02-17 - 06:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Feb 17, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
327092205176,19sleep30-21swapper/319:07:593
327082203170,22sleep20-21swapper/219:07:572
325602203170,22sleep00-21swapper/019:06:060
327392201168,22sleep10-21swapper/119:08:211
139391950,1ptp4l32148-21taskset22:28:343
54832600,4sleep30-21swapper/320:25:173
139391590,1ptp4l401ktimersoftd/323:20:143
139391560,1ptp4l401ktimersoftd/320:50:283
735995419,7cyclictest41-21ksoftirqd/320:34:593
49772540,2sleep20-21swapper/221:30:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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