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2026-02-02 - 09:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Feb 02, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491209175,22phc2sys0-21swapper/319:05:023
209292200168,22sleep10-21swapper/119:09:331
188292199166,22sleep20-21swapper/219:05:072
209582196162,23sleep00-21swapper/019:09:550
139391570,1ptp4l401ktimersoftd/320:00:113
92082560,1sleep10-21swapper/123:20:201
139391550,1ptp4l401ktimersoftd/322:15:173
312722520,4sleep22125799cyclictest00:05:212
21258994538,4cyclictest1249-21cron21:54:593
21256994436,5cyclictest25-21ksoftirqd/120:05:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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