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2026-03-18 - 18:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Wed Mar 18, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73112227168,48sleep10-21swapper/107:06:091
72872208174,22sleep20-21swapper/207:05:502
72782199164,23sleep30-21swapper/307:05:433
75142197164,22sleep00-21swapper/007:08:420
297942570,7sleep0790699cyclictest09:00:250
13732560,3sleep11377-21irqrtprio09:10:171
250592530,4sleep325061-21needreboot11:05:203
182872520,1sleep10-21swapper/109:45:191
139391510,1ptp4l401ktimersoftd/311:17:013
139391510,1ptp4l401ktimersoftd/311:17:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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