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2026-03-02 - 18:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Mar 02, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491223160,51phc2sys0-21swapper/307:05:103
302402203170,22sleep20-21swapper/207:09:542
302342201169,22sleep10-21swapper/107:09:501
300882196163,22sleep00-21swapper/007:07:560
590621360,6sleep13054599cyclictest11:55:191
17862780,1sleep20-21swapper/207:15:222
139391430,0ptp4l401ktimersoftd/310:31:473
139391430,0ptp4l401ktimersoftd/307:29:383
30546994223,17cyclictest33-21ksoftirqd/209:30:002
30546994223,16cyclictest33-21ksoftirqd/208:05:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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