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2026-01-03 - 13:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Jan 03, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
308542203170,22sleep10-21swapper/119:09:061
139491203170,22phc2sys0-21swapper/319:08:583
309072202167,23sleep20-21swapper/219:09:472
306832202168,22sleep00-21swapper/019:06:510
31217996912,18cyclictest27925-21sed22:25:140
3121799590,26cyclictest8554-21/usr/sbin/munin00:00:220
172532580,6sleep13121899cyclictest00:15:241
172532580,6sleep13121899cyclictest00:15:241
139391570,1ptp4l401ktimersoftd/323:36:523
139391560,1ptp4l401ktimersoftd/319:40:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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