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2026-08-24 - 11:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Aug 24, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
986124440,3sleep1241ktimersoftd/119:05:261
103522238193,34sleep30-21swapper/319:07:593
104432202169,22sleep20-21swapper/219:09:102
83742201167,23sleep00-21swapper/019:05:060
1394918363,11phc2sys0-21swapper/319:10:023
1050928262,11sleep00-21swapper/019:10:000
1080099694,9cyclictest9-21ksoftirqd/020:10:000
10800996732,4cyclictest9-21ksoftirqd/000:05:000
10800996426,10cyclictest9-21ksoftirqd/022:20:250
10800995926,4cyclictest9-21ksoftirqd/023:05:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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