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2026-02-10 - 16:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Feb 10, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491208175,22phc2sys0-21swapper/307:06:183
89742202169,22sleep20-21swapper/207:09:072
89722202168,23sleep00-21swapper/007:09:060
87642202169,22sleep10-21swapper/107:06:301
904228866,12sleep20-21swapper/207:10:012
9335997412,60cyclictest5067-21kworker/2:009:30:332
9335996315,45cyclictest7427-21kworker/2:212:05:332
139391620,1ptp4l401ktimersoftd/311:21:553
9334996023,6cyclictest25-21ksoftirqd/108:40:161
933599583,52cyclictest12433-21kworker/2:210:50:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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