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2026-08-27 - 11:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Aug 27, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491231170,49phc2sys0-21swapper/319:09:133
218062229169,49sleep20-21swapper/219:09:002
217262226198,18sleep10-21swapper/119:07:591
215982201168,22sleep00-21swapper/019:06:160
3246321490,6sleep22232099cyclictest22:50:242
648121370,5sleep02231899cyclictest00:10:260
37662550,1sleep10-21swapper/119:35:271
139391510,1ptp4l401ktimersoftd/323:50:473
139391510,1ptp4l401ktimersoftd/300:23:183
139391510,1ptp4l401ktimersoftd/300:23:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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