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2026-02-11 - 05:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Wed Feb 11, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
90602206173,22sleep20-21swapper/219:07:312
92422204171,22sleep00-21swapper/019:09:540
90072202168,22sleep10-21swapper/119:06:481
89162201168,22sleep30-21swapper/319:05:383
2387021550,5sleep0954399cyclictest21:54:590
2211021380,4sleep2954599cyclictest19:35:172
9543997110,19cyclictest25705-21cut20:50:190
954399660,3cyclictest3169-21latency_hist20:05:010
954399650,2cyclictest29569-21latency_hist21:00:000
9544995925,4cyclictest25-21ksoftirqd/100:20:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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