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2025-11-13 - 20:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Nov 13, 2025 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64702229168,50sleep10-21swapper/107:06:101
137191209174,23phc2sys0-21swapper/307:06:513
64662202169,22sleep20-21swapper/207:06:082
66452199164,23sleep00-21swapper/007:08:280
7065997841,3cyclictest33-21ksoftirqd/210:29:072
91882750,4sleep29191-21fschecks_time11:40:162
7065997035,6cyclictest33-21ksoftirqd/211:03:342
136991650,1ptp4l401ktimersoftd/312:08:223
136991630,1ptp4l401ktimersoftd/310:02:533
7065996230,7cyclictest33-21ksoftirqd/208:04:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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