You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-06 - 20:47
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Nov 06, 2025 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299452225160,22sleep30-21swapper/307:06:463
300932205172,22sleep20-21swapper/207:08:432
301172200167,22sleep00-21swapper/007:09:010
299582199166,22sleep10-21swapper/107:06:561
1371918263,10phc2sys0-21swapper/307:10:013
157062590,4sleep03049099cyclictest07:45:190
30493995120,3cyclictest41-21ksoftirqd/312:00:003
30490994942,4cyclictest4374-21basename10:45:010
59298470,11rtkit-daemon0-21swapper/311:22:253
30493994715,7cyclictest41-21ksoftirqd/309:10:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional