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2026-03-03 - 22:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Mar 03, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
687922270,7sleep00-21swapper/007:05:140
85952203172,20sleep20-21swapper/207:09:192
84172203170,22sleep10-21swapper/107:07:051
84762202168,22sleep30-21swapper/307:07:513
38322570,2sleep20-21swapper/208:05:142
182642510,2sleep30-21swapper/310:50:143
18222470,2sleep10-21swapper/108:00:201
139391440,1ptp4l401ktimersoftd/309:00:533
8942994034,3cyclictest25-21ksoftirqd/112:20:001
139391400,1ptp4l401ktimersoftd/309:24:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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