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2026-02-23 - 12:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Feb 23, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
204522202168,23sleep20-21swapper/219:09:322
204442202169,22sleep10-21swapper/119:09:281
202422202168,23sleep30-21swapper/319:06:493
202442200167,22sleep00-21swapper/019:06:490
1077921760,6sleep22083699cyclictest22:10:122
121932670,5sleep312195-21irqrtprio00:25:203
20837996529,5cyclictest41-21ksoftirqd/300:05:253
20837996323,11cyclictest41-21ksoftirqd/319:10:233
20837996226,4cyclictest41-21ksoftirqd/322:05:003
20837996129,7cyclictest41-21ksoftirqd/321:20:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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