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2026-06-27 - 17:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Jun 27, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491229164,22phc2sys0-21swapper/307:06:453
140942226198,19sleep10-21swapper/107:09:591
138782204171,22sleep00-21swapper/007:07:160
138502204171,22sleep20-21swapper/207:06:542
170521700,6sleep31439199cyclictest12:20:143
70721550,6sleep11438999cyclictest10:00:261
14389997315,9cyclictest15579-21awk08:20:001
14391997121,5cyclictest41-21ksoftirqd/312:25:153
14391997028,9cyclictest41-21ksoftirqd/310:00:133
14389997012,12cyclictest26348-21latency_hist12:05:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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