You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-02 - 06:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Mar 02, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207173,22phc2sys0-21swapper/319:06:513
79072204170,23sleep20-21swapper/219:09:192
77222203169,22sleep10-21swapper/119:06:531
77562201168,22sleep00-21swapper/019:07:200
1394919368,13phc2sys0-21swapper/319:10:013
8254998334,3cyclictest25-21ksoftirqd/123:19:591
153802730,1sleep00-21swapper/019:25:010
8256995928,7cyclictest41-21ksoftirqd/322:32:093
8256995828,9cyclictest41-21ksoftirqd/320:40:003
8256995827,10cyclictest41-21ksoftirqd/300:30:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional