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2026-04-27 - 00:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sun Apr 26, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48152204171,22sleep30-21swapper/307:08:203
46702204171,22sleep20-21swapper/207:06:272
49232201168,22sleep10-21swapper/107:09:381
47502201168,22sleep00-21swapper/007:07:280
2006121730,5sleep0524399cyclictest07:40:170
139391650,53ptp4l0-21swapper/307:10:003
139391640,1ptp4l401ktimersoftd/307:45:383
184612620,3sleep2311rcuc/208:45:142
294442580,4sleep229448-21cpuspeed_turbos08:00:132
139391580,1ptp4l401ktimersoftd/312:10:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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