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2026-04-06 - 22:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Apr 06, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
145772234168,21sleep20-21swapper/207:06:582
139491232169,51phc2sys0-21swapper/307:07:033
147402204170,23sleep00-21swapper/007:09:040
144992202170,21sleep10-21swapper/107:05:561
139391800,1ptp4l5870-21cpuspeed_turbos09:05:133
93212670,2sleep20-21swapper/212:35:002
15114996625,4cyclictest33-21ksoftirqd/208:55:142
15113996519,4cyclictest25-21ksoftirqd/109:20:191
15114996322,4cyclictest33-21ksoftirqd/208:45:192
15113996217,5cyclictest25-21ksoftirqd/110:25:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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