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2026-05-12 - 02:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon May 11, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491232168,52phc2sys0-21swapper/307:09:003
152862222194,18sleep10-21swapper/107:07:581
156472205172,22sleep20-21swapper/207:09:212
156962204171,22sleep00-21swapper/007:09:510
139391810,1ptp4l401ktimersoftd/308:30:293
139391650,1ptp4l401ktimersoftd/310:55:143
139391650,0ptp4l401ktimersoftd/309:49:503
16000994611,25cyclictest23538-21seq08:31:220
139391440,0ptp4l401ktimersoftd/308:42:373
139391430,0ptp4l401ktimersoftd/311:26:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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