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2026-07-12 - 23:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sun Jul 12, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27762203170,22sleep20-21swapper/207:07:082
27492203169,22sleep10-21swapper/107:06:471
26612202169,22sleep30-21swapper/307:05:413
29202201168,22sleep00-21swapper/007:08:540
166221500,4sleep0329999cyclictest08:10:280
2810821400,5sleep2330199cyclictest10:15:182
1393911180,1ptp4l14428-21df_abs10:55:143
209902580,3sleep020994-21kernelversion12:15:180
3299995723,6cyclictest9-21ksoftirqd/008:20:000
44672560,2sleep00-21swapper/011:40:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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