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2026-01-15 - 00:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jan 14, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206172,22phc2sys0-21swapper/307:06:043
245402205160,33sleep20-21swapper/207:05:032
264092204171,22sleep10-21swapper/107:06:361
245382197164,22sleep00-21swapper/007:05:010
1966921700,6sleep22697399cyclictest08:00:202
139391670,1ptp4l401ktimersoftd/309:20:193
115122600,7sleep02697199cyclictest11:10:150
139391560,1ptp4l401ktimersoftd/312:13:183
139391560,1ptp4l401ktimersoftd/310:18:323
139391560,1ptp4l401ktimersoftd/310:18:323
139391550,1ptp4l401ktimersoftd/307:52:143
139391540,1ptp4l401ktimersoftd/309:35:183
139391470,0ptp4l401ktimersoftd/309:30:303
26973994336,3cyclictest3579-21tr09:45:192
26973994336,3cyclictest3579-21tr09:45:182
139391430,1ptp4l0-21swapper/311:13:383
26972994136,3cyclictest25-21ksoftirqd/107:25:001
139391410,0ptp4l401ktimersoftd/309:29:153
139391410,0ptp4l401ktimersoftd/307:27:273
26971994032,4cyclictest9-21ksoftirqd/009:40:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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