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2026-05-04 - 16:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon May 04, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35232230165,21sleep30-21swapper/307:06:073
35892211164,36sleep20-21swapper/207:06:592
34802202169,21sleep10-21swapper/107:05:331
16432200167,22sleep00-21swapper/007:05:080
28112710,4sleep00-21swapper/008:15:000
4121996736,3cyclictest9-21ksoftirqd/008:00:010
4124996531,10cyclictest41-21ksoftirqd/311:35:263
4124996521,4cyclictest41-21ksoftirqd/311:04:423
4124996428,7cyclictest41-21ksoftirqd/309:15:193
4124996330,4cyclictest41-21ksoftirqd/311:45:013
4124996328,8cyclictest41-21ksoftirqd/307:50:183
4124996328,7cyclictest41-21ksoftirqd/307:25:193
4124996321,4cyclictest41-21ksoftirqd/309:09:063
4121996328,4cyclictest9-21ksoftirqd/010:55:010
4124996227,4cyclictest41-21ksoftirqd/312:30:203
4124996226,4cyclictest41-21ksoftirqd/310:30:013
139391620,1ptp4l0-21swapper/308:30:203
75062610,3sleep1412299cyclictest08:25:001
4124996131,3cyclictest41-21ksoftirqd/308:25:223
4124996126,6cyclictest41-21ksoftirqd/311:50:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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