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2026-04-01 - 21:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Apr 01, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
290172236171,22sleep10-21swapper/107:06:431
290062216151,22sleep00-21swapper/007:06:340
139491206172,23phc2sys0-21swapper/307:09:523
291572202168,23sleep20-21swapper/207:08:262
139391800,1ptp4l401ktimersoftd/310:00:223
118532700,3sleep311857-21timerandwakeup08:45:263
140452640,5sleep314047-21grep08:50:233
253802600,2sleep30-21swapper/310:20:293
39082570,2sleep00-21swapper/009:35:290
2957599541,17cyclictest0-21swapper/207:15:202
2957599521,17cyclictest0-21swapper/208:55:142
2957599510,17cyclictest0-21swapper/211:25:252
2957599510,17cyclictest0-21swapper/207:30:262
45592470,2sleep20-21swapper/208:30:242
2957599473,15cyclictest1016-21timerandwakeup11:45:272
2957599470,16cyclictest0-21swapper/211:30:272
2957599461,7cyclictest13134-21grep12:10:262
2957599460,16cyclictest0-21swapper/210:45:262
2957599455,22cyclictest22926-21smartctl09:10:162
2957599453,13cyclictest18965-21/usr/sbin/munin12:25:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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