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2025-12-20 - 19:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Dec 20, 2025 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
316202233168,21sleep30-21swapper/307:06:323
319042225158,22sleep00-21swapper/007:09:310
318242201168,22sleep20-21swapper/207:08:282
316492200169,20sleep10-21swapper/107:06:551
1828521690,7sleep23224299cyclictest12:15:282
262642620,3sleep026267-21cpuspeed_turbos08:05:140
262642620,3sleep026267-21cpuspeed_turbos08:05:140
226382620,2sleep20-21swapper/210:10:242
312612590,7sleep03224099cyclictest09:20:280
139391570,1ptp4l391rcuc/309:40:293
32241994337,3cyclictest12652-21cron11:00:001
139391430,0ptp4l401ktimersoftd/310:37:173
139391420,1ptp4l401ktimersoftd/309:19:123
139391420,0ptp4l401ktimersoftd/309:13:263
32242994035,3cyclictest33-21ksoftirqd/208:45:012
57898370,7rtkit-daemon0-21swapper/010:55:230
32243993732,3cyclictest2258-21egrep07:15:133
32242993731,4cyclictest33-21ksoftirqd/208:29:472
32242993730,5cyclictest33-21ksoftirqd/212:12:112
32240993732,3cyclictest9-21ksoftirqd/010:00:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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