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2026-07-14 - 20:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jul 14, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491227200,18phc2sys0-21swapper/307:07:583
187352215169,34sleep20-21swapper/207:06:402
189422204171,22sleep00-21swapper/007:09:140
187642204170,22sleep10-21swapper/107:07:031
1900228463,11sleep10-21swapper/107:10:001
139391720,1ptp4l7660-21ls07:50:283
19296996115,5cyclictest41-21ksoftirqd/309:25:013
54932570,2sleep30-21swapper/311:10:193
139391560,48ptp4l0-21swapper/307:10:003
139391560,1ptp4l401ktimersoftd/312:10:413
95622550,5sleep1241ktimersoftd/110:10:201
139391550,1ptp4l401ktimersoftd/308:19:573
1929699517,10cyclictest41-21ksoftirqd/310:38:573
19296995110,9cyclictest41-21ksoftirqd/307:20:283
1929699498,9cyclictest41-21ksoftirqd/309:45:003
19295994929,17cyclictest33-21ksoftirqd/208:20:122
19295994916,3cyclictest33-21ksoftirqd/210:35:142
19295994814,4cyclictest33-21ksoftirqd/209:05:202
1929499480,3cyclictest31364-21/usr/sbin/munin08:40:231
1929699478,4cyclictest41-21ksoftirqd/311:45:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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