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2026-08-25 - 00:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Aug 24, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491232164,23phc2sys0-21swapper/307:06:443
291372230168,51sleep10-21swapper/107:07:211
291942204169,23sleep20-21swapper/207:08:052
291612201168,22sleep00-21swapper/007:07:390
139391650,1ptp4l401ktimersoftd/308:35:173
242222600,2sleep20-21swapper/209:10:262
26312580,3sleep20-21swapper/209:35:122
139391540,1ptp4l401ktimersoftd/307:59:233
139391530,1ptp4l401ktimersoftd/312:07:053
11372530,3sleep1231rcuc/110:40:141
29642995221,8cyclictest33-21ksoftirqd/210:00:002
139391500,0ptp4l401ktimersoftd/309:43:443
2964299495,7cyclictest32461-21sed10:35:252
29642994831,10cyclictest33-21ksoftirqd/210:20:132
29642994617,9cyclictest33-21ksoftirqd/210:00:192
29642994526,8cyclictest33-21ksoftirqd/207:55:232
1394914433,4phc2sys0-21swapper/307:10:003
139391440,0ptp4l401ktimersoftd/312:16:543
139391440,0ptp4l401ktimersoftd/311:25:143
139391440,0ptp4l401ktimersoftd/307:16:463
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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