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2026-04-05 - 01:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Apr 04, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110032205173,21sleep20-21swapper/207:07:262
90772204171,22sleep30-21swapper/307:05:053
90792203171,22sleep00-21swapper/007:05:060
110652200167,22sleep10-21swapper/107:08:131
1050521720,4sleep11150599cyclictest10:30:141
2826721290,6sleep21150699cyclictest11:05:252
292112750,1sleep00-21swapper/010:00:210
273672620,3sleep30-21swapper/309:55:273
11507996222,8cyclictest41-21ksoftirqd/308:54:283
11507996128,7cyclictest41-21ksoftirqd/311:55:183
11507996128,7cyclictest41-21ksoftirqd/311:55:183
11507996028,6cyclictest41-21ksoftirqd/312:20:213
11507996020,8cyclictest41-21ksoftirqd/307:30:523
11507995931,3cyclictest41-21ksoftirqd/310:20:133
11507995927,7cyclictest41-21ksoftirqd/308:10:193
11507995925,9cyclictest41-21ksoftirqd/310:25:143
11507995923,8cyclictest41-21ksoftirqd/308:59:583
11507995828,9cyclictest41-21ksoftirqd/307:50:153
11507995826,8cyclictest41-21ksoftirqd/308:25:213
11507995821,8cyclictest41-21ksoftirqd/309:09:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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