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2026-10-01 - 19:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Oct 01, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
214142232167,21sleep30-21swapper/307:08:563
212682203170,21sleep20-21swapper/207:07:022
193662203169,23sleep00-21swapper/007:05:030
213662202169,22sleep10-21swapper/107:08:181
778021570,7sleep32180299cyclictest08:55:143
1569321540,6sleep32180299cyclictest12:30:193
21801996712,18cyclictest26058-21cut09:30:232
21801996712,18cyclictest26058-21cut09:30:232
283622650,5sleep028364-21proc_pri09:35:220
2179999607,10cyclictest13960-21latency_hist10:15:000
2179999597,9cyclictest25795-21systemctl07:15:230
2179999587,11cyclictest29861-21df_abs09:40:150
2180199570,22cyclictest21305-21perl08:15:162
2179999566,16cyclictest0-21swapper/008:40:220
2179999554,17cyclictest0-21swapper/009:50:000
2179999544,16cyclictest16169-21grep12:30:240
106892540,2sleep30-21swapper/309:00:193
106892540,2sleep30-21swapper/309:00:193
2179999539,10cyclictest1191-21awk12:00:230
2179999538,16cyclictest3250-21df_abs08:45:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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