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2026-07-17 - 23:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jul 17, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44812216169,36sleep20-21swapper/207:07:592
43052208175,22sleep10-21swapper/107:05:411
139491207172,24phc2sys0-21swapper/307:06:023
44842204171,22sleep00-21swapper/007:08:010
46452163124,13sleep30-21swapper/307:10:013
2842221590,6sleep2494099cyclictest09:05:202
114021270,5sleep2494099cyclictest08:10:002
76912630,3sleep0493899cyclictest09:30:180
221212610,2sleep30-21swapper/307:45:143
139391600,1ptp4l401ktimersoftd/312:29:463
139391580,1ptp4l401ktimersoftd/307:30:283
139391570,1ptp4l401ktimersoftd/312:30:193
139391540,1ptp4l401ktimersoftd/309:11:343
139391530,1ptp4l401ktimersoftd/310:04:063
493999512,45cyclictest14398-21turbostat12:00:011
4939994821,7cyclictest25-21ksoftirqd/110:00:021
4939994817,4cyclictest25-21ksoftirqd/111:10:211
493999468,5cyclictest25-21ksoftirqd/112:25:011
4939994618,7cyclictest25-21ksoftirqd/112:05:151
4939994613,7cyclictest25-21ksoftirqd/110:55:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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