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2026-07-13 - 18:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jul 13, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
124542208142,21sleep00-21swapper/007:06:010
139491207172,23phc2sys0-21swapper/307:09:493
127432207173,23sleep20-21swapper/207:09:412
126762204170,22sleep10-21swapper/107:08:561
908221280,1sleep30-21swapper/309:15:223
13062996432,4cyclictest33-21ksoftirqd/211:30:202
13062996429,6cyclictest33-21ksoftirqd/208:55:282
165622630,7sleep31306399cyclictest09:30:223
139391630,1ptp4l401ktimersoftd/311:27:073
13062996230,10cyclictest33-21ksoftirqd/212:15:142
13062996223,8cyclictest33-21ksoftirqd/207:25:012
13062996220,8cyclictest33-21ksoftirqd/209:00:132
13062996126,4cyclictest33-21ksoftirqd/208:40:252
13062996126,4cyclictest33-21ksoftirqd/208:40:242
13062996123,7cyclictest33-21ksoftirqd/211:45:292
13062996121,7cyclictest33-21ksoftirqd/207:30:272
13062996121,7cyclictest33-21ksoftirqd/207:10:222
13062996120,6cyclictest33-21ksoftirqd/209:45:252
13062996026,4cyclictest33-21ksoftirqd/210:10:252
13062996022,7cyclictest33-21ksoftirqd/210:35:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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