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2025-11-25 - 20:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Nov 25, 2025 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191228163,22phc2sys0-21swapper/307:09:163
137191228163,22phc2sys0-21swapper/307:09:163
67422205172,22sleep20-21swapper/207:09:022
67422205172,22sleep20-21swapper/207:09:022
66692203170,22sleep00-21swapper/007:08:080
66692203170,22sleep00-21swapper/007:08:080
65622203170,22sleep10-21swapper/107:06:441
65622203170,22sleep10-21swapper/107:06:431
2444221490,5sleep3712199cyclictest07:45:163
3213121470,3sleep232134-21unixbench_singl09:05:272
682728562,15sleep00-21swapper/007:10:010
152562660,1sleep30-21swapper/309:40:153
7119996229,5cyclictest25-21ksoftirqd/107:15:241
7119996227,5cyclictest25-21ksoftirqd/112:30:141
242422620,2sleep10-21swapper/108:50:221
7119996126,6cyclictest25-21ksoftirqd/108:45:191
7119996122,8cyclictest25-21ksoftirqd/111:15:241
7119996029,8cyclictest25-21ksoftirqd/109:35:001
7119996026,7cyclictest25-21ksoftirqd/112:10:411
7119995930,6cyclictest25-21ksoftirqd/111:00:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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