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2025-10-20 - 11:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Oct 20, 2025 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191231163,23phc2sys0-21swapper/319:07:263
245232207173,23sleep20-21swapper/219:06:022
244902202169,22sleep10-21swapper/119:05:381
244892201168,22sleep00-21swapper/019:05:360
136991850,1ptp4l391rcuc/322:00:143
136991830,1ptp4l391rcuc/321:30:133
136991830,1ptp4l391rcuc/319:45:263
136991830,1ptp4l391rcuc/300:10:293
136991820,1ptp4l391rcuc/323:25:113
136991820,1ptp4l391rcuc/322:50:123
136991820,1ptp4l391rcuc/319:25:123
136991810,1ptp4l391rcuc/320:15:153
136991810,1ptp4l391rcuc/320:10:223
136991810,1ptp4l391rcuc/319:35:133
136991810,0ptp4l391rcuc/319:30:133
136991800,1ptp4l391rcuc/323:50:203
136991790,1ptp4l391rcuc/322:40:263
136991790,0ptp4l391rcuc/319:40:153
136991780,1ptp4l391rcuc/323:05:223
136991780,1ptp4l391rcuc/322:30:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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