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2026-06-20 - 22:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jun 20, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
113002205170,23sleep30-21swapper/307:09:273
113032204171,22sleep10-21swapper/107:09:291
109982201168,22sleep00-21swapper/007:05:300
111452199166,22sleep20-21swapper/207:07:252
1371721390,1sleep10-21swapper/109:30:011
558921320,3sleep11164799cyclictest09:10:231
139391680,9ptp4l401ktimersoftd/312:34:163
11648996728,5cyclictest33-21ksoftirqd/209:25:282
11648996433,4cyclictest33-21ksoftirqd/212:00:002
11648996432,4cyclictest33-21ksoftirqd/210:10:232
11648996431,4cyclictest33-21ksoftirqd/211:25:142
11648996332,4cyclictest33-21ksoftirqd/210:15:242
11648996326,5cyclictest33-21ksoftirqd/208:05:232
11648996229,5cyclictest33-21ksoftirqd/210:05:172
11648996229,4cyclictest33-21ksoftirqd/211:30:232
11648996130,4cyclictest33-21ksoftirqd/207:10:252
11648996130,4cyclictest33-21ksoftirqd/207:10:252
11648996129,4cyclictest33-21ksoftirqd/208:55:172
11648996127,7cyclictest33-21ksoftirqd/209:15:272
11648996125,9cyclictest33-21ksoftirqd/207:37:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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