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2026-02-03 - 18:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Feb 03, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205392208175,22sleep20-21swapper/207:07:042
205392208175,22sleep20-21swapper/207:07:042
206312204171,22sleep10-21swapper/107:08:151
206312204171,22sleep10-21swapper/107:08:151
206032203170,22sleep30-21swapper/307:07:533
206032203170,22sleep30-21swapper/307:07:533
204442202169,22sleep00-21swapper/007:05:490
204442202169,22sleep00-21swapper/007:05:490
2872221230,1sleep20-21swapper/208:35:212
2872221230,1sleep20-21swapper/208:35:212
139391730,1ptp4l13414-21mailstats09:10:263
159532700,1sleep315954-21/usr/sbin/munin11:30:203
139391690,1ptp4l23936-21/usr/sbin/munin09:35:213
139391660,1ptp4l391rcuc/310:25:243
242512630,6sleep22106799cyclictest11:50:002
21068996126,10cyclictest41-21ksoftirqd/312:05:003
21068996124,4cyclictest41-21ksoftirqd/309:40:163
21068996023,4cyclictest41-21ksoftirqd/308:02:193
21068996022,4cyclictest41-21ksoftirqd/312:28:083
21068995922,4cyclictest41-21ksoftirqd/311:10:083
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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