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2026-06-24 - 01:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jun 23, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491233168,22phc2sys0-21swapper/307:09:223
267862206171,24sleep20-21swapper/207:09:012
266942205171,23sleep00-21swapper/007:07:550
266362202169,22sleep10-21swapper/107:07:111
2407721420,6sleep12733299cyclictest11:30:231
134491720,6getstats2733899cyclictest11:34:543
228852600,7sleep2321ktimersoftd/209:15:162
139391570,1ptp4l401ktimersoftd/308:09:533
139391540,1ptp4l401ktimersoftd/307:15:153
139391540,1ptp4l391rcuc/308:50:423
139391540,1ptp4l391rcuc/308:50:413
139391470,1ptp4l401ktimersoftd/311:58:233
57898450,2rtkit-daemon577-21rtkit-daemon08:50:171
57898450,2rtkit-daemon577-21rtkit-daemon08:50:161
27336994439,3cyclictest13950-21sh10:05:002
1394914433,5phc2sys0-21swapper/307:10:013
1394914433,5phc2sys0-21swapper/307:10:003
139391440,0ptp4l401ktimersoftd/307:49:153
139391430,0ptp4l401ktimersoftd/309:52:533
139391430,0ptp4l401ktimersoftd/309:52:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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