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2026-08-10 - 16:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Aug 10, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207173,23phc2sys0-21swapper/307:08:503
139492205172,22sleep00-21swapper/007:08:010
138682205172,22sleep10-21swapper/107:06:571
138492202169,22sleep20-21swapper/207:06:422
2426221500,6sleep01440399cyclictest09:45:180
2426221500,6sleep01440399cyclictest09:45:170
89792610,4sleep38982-21irqrtprio08:05:203
139391560,1ptp4l401ktimersoftd/311:45:593
139391560,1ptp4l401ktimersoftd/307:13:183
139391540,1ptp4l401ktimersoftd/309:40:113
139391440,0ptp4l401ktimersoftd/310:07:003
139391430,0ptp4l401ktimersoftd/309:01:583
139391420,0ptp4l401ktimersoftd/310:01:583
139391420,0ptp4l401ktimersoftd/307:48:113
139391400,1ptp4l401ktimersoftd/308:15:243
139391400,0ptp4l401ktimersoftd/310:20:273
14404993935,3cyclictest25-21ksoftirqd/111:55:001
139391390,0ptp4l401ktimersoftd/307:55:423
14405993824,12cyclictest33-21ksoftirqd/208:40:002
14404993825,10cyclictest25-21ksoftirqd/109:55:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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