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2026-07-06 - 13:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jul 06, 2026 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491225163,51phc2sys0-21swapper/319:08:103
301732204170,22sleep00-21swapper/019:06:050
302792203171,22sleep10-21swapper/119:07:281
302072202168,23sleep20-21swapper/219:06:332
2463421330,5sleep23089199cyclictest21:10:192
2826121300,3sleep23089199cyclictest20:10:222
1393911010,1ptp4l12716-21dump-pmu-power19:40:003
139391900,1ptp4l6690-21cat20:35:003
30891997633,4cyclictest33-21ksoftirqd/200:20:012
30891996332,4cyclictest33-21ksoftirqd/223:15:242
30892996231,4cyclictest41-21ksoftirqd/321:00:293
30891996219,4cyclictest33-21ksoftirqd/221:05:002
30891996028,4cyclictest33-21ksoftirqd/222:55:122
30891995925,3cyclictest33-21ksoftirqd/219:35:192
30890995956,2cyclictest231rcuc/123:33:571
30892995828,4cyclictest41-21ksoftirqd/323:25:133
30892995825,4cyclictest41-21ksoftirqd/320:05:263
30891995834,2cyclictest33-21ksoftirqd/220:09:112
30890995855,2cyclictest231rcuc/122:09:531
30890995855,2cyclictest231rcuc/120:31:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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