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2026-01-06 - 10:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jan 06, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112122202163,28sleep30-21swapper/319:07:543
110482202169,22sleep20-21swapper/219:05:522
110422201168,22sleep10-21swapper/119:05:471
91132197164,22sleep00-21swapper/019:05:010
37012690,5sleep23704-21irqrtprio22:15:182
1166699665,20cyclictest10289-21date20:15:010
139391650,1ptp4l401ktimersoftd/322:41:083
78172590,4sleep20-21swapper/221:15:212
57952570,2sleep30-21swapper/320:05:153
315832550,1sleep20-21swapper/200:20:182
134491550,1getstats0-21swapper/323:29:173
1166699541,23cyclictest29022-21seq20:51:240
139391530,0ptp4l401ktimersoftd/322:15:213
1166699520,21cyclictest3610-21runrttasks00:34:160
1166699490,21cyclictest1317-21runrttasks22:08:180
134491460,7getstats1166999cyclictest21:59:183
134491460,1getstats0-21swapper/323:19:183
11668994617,3cyclictest33-21ksoftirqd/222:10:192
1166899460,3cyclictest121rcu_preempt21:55:002
11668994518,4cyclictest33-21ksoftirqd/222:45:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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