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2026-09-03 - 05:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Sep 03, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
160482234168,22sleep20-21swapper/219:09:222
139491232165,22phc2sys0-21swapper/319:05:443
160422204170,22sleep10-21swapper/119:09:171
159592201168,22sleep00-21swapper/019:08:120
1654099701,67cyclictest22615-21kworker/2:122:25:332
139391630,7ptp4l401ktimersoftd/319:19:283
139391610,2ptp4l401ktimersoftd/321:25:013
1654099570,55cyclictest22615-21kworker/2:119:55:052
139391560,1ptp4l401ktimersoftd/320:45:183
16540995412,13cyclictest22194-21kworker/2:022:50:032
1653999538,43cyclictest0-21swapper/100:30:531
11982500,1sleep10-21swapper/119:45:151
139391470,1ptp4l401ktimersoftd/322:25:473
16539994630,13cyclictest25-21ksoftirqd/121:43:591
1653999460,44cyclictest0-21swapper/122:52:431
139391460,0ptp4l401ktimersoftd/320:32:493
1653999442,41cyclictest0-21swapper/119:24:131
1653999440,42cyclictest0-21swapper/120:00:231
16538994438,3cyclictest9408-21sh21:10:000
16538994438,3cyclictest9408-21sh21:10:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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