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2025-12-25 - 22:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Dec 25, 2025 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
303892226163,51sleep20-21swapper/207:07:412
303702203169,23sleep30-21swapper/307:07:273
303682200166,22sleep10-21swapper/107:07:251
303672200167,22sleep00-21swapper/007:07:230
130562690,7sleep00-21swapper/007:39:590
139391620,1ptp4l401ktimersoftd/311:43:273
3086899575,6cyclictest2689-21cut10:40:001
139391570,49ptp4l0-21swapper/307:10:023
311252550,2sleep10-21swapper/107:10:131
30868995552,2cyclictest231rcuc/112:13:241
139391550,0ptp4l401ktimersoftd/312:27:173
30868995350,2cyclictest231rcuc/110:42:461
30868995225,4cyclictest25-21ksoftirqd/112:05:131
3086899514,6cyclictest17744-21if_enp4s011:10:161
139391510,1ptp4l401ktimersoftd/307:52:273
30869995020,3cyclictest33-21ksoftirqd/209:05:262
30869995016,3cyclictest33-21ksoftirqd/207:20:542
3086899501,7cyclictest25872-21expr12:35:121
139391500,1ptp4l401ktimersoftd/311:12:203
30869994918,7cyclictest33-21ksoftirqd/210:40:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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