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2026-08-13 - 17:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Aug 13, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491227162,22phc2sys0-21swapper/307:08:393
267252203171,21sleep20-21swapper/207:09:412
264712203169,23sleep00-21swapper/007:06:210
265602202169,21sleep10-21swapper/107:07:321
946121690,2sleep20-21swapper/212:10:202
518521390,6sleep02705099cyclictest07:30:210
27053996210,11cyclictest4470-21sed08:35:243
23172610,3sleep22321-21irqrtprio09:40:202
27053996010,17cyclictest22082-21egrep09:15:133
27053996010,11cyclictest17423-21cut12:25:233
142872600,1sleep00-21swapper/012:20:170
2705399589,9cyclictest6305-21irqstats08:40:183
27053995810,15cyclictest16431-21mailstats11:15:233
2705399559,14cyclictest25438-21ls09:20:193
2705399558,16cyclictest0-21swapper/308:30:263
99522540,4sleep19884-21latency_hist08:50:001
227662540,3sleep00-21swapper/009:15:190
139391540,1ptp4l391rcuc/312:05:373
170712530,1sleep10-21swapper/110:10:201
2705399519,14cyclictest3150-21ps07:25:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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