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2026-02-22 - 06:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Feb 22, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207174,22phc2sys0-21swapper/319:06:313
54792203169,23sleep20-21swapper/219:08:202
54572203170,22sleep00-21swapper/019:08:010
52712202169,22sleep10-21swapper/119:05:411
328021710,6sleep1590099cyclictest23:30:261
1473021550,7sleep2590199cyclictest19:25:242
1394919067,12phc2sys0-21swapper/319:10:003
139391630,1ptp4l401ktimersoftd/323:30:143
303032590,3sleep30-21swapper/300:30:003
293252580,3sleep129327-21unixbench_singl19:55:281
139391570,1ptp4l401ktimersoftd/320:22:263
5902995524,7cyclictest41-21ksoftirqd/321:10:203
5902995323,3cyclictest41-21ksoftirqd/323:35:273
5902995017,4cyclictest41-21ksoftirqd/320:00:013
5902994916,7cyclictest41-21ksoftirqd/322:10:013
5902994820,3cyclictest41-21ksoftirqd/322:10:273
257042480,1sleep20-21swapper/219:50:152
5902994719,8cyclictest41-21ksoftirqd/321:10:013
199662470,2sleep30-21swapper/321:50:273
139391470,1ptp4l401ktimersoftd/320:29:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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