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2026-06-18 - 20:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jun 18, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
262142209143,23sleep30-21swapper/307:06:413
263482204160,33sleep20-21swapper/207:08:252
261662203169,22sleep00-21swapper/007:06:010
263622202169,22sleep10-21swapper/107:08:361
80421160,2sleep00-21swapper/008:30:140
26773997222,8cyclictest33-21ksoftirqd/207:25:252
26773997122,9cyclictest33-21ksoftirqd/209:20:152
26773996926,8cyclictest33-21ksoftirqd/207:15:182
26773996822,4cyclictest33-21ksoftirqd/211:40:102
26773996815,11cyclictest33-21ksoftirqd/208:55:002
26773996727,9cyclictest33-21ksoftirqd/208:50:002
26773996727,9cyclictest33-21ksoftirqd/208:50:002
26773996723,5cyclictest33-21ksoftirqd/209:55:222
26773996722,4cyclictest33-21ksoftirqd/209:30:232
26771996631,8cyclictest9-21ksoftirqd/009:55:190
26771996630,7cyclictest9-21ksoftirqd/007:30:010
26773996528,3cyclictest33-21ksoftirqd/211:00:002
26773996526,5cyclictest33-21ksoftirqd/209:10:132
26773996526,5cyclictest33-21ksoftirqd/208:20:002
26773996526,5cyclictest33-21ksoftirqd/207:35:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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