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2026-06-12 - 16:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jun 12, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
57722204171,22sleep00-21swapper/007:06:170
57722204171,22sleep00-21swapper/007:06:170
57692204169,23sleep20-21swapper/207:06:152
57692204169,23sleep20-21swapper/207:06:152
59342203170,22sleep30-21swapper/307:08:213
59342203170,22sleep30-21swapper/307:08:213
57382203170,22sleep10-21swapper/107:05:501
57382203170,22sleep10-21swapper/107:05:501
139391780,1ptp4l391rcuc/311:20:133
6527997035,4cyclictest41-21ksoftirqd/311:55:003
6526996712,53cyclictest7563-21kworker/2:011:45:342
652699652,61cyclictest24915-21kworker/2:010:35:342
6527996424,7cyclictest41-21ksoftirqd/310:50:213
6524996427,7cyclictest25-21ksoftirqd/109:40:011
6524996427,7cyclictest25-21ksoftirqd/109:40:011
6527996324,11cyclictest41-21ksoftirqd/311:40:253
6527996322,7cyclictest41-21ksoftirqd/310:00:153
6527996320,4cyclictest41-21ksoftirqd/310:46:343
6527996228,8cyclictest41-21ksoftirqd/311:05:193
6527996226,7cyclictest41-21ksoftirqd/307:35:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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