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2025-12-04 - 14:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Dec 04, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191207173,22phc2sys0-21swapper/319:07:473
187892201168,22sleep20-21swapper/219:09:572
187452201168,22sleep10-21swapper/119:09:241
184752201167,23sleep00-21swapper/019:06:010
59298810,12rtkit-daemon0-21swapper/300:30:143
136991780,6ptp4l401ktimersoftd/320:45:213
19087996123,3cyclictest33-21ksoftirqd/219:20:232
71342600,3sleep30-21swapper/320:55:283
19087996027,11cyclictest33-21ksoftirqd/221:20:212
19087996026,6cyclictest33-21ksoftirqd/219:25:252
19087996024,4cyclictest33-21ksoftirqd/223:40:152
19087996024,4cyclictest33-21ksoftirqd/223:20:222
19087996023,4cyclictest33-21ksoftirqd/220:50:232
19087995929,6cyclictest33-21ksoftirqd/222:45:002
19087995924,5cyclictest33-21ksoftirqd/221:40:242
19087995924,4cyclictest33-21ksoftirqd/219:55:232
19087995921,4cyclictest33-21ksoftirqd/200:00:262
19087995921,10cyclictest33-21ksoftirqd/200:35:222
19087995824,6cyclictest33-21ksoftirqd/222:20:262
19087995823,5cyclictest33-21ksoftirqd/223:10:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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