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2026-04-30 - 15:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Apr 30, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491208173,23phc2sys0-21swapper/307:06:493
81542205170,23sleep20-21swapper/207:08:152
79292205172,22sleep00-21swapper/007:05:190
79252202169,22sleep10-21swapper/107:05:171
82982161124,12sleep30-21swapper/307:10:023
139391670,1ptp4l401ktimersoftd/307:19:153
8593996630,5cyclictest33-21ksoftirqd/210:08:562
139391660,1ptp4l401ktimersoftd/310:49:563
859299600,1cyclictest0-21swapper/107:46:531
8593995724,6cyclictest33-21ksoftirqd/210:57:122
139391570,1ptp4l401ktimersoftd/309:41:083
8593995620,4cyclictest33-21ksoftirqd/208:40:002
247672550,3sleep09-21ksoftirqd/011:05:130
8593995418,7cyclictest33-21ksoftirqd/208:25:212
8593995341,2cyclictest12175-21dump-pmu-power10:40:002
8593995322,4cyclictest33-21ksoftirqd/210:15:122
8593995318,5cyclictest33-21ksoftirqd/212:15:232
8593995224,3cyclictest33-21ksoftirqd/208:15:002
8593995114,9cyclictest33-21ksoftirqd/209:00:012
8593995023,4cyclictest33-21ksoftirqd/211:50:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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