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2026-06-09 - 03:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jun 09, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
269902224197,18sleep10-21swapper/119:07:591
139491205172,22phc2sys0-21swapper/319:06:243
269072203169,23sleep00-21swapper/019:07:010
270782201169,21sleep20-21swapper/219:09:082
276221340,3sleep32744099cyclictest19:25:173
2743899616,11cyclictest20229-21sort23:20:251
2743899616,11cyclictest20229-21sort23:20:251
113472600,5sleep02743799cyclictest21:55:250
2743899595,12cyclictest29064-21cat22:35:011
27439995815,9cyclictest33-21ksoftirqd/223:55:002
34592570,1sleep10-21swapper/119:25:241
2743899565,12cyclictest2088-21cut22:45:151
139391560,1ptp4l401ktimersoftd/320:55:153
2743899555,16cyclictest11694-21ptp4l00:10:231
2743899545,12cyclictest29878-21cpu19:15:131
2743899545,11cyclictest25411-21sed22:25:181
2743899535,12cyclictest15660-21sed19:50:201
2743899534,11cyclictest28306-21cpu23:40:131
2743899525,17cyclictest31652-21cpu22:40:121
139391520,1ptp4l401ktimersoftd/300:36:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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