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2025-12-10 - 11:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Dec 10, 2025 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
270372208141,22sleep10-21swapper/119:08:201
137191204169,23phc2sys0-21swapper/319:06:023
268352202169,22sleep20-21swapper/219:05:522
268382201167,23sleep00-21swapper/019:05:540
136991810,1ptp4l391rcuc/320:15:333
136991810,1ptp4l391rcuc/320:15:323
27459997532,6cyclictest25-21ksoftirqd/123:20:001
272312660,3sleep10-21swapper/120:15:231
272312660,3sleep10-21swapper/120:15:231
27459996525,4cyclictest25-21ksoftirqd/121:50:271
27459996419,6cyclictest25-21ksoftirqd/122:14:591
27459996328,4cyclictest25-21ksoftirqd/121:30:011
27459996324,7cyclictest25-21ksoftirqd/120:00:161
27459996128,7cyclictest25-21ksoftirqd/122:20:241
27458996131,4cyclictest9-21ksoftirqd/000:30:140
27459996027,10cyclictest25-21ksoftirqd/100:25:021
27459996025,7cyclictest25-21ksoftirqd/123:20:271
27459996025,7cyclictest25-21ksoftirqd/123:20:261
27459996024,6cyclictest25-21ksoftirqd/120:55:001
27459996021,7cyclictest25-21ksoftirqd/122:00:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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