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2026-02-14 - 15:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Feb 14, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
95252204171,22sleep20-21swapper/207:09:322
95262202169,22sleep30-21swapper/307:09:323
95282201167,22sleep00-21swapper/007:09:340
93482197163,22sleep10-21swapper/107:07:131
1883421310,3sleep2986699cyclictest09:40:252
288832660,5sleep028886-21turbostat07:49:590
986799595,11cyclictest57832sleep308:06:043
986799575,11cyclictest278392sleep311:07:353
986799567,17cyclictest21649-21chrt07:33:593
986799566,11cyclictest16241-21sshd08:30:153
986799565,9cyclictest117992chrt07:12:203
986799564,11cyclictest143032sleep307:19:013
986799564,10cyclictest27372chrt11:23:123
986799555,11cyclictest73552sleep311:31:333
257302550,4sleep30-21swapper/309:55:233
986799547,17cyclictest1323-21chrt12:28:383
986799536,15cyclictest16757-21runrttasks07:22:043
986799535,12cyclictest207782sleep310:53:343
986699532,11cyclictest23663-21timedrift12:05:242
127922520,3sleep30-21swapper/311:45:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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