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2026-05-14 - 17:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu May 14, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
244872208173,23sleep30-21swapper/307:09:103
244852205171,23sleep10-21swapper/107:09:081
244842204171,22sleep00-21swapper/007:09:060
241982201169,21sleep20-21swapper/207:06:062
138412750,2sleep00-21swapper/009:00:140
247722680,5sleep233-21ksoftirqd/211:35:212
261442570,2sleep10-21swapper/110:30:251
1394915738,11phc2sys0-21swapper/307:10:013
25009995628,10cyclictest41-21ksoftirqd/312:05:013
25009995623,8cyclictest41-21ksoftirqd/310:55:263
25009995526,9cyclictest41-21ksoftirqd/312:20:003
217402550,1sleep00-21swapper/008:10:120
25009995426,8cyclictest41-21ksoftirqd/312:10:263
65712530,2sleep06565-21latency_hist11:00:000
25009995225,10cyclictest41-21ksoftirqd/310:35:273
323862510,2sleep20-21swapper/211:50:252
2500999513,6cyclictest41-21ksoftirqd/307:30:213
25009995126,8cyclictest41-21ksoftirqd/311:20:163
25009995124,8cyclictest41-21ksoftirqd/308:05:203
2500999510,6cyclictest401ktimersoftd/310:15:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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