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2026-07-22 - 04:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jul 22, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
105602205172,22sleep30-21swapper/319:07:193
106272204172,21sleep20-21swapper/219:08:092
105282202169,22sleep10-21swapper/119:06:521
104362202169,22sleep00-21swapper/019:05:460
136921680,4sleep31106599cyclictest21:05:003
3167321360,1sleep30-21swapper/323:15:183
11063996423,8cyclictest25-21ksoftirqd/121:40:231
11063996323,7cyclictest25-21ksoftirqd/122:55:261
11063996222,9cyclictest25-21ksoftirqd/123:25:241
11063996221,9cyclictest25-21ksoftirqd/119:25:241
11063996221,8cyclictest25-21ksoftirqd/120:05:161
11063996220,7cyclictest25-21ksoftirqd/123:30:131
11063996128,4cyclictest25-21ksoftirqd/123:05:171
11063996122,9cyclictest25-21ksoftirqd/120:15:201
11063996120,8cyclictest25-21ksoftirqd/122:30:181
11063996028,4cyclictest25-21ksoftirqd/100:20:241
11063996027,7cyclictest25-21ksoftirqd/123:00:171
11063996022,6cyclictest25-21ksoftirqd/122:05:281
11063996021,8cyclictest25-21ksoftirqd/123:10:201
206172590,2sleep30-21swapper/319:30:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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