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2025-12-18 - 14:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Dec 18, 2025 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
316892228168,49sleep10-21swapper/119:08:201
318022205172,22sleep20-21swapper/219:09:502
317782204170,22sleep30-21swapper/319:09:303
314922201168,22sleep00-21swapper/019:05:460
114921400,4sleep33211299cyclictest22:35:163
32112996630,7cyclictest41-21ksoftirqd/320:55:003
3211199666,12cyclictest378-21perf22:35:002
32112996534,8cyclictest41-21ksoftirqd/319:40:003
32112996530,8cyclictest41-21ksoftirqd/323:00:003
32112996433,8cyclictest41-21ksoftirqd/320:55:243
32112996330,3cyclictest41-21ksoftirqd/300:00:003
32112996131,4cyclictest41-21ksoftirqd/320:40:193
32112996130,4cyclictest41-21ksoftirqd/322:45:273
32112996129,8cyclictest41-21ksoftirqd/323:55:003
32112996127,6cyclictest41-21ksoftirqd/320:45:153
32112996127,5cyclictest41-21ksoftirqd/321:25:243
32112996030,3cyclictest41-21ksoftirqd/321:20:163
32112996026,7cyclictest41-21ksoftirqd/321:00:293
32112996022,11cyclictest41-21ksoftirqd/319:15:003
32112995923,8cyclictest41-21ksoftirqd/300:10:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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