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2026-07-04 - 13:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jul 04, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
294372232168,53sleep30-21swapper/319:05:283
295572207172,24sleep00-21swapper/019:06:470
295032204170,22sleep10-21swapper/119:06:111
296982202169,22sleep20-21swapper/219:08:382
1625121680,4sleep03009699cyclictest19:45:250
71021360,4sleep13009799cyclictest19:15:171
30096996428,4cyclictest9-21ksoftirqd/000:35:000
30096996428,4cyclictest9-21ksoftirqd/000:35:000
30096996427,8cyclictest9-21ksoftirqd/000:10:270
139391640,1ptp4l401ktimersoftd/320:55:173
30096996225,4cyclictest9-21ksoftirqd/020:35:140
30096996125,4cyclictest9-21ksoftirqd/023:25:210
30096996025,4cyclictest9-21ksoftirqd/000:00:130
30096996025,4cyclictest9-21ksoftirqd/000:00:130
139391600,0ptp4l401ktimersoftd/321:18:343
30096995928,4cyclictest9-21ksoftirqd/023:40:180
30096995927,4cyclictest9-21ksoftirqd/019:25:220
30096995925,4cyclictest9-21ksoftirqd/000:15:210
30097995855,2cyclictest231rcuc/122:19:121
30097995855,2cyclictest231rcuc/119:31:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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