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2026-01-30 - 03:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jan 30, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207164,31phc2sys0-21swapper/319:08:193
109812204171,22sleep10-21swapper/119:09:541
107452202169,22sleep00-21swapper/019:06:550
107372202170,21sleep20-21swapper/219:06:492
2112021430,2sleep00-21swapper/022:50:220
139391850,1ptp4l12502-21runrttasks19:10:213
1128399594,17cyclictest9349-21df_abs23:35:131
139391570,1ptp4l401ktimersoftd/321:55:063
1128399575,15cyclictest13632-21irqrtprio22:35:171
141912560,2sleep20-21swapper/221:30:142
1128399553,16cyclictest0-21swapper/119:55:131
139391540,1ptp4l401ktimersoftd/320:52:213
139391540,1ptp4l401ktimersoftd/320:52:213
1128399533,17cyclictest0-21swapper/122:20:231
1128399533,15cyclictest0-21swapper/121:20:181
1128399533,15cyclictest0-21swapper/121:20:171
132552520,5sleep213260-21unixbench_multi21:25:292
11285995221,4cyclictest41-21ksoftirqd/322:14:593
142312500,1sleep00-21swapper/020:20:280
1128399496,7cyclictest29962-21uptime22:00:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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