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2026-03-24 - 05:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Mar 24, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491233168,53phc2sys0-21swapper/319:07:583
139491233168,53phc2sys0-21swapper/319:07:573
111742203169,23sleep20-21swapper/219:09:372
111742203169,23sleep20-21swapper/219:09:372
109352203171,21sleep10-21swapper/119:06:391
109352203171,21sleep10-21swapper/119:06:381
90722201168,22sleep00-21swapper/019:05:090
90722201168,22sleep00-21swapper/019:05:090
1149799780,76cyclictest0-21swapper/120:01:331
139391680,1ptp4l401ktimersoftd/300:26:323
11496996628,6cyclictest9-21ksoftirqd/022:10:150
11496996425,10cyclictest9-21ksoftirqd/021:10:240
11496996328,5cyclictest9-21ksoftirqd/020:19:590
1149899628,16cyclictest27363-21ptp4l-jitter19:40:222
11498996210,17cyclictest14586-21perl21:30:172
11496996224,6cyclictest9-21ksoftirqd/019:20:200
11496996222,6cyclictest9-21ksoftirqd/023:50:180
11498996111,9cyclictest12121-21tune2fs23:40:162
11496996124,5cyclictest9-21ksoftirqd/021:20:170
11496996124,5cyclictest9-21ksoftirqd/020:25:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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