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2026-03-13 - 22:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Mar 13, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
313122207175,21sleep20-21swapper/207:05:492
139491205172,22phc2sys0-21swapper/307:09:473
313632203170,22sleep10-21swapper/107:06:291
313672200167,23sleep00-21swapper/007:06:310
139391890,1ptp4l2699-21irqrtprio07:15:183
139391820,1ptp4l401ktimersoftd/308:18:493
31934996429,6cyclictest33-21ksoftirqd/208:20:142
31934996232,3cyclictest33-21ksoftirqd/209:55:182
31934996227,4cyclictest33-21ksoftirqd/211:30:122
31934996129,6cyclictest33-21ksoftirqd/209:15:212
31934996127,6cyclictest33-21ksoftirqd/208:00:182
31934996124,4cyclictest33-21ksoftirqd/210:00:212
31934996122,6cyclictest33-21ksoftirqd/209:15:002
31934996121,7cyclictest33-21ksoftirqd/210:40:122
31934996023,5cyclictest33-21ksoftirqd/210:10:002
31934996019,8cyclictest33-21ksoftirqd/209:20:172
31934995926,8cyclictest33-21ksoftirqd/210:50:122
31934995926,10cyclictest33-21ksoftirqd/211:45:292
31934995924,4cyclictest33-21ksoftirqd/211:15:242
31934995922,6cyclictest33-21ksoftirqd/207:20:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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