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2026-07-18 - 23:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jul 18, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
88302203169,23sleep20-21swapper/207:09:432
85152203170,22sleep10-21swapper/107:05:371
85172202168,23sleep30-21swapper/307:05:383
85192201168,22sleep00-21swapper/007:05:390
835521340,5sleep3915699cyclictest09:20:253
915599770,75cyclictest9120-21kworker/2:209:35:332
9153996028,3cyclictest9-21ksoftirqd/012:25:150
9154995922,6cyclictest25-21ksoftirqd/108:37:401
9154995822,8cyclictest25-21ksoftirqd/110:38:561
9154995623,6cyclictest25-21ksoftirqd/109:05:191
91382560,6sleep341-21ksoftirqd/309:25:103
139391560,0ptp4l401ktimersoftd/310:56:533
9153995521,7cyclictest9-21ksoftirqd/012:00:180
296292550,3sleep10-21swapper/110:05:241
296292550,3sleep10-21swapper/110:05:241
9154995451,2cyclictest231rcuc/109:37:251
9154995451,2cyclictest231rcuc/108:46:421
9154995421,9cyclictest25-21ksoftirqd/111:45:251
9154995421,6cyclictest25-21ksoftirqd/109:21:131
9153995420,4cyclictest9-21ksoftirqd/009:30:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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