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2026-02-05 - 12:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Feb 05, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8482206173,22sleep20-21swapper/219:08:432
8482206173,22sleep20-21swapper/219:08:432
6802203170,22sleep30-21swapper/319:06:393
6802203170,22sleep30-21swapper/319:06:393
7802202168,22sleep10-21swapper/119:07:501
7802202168,22sleep10-21swapper/119:07:501
6822199165,23sleep00-21swapper/019:06:400
6822199165,23sleep00-21swapper/019:06:400
139391660,1ptp4l401ktimersoftd/323:55:113
124099620,22cyclictest17503-21expr21:55:280
124099610,20cyclictest17121-21irqstats00:10:180
124099600,20cyclictest13064-21irqrtprio22:55:180
104582570,2sleep10-21swapper/121:40:251
139391550,1ptp4l401ktimersoftd/319:10:153
208382540,2sleep30-21swapper/320:55:223
139391530,1ptp4l401ktimersoftd/321:55:023
124099520,18cyclictest3085-21mailstats21:25:240
65272510,2sleep00-21swapper/023:50:130
124099460,33cyclictest22671-21awk22:05:280
139391430,0ptp4l401ktimersoftd/323:05:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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