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2026-03-12 - 14:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Mar 12, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121252232166,22sleep00-21swapper/019:06:060
139491207168,27phc2sys0-21swapper/319:07:103
122092205172,22sleep10-21swapper/119:07:121
121172203170,22sleep20-21swapper/219:06:002
2409521610,3sleep31272199cyclictest20:40:163
516921560,6sleep31272199cyclictest21:10:003
12720996732,5cyclictest33-21ksoftirqd/223:25:002
139391650,1ptp4l401ktimersoftd/319:26:443
129932650,7sleep11271999cyclictest23:40:141
139391640,1ptp4l401ktimersoftd/321:30:103
139391640,1ptp4l401ktimersoftd/300:28:283
12720996431,4cyclictest33-21ksoftirqd/222:20:232
12720996230,6cyclictest33-21ksoftirqd/219:10:242
12720996228,5cyclictest33-21ksoftirqd/200:20:002
12720996128,9cyclictest33-21ksoftirqd/219:55:012
12720996125,4cyclictest33-21ksoftirqd/223:45:272
12719996132,4cyclictest25-21ksoftirqd/122:50:231
12718996129,4cyclictest9-21ksoftirqd/000:20:000
12720996031,3cyclictest33-21ksoftirqd/222:05:002
12720996029,9cyclictest33-21ksoftirqd/223:40:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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