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2026-02-04 - 12:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Feb 04, 2026 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491201164,25phc2sys0-21swapper/319:07:413
146012198165,22sleep20-21swapper/219:07:582
126232197165,22sleep10-21swapper/119:05:081
145742192159,22sleep00-21swapper/019:07:370
2167521360,7sleep11505199cyclictest22:45:151
15052997217,53cyclictest16087-21kworker/2:222:10:132
167062620,2sleep30-21swapper/321:25:263
15052996014,44cyclictest5791-21kworker/2:019:15:332
139391590,1ptp4l401ktimersoftd/321:30:253
290812580,2sleep20-21swapper/220:45:212
15052995812,44cyclictest16087-21kworker/2:220:21:142
1505299558,45cyclictest20379-21kworker/2:200:10:332
139391530,1ptp4l391rcuc/323:45:313
139391490,1ptp4l401ktimersoftd/323:11:513
152782480,2sleep30-21swapper/322:30:213
15052994741,4cyclictest31751-21cron22:00:002
258822450,2sleep10-21swapper/121:45:221
139391440,0ptp4l401ktimersoftd/320:15:173
15053994335,5cyclictest31515-21grep23:05:183
139391430,0ptp4l401ktimersoftd/320:05:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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