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2025-12-22 - 08:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Dec 22, 2025 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53392204169,24sleep20-21swapper/219:07:022
139491204169,23phc2sys0-21swapper/319:09:403
52522202169,22sleep00-21swapper/019:06:000
54622198165,22sleep10-21swapper/119:08:381
1394918363,11phc2sys0-21swapper/319:10:013
139391660,0ptp4l401ktimersoftd/322:10:283
185042640,3sleep318509-21irqrtprio19:35:193
144282530,2sleep00-21swapper/022:50:000
139391490,1ptp4l401ktimersoftd/320:59:513
5864994539,3cyclictest13748-21cron23:54:592
139391440,0ptp4l401ktimersoftd/323:38:133
139391410,1ptp4l401ktimersoftd/323:23:143
139391410,0ptp4l401ktimersoftd/321:37:183
139391410,0ptp4l401ktimersoftd/321:37:173
5865994035,3cyclictest41-21ksoftirqd/319:25:013
5862993932,4cyclictest4245-21wc23:35:150
57898390,6rtkit-daemon0-21swapper/123:37:051
139391390,0ptp4l401ktimersoftd/323:15:233
5865993833,2cyclictest23331-21fschecks_count22:00:173
5865993732,2cyclictest41-21ksoftirqd/320:35:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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