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2026-01-13 - 09:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jan 13, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491225198,18phc2sys0-21swapper/319:05:583
291302204171,22sleep00-21swapper/019:06:010
291322201168,22sleep20-21swapper/219:06:042
291262196164,21sleep10-21swapper/119:05:591
2557021460,4sleep12973599cyclictest22:25:201
3165221400,2sleep32973799cyclictest20:20:183
1566421320,2sleep00-21swapper/022:05:170
75922750,5sleep12973599cyclictest00:05:001
2973799650,20cyclictest23914-21/usr/sbin/munin23:30:153
116622580,3sleep30-21swapper/323:05:133
2973799570,27cyclictest5487-21irqstats19:25:183
29734995548,3cyclictest25528-21wc23:35:000
2973799540,27cyclictest8896-21/usr/sbin/munin23:00:293
2973799520,19cyclictest23294-21/usr/sbin/munin21:15:233
87712480,2sleep20-21swapper/200:05:222
139391440,0ptp4l401ktimersoftd/321:39:103
139391440,0ptp4l401ktimersoftd/320:40:333
2973799431,39cyclictest25973-21cron20:09:593
139391430,0ptp4l401ktimersoftd/323:15:493
139391430,0ptp4l401ktimersoftd/322:08:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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