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2026-02-19 - 05:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Feb 19, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
96512217178,31sleep10-21swapper/119:09:581
139491203168,23phc2sys0-21swapper/319:05:053
93092199166,22sleep20-21swapper/219:06:222
93122197164,22sleep00-21swapper/019:06:240
2858321420,3sleep0994599cyclictest23:10:010
9946996631,9cyclictest25-21ksoftirqd/100:10:251
9946996631,9cyclictest25-21ksoftirqd/100:10:241
114532660,6sleep2994799cyclictest22:35:132
9945996028,4cyclictest9-21ksoftirqd/020:15:130
9945995828,5cyclictest9-21ksoftirqd/020:10:240
9945995826,4cyclictest9-21ksoftirqd/023:40:250
994699576,7cyclictest28089-21strings22:00:211
994699565,9cyclictest3462-21grep22:15:261
9945995625,4cyclictest9-21ksoftirqd/000:30:210
9945995526,3cyclictest9-21ksoftirqd/020:30:160
9945995521,7cyclictest9-21ksoftirqd/000:05:140
9945995521,3cyclictest9-21ksoftirqd/023:35:280
9945995520,4cyclictest9-21ksoftirqd/023:35:000
994699545,7cyclictest31840-21cpuspeed_turbos22:10:131
994699544,5cyclictest21560-21grep20:40:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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