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2026-05-29 - 17:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri May 29, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
217252229202,18sleep00-21swapper/007:09:580
139491207172,23phc2sys0-21swapper/307:05:433
215292203171,21sleep20-21swapper/207:07:312
215282203170,22sleep10-21swapper/107:07:311
1363121650,6sleep22202199cyclictest08:25:132
1098421360,3sleep12202099cyclictest11:50:111
57898920,70rtkit-daemon0-21swapper/207:10:022
22019999037,6cyclictest9-21ksoftirqd/011:54:110
22022998618,4cyclictest41-21ksoftirqd/311:53:413
22019997432,7cyclictest9-21ksoftirqd/010:18:280
22019996332,6cyclictest9-21ksoftirqd/008:20:000
252132620,5sleep12202099cyclictest11:10:201
22019996231,7cyclictest9-21ksoftirqd/010:55:000
22022996112,4cyclictest41-21ksoftirqd/310:18:293
22019995926,7cyclictest9-21ksoftirqd/010:05:000
22019995926,6cyclictest9-21ksoftirqd/012:05:270
22019995826,6cyclictest9-21ksoftirqd/007:20:150
22019995822,4cyclictest9-21ksoftirqd/011:00:240
22019995819,6cyclictest9-21ksoftirqd/010:30:240
22019995726,7cyclictest9-21ksoftirqd/008:00:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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