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2026-06-28 - 05:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jun 28, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
293672228163,21sleep20-21swapper/219:08:382
293712207173,22sleep10-21swapper/119:08:411
139491205172,22phc2sys0-21swapper/319:05:363
273432200167,22sleep00-21swapper/019:05:110
2485021500,6sleep12976499cyclictest20:05:211
139391770,1ptp4l391rcuc/322:40:233
170302690,2sleep10-21swapper/120:55:241
139391680,1ptp4l391rcuc/322:15:253
29766996526,8cyclictest41-21ksoftirqd/319:40:173
22682620,7sleep22976599cyclictest19:20:132
75442610,3sleep02976399cyclictest00:00:010
61032610,2sleep20-21swapper/221:40:222
29766996025,7cyclictest41-21ksoftirqd/319:20:143
29766995922,4cyclictest41-21ksoftirqd/319:55:143
89212580,2sleep30-21swapper/320:40:173
2976699576,6cyclictest31384-21dpkg22:35:003
29766995722,10cyclictest41-21ksoftirqd/322:35:103
29763995622,8cyclictest9-21ksoftirqd/021:15:000
139391540,46ptp4l0-21swapper/319:10:003
139391540,46ptp4l0-21swapper/319:10:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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