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2026-01-07 - 16:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jan 07, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
308152205171,22sleep20-21swapper/207:07:492
308452201168,22sleep00-21swapper/007:08:110
306332201168,22sleep30-21swapper/307:05:293
306962197164,22sleep10-21swapper/107:06:151
139391710,1ptp4l401ktimersoftd/309:49:563
229992660,4sleep20-21swapper/209:05:222
125782640,2sleep10-21swapper/107:35:271
306592630,2sleep30-21swapper/309:20:233
75422610,3sleep30-21swapper/307:25:223
139391610,1ptp4l401ktimersoftd/308:43:143
139391550,1ptp4l401ktimersoftd/310:24:483
135792520,2sleep33141999cyclictest07:40:143
31418994811,4cyclictest33-21ksoftirqd/210:40:002
31418994612,10cyclictest33-21ksoftirqd/212:30:002
31418994510,9cyclictest33-21ksoftirqd/208:15:012
3141899448,6cyclictest33-21ksoftirqd/208:10:002
31418994413,4cyclictest33-21ksoftirqd/208:30:162
139391430,0ptp4l401ktimersoftd/312:13:263
31418994223,16cyclictest33-21ksoftirqd/207:40:012
31418994213,4cyclictest33-21ksoftirqd/209:10:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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