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2026-07-26 - 04:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jul 26, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491216172,33phc2sys0-21swapper/319:07:463
278162206171,23sleep20-21swapper/219:09:592
277832205172,22sleep10-21swapper/119:09:351
275862203169,23sleep00-21swapper/019:07:010
28109996531,4cyclictest9-21ksoftirqd/022:24:590
28109996432,4cyclictest9-21ksoftirqd/021:20:000
28109996331,5cyclictest9-21ksoftirqd/022:50:140
28109996222,11cyclictest9-21ksoftirqd/022:30:250
28109996131,4cyclictest9-21ksoftirqd/020:05:250
28109996128,4cyclictest9-21ksoftirqd/020:25:140
28109996026,7cyclictest9-21ksoftirqd/020:45:150
28109996026,4cyclictest9-21ksoftirqd/022:15:260
28109996023,8cyclictest9-21ksoftirqd/023:35:270
28109996022,7cyclictest9-21ksoftirqd/023:50:260
28109995929,4cyclictest9-21ksoftirqd/000:20:200
28109995928,4cyclictest9-21ksoftirqd/022:00:220
28109995927,8cyclictest9-21ksoftirqd/019:35:150
28109995926,4cyclictest9-21ksoftirqd/019:55:180
28109995926,3cyclictest9-21ksoftirqd/019:25:140
28109995924,4cyclictest9-21ksoftirqd/019:15:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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