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2026-03-11 - 13:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Mar 11, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30122209173,25sleep30-21swapper/319:09:333
28482205172,22sleep00-21swapper/019:07:250
28552204170,23sleep20-21swapper/219:07:312
28492201168,22sleep10-21swapper/119:07:261
502121750,6sleep3334199cyclictest21:25:193
3339997032,7cyclictest25-21ksoftirqd/121:40:011
3339996429,7cyclictest25-21ksoftirqd/119:20:001
3339996326,7cyclictest25-21ksoftirqd/121:55:191
3339996323,9cyclictest25-21ksoftirqd/120:55:271
3339996323,8cyclictest25-21ksoftirqd/100:25:221
3339996322,8cyclictest25-21ksoftirqd/120:20:161
3339996223,8cyclictest25-21ksoftirqd/121:05:001
3339996223,7cyclictest25-21ksoftirqd/100:20:251
3339996131,8cyclictest25-21ksoftirqd/122:30:231
3339996125,11cyclictest25-21ksoftirqd/123:45:011
3339996122,8cyclictest25-21ksoftirqd/122:00:221
3339996122,8cyclictest25-21ksoftirqd/121:20:251
3339996122,8cyclictest25-21ksoftirqd/121:20:251
3339996122,8cyclictest25-21ksoftirqd/120:00:241
3339996122,7cyclictest25-21ksoftirqd/120:50:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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