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2026-07-05 - 13:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jul 05, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304212207172,23sleep30-21swapper/319:07:503
305782206167,27sleep00-21swapper/019:09:520
305082204170,22sleep20-21swapper/219:08:582
305742203171,21sleep10-21swapper/119:09:491
1594121730,6sleep23088299cyclictest00:15:142
193182780,2sleep20-21swapper/221:00:122
3088099650,26cyclictest13473-21awk23:00:270
223672650,2sleep00-21swapper/022:15:010
323962640,4sleep03088099cyclictest21:25:220
30882996031,7cyclictest33-21ksoftirqd/222:40:242
30882996026,9cyclictest33-21ksoftirqd/222:25:242
139391600,1ptp4l401ktimersoftd/322:00:193
30882995922,7cyclictest33-21ksoftirqd/200:40:012
30882995829,6cyclictest33-21ksoftirqd/219:25:002
30882995825,3cyclictest33-21ksoftirqd/221:05:252
30882995824,3cyclictest33-21ksoftirqd/223:10:242
30882995729,9cyclictest33-21ksoftirqd/221:10:252
30882995726,10cyclictest33-21ksoftirqd/222:45:412
30882995625,4cyclictest33-21ksoftirqd/220:05:182
30882995622,4cyclictest33-21ksoftirqd/223:20:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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