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2026-01-09 - 00:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jan 08, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491245196,38phc2sys0-21swapper/307:09:583
19082201168,22sleep20-21swapper/207:07:472
18502199165,23sleep00-21swapper/007:07:000
17372197163,22sleep10-21swapper/107:05:321
139391680,1ptp4l401ktimersoftd/308:17:363
244832620,2sleep20-21swapper/210:15:192
143212600,3sleep1241ktimersoftd/107:35:001
134491590,7getstats259599cyclictest10:29:543
139391560,1ptp4l401ktimersoftd/307:58:003
134491560,7getstats259599cyclictest07:49:533
139391540,1ptp4l401ktimersoftd/308:21:533
139391520,1ptp4l401ktimersoftd/312:32:523
134391460,8getstats259599cyclictest10:36:253
139391450,1ptp4l0-21swapper/310:40:373
2595994236,3cyclictest41-21ksoftirqd/311:55:003
139391420,1ptp4l401ktimersoftd/307:54:053
139391420,0ptp4l401ktimersoftd/307:16:523
2593994127,12cyclictest25-21ksoftirqd/109:30:111
259399410,2cyclictest0-21swapper/109:08:441
2592993932,4cyclictest9-21ksoftirqd/008:35:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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