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2026-02-27 - 22:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Feb 27, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491230165,21phc2sys0-21swapper/307:09:463
134462202169,22sleep10-21swapper/107:06:071
136502201167,22sleep00-21swapper/007:08:400
136122200168,21sleep20-21swapper/207:08:162
1280021470,4sleep01404699cyclictest09:20:200
1375528263,10sleep10-21swapper/107:10:011
139391790,2ptp4l391rcuc/310:10:183
1404699660,26cyclictest12382-21df_abs11:35:140
265842630,2sleep10-21swapper/110:55:241
1404699630,21cyclictest26273-21grep07:35:110
139391610,1ptp4l401ktimersoftd/311:05:093
1404699590,19cyclictest7756-21grep11:25:160
1404699571,28cyclictest2518-21gnome-shell12:30:580
150702560,2sleep00-21swapper/009:25:170
150702560,2sleep00-21swapper/009:25:170
139391540,1ptp4l401ktimersoftd/310:42:203
1404699531,17cyclictest14874-21runrttasks08:15:270
139391520,1ptp4l401ktimersoftd/307:57:033
38322510,2sleep03835-21timerandwakeup09:00:260
1404699510,22cyclictest2751-21taskset10:06:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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