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2025-12-29 - 13:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Dec 29, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180802202169,22sleep00-21swapper/019:05:050
200462201167,23sleep30-21swapper/319:07:093
199872200167,22sleep20-21swapper/219:06:242
200442197165,22sleep10-21swapper/119:07:071
202752162124,13sleep20-21swapper/219:10:012
2410921380,4sleep02056799cyclictest20:25:040
2056799687,20cyclictest26942-21grep21:35:270
139391600,1ptp4l401ktimersoftd/323:40:233
139391560,1ptp4l401ktimersoftd/322:30:103
2056799550,3cyclictest24428-21seq23:45:450
170872550,2sleep00-21swapper/020:10:160
139391550,1ptp4l401ktimersoftd/322:52:193
139391550,1ptp4l401ktimersoftd/322:08:103
139391550,1ptp4l401ktimersoftd/320:47:553
2056799540,3cyclictest17341-21seq23:32:050
139391540,1ptp4l401ktimersoftd/323:51:533
139391530,0ptp4l401ktimersoftd/321:33:443
83692520,10sleep2321ktimersoftd/221:00:002
2056799520,2cyclictest14906-21seq23:26:120
2056799510,3cyclictest3016-21seq23:00:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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