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2025-09-16 - 14:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Sep 16, 2025 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
306562241197,34sleep30-21swapper/319:06:593
308572204169,23sleep10-21swapper/119:09:261
308262203169,23sleep20-21swapper/219:09:022
307372202168,23sleep00-21swapper/019:07:520
1624521760,5sleep23119499cyclictest00:14:592
2077021470,6sleep33119599cyclictest22:09:593
31193995923,10cyclictest25-21ksoftirqd/123:10:211
31195995821,11cyclictest41-21ksoftirqd/300:15:003
31193995855,2cyclictest231rcuc/120:15:281
31193995651,3cyclictest231rcuc/120:47:391
31193995621,4cyclictest25-21ksoftirqd/100:24:471
31193995350,2cyclictest231rcuc/122:16:361
3119399534,8cyclictest25-21ksoftirqd/123:50:111
31193995321,3cyclictest25-21ksoftirqd/120:10:491
31193995320,4cyclictest25-21ksoftirqd/100:27:561
31193995249,2cyclictest231rcuc/123:58:021
31193995249,2cyclictest231rcuc/100:02:201
31193995224,4cyclictest25-21ksoftirqd/100:10:171
31193995219,3cyclictest25-21ksoftirqd/119:39:401
31194995111,9cyclictest33-21ksoftirqd/221:15:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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