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2026-01-04 - 17:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jan 04, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1792423350,1sleep1231rcuc/107:05:041
378222190,5sleep33802-21spawn07:05:023
116722140,5sleep20-21swapper/207:09:382
571921910,4sleep05721-21sh07:08:030
1709121740,6sleep12555499cyclictest07:11:531
1393911250,1ptp4l3503-21looper07:11:323
2909721180,3sleep32556199cyclictest08:15:223
77932810,7sleep02555399cyclictest07:13:110
178572650,3sleep30-21swapper/309:00:143
143702630,7sleep12555499cyclictest11:05:241
118972630,5sleep211874-21sh07:10:182
252182580,2sleep10-21swapper/112:35:261
139391530,6ptp4l2556199cyclictest12:25:063
2555799451,5cyclictest33-21ksoftirqd/210:55:252
25557994412,4cyclictest33-21ksoftirqd/208:05:162
139391440,0ptp4l401ktimersoftd/310:14:213
25557994328,12cyclictest33-21ksoftirqd/209:05:002
25557994325,14cyclictest33-21ksoftirqd/208:50:122
2555799418,4cyclictest33-21ksoftirqd/212:00:002
25557994130,9cyclictest33-21ksoftirqd/211:25:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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