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2025-11-08 - 13:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Nov 08, 2025 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191205171,22phc2sys0-21swapper/319:09:023
148352204170,22sleep20-21swapper/219:05:342
150732203171,21sleep10-21swapper/119:08:311
151542196163,22sleep00-21swapper/019:09:330
946921470,7sleep21548099cyclictest21:10:222
1369911130,89ptp4l0-21swapper/319:10:013
1518728362,11sleep20-21swapper/219:10:002
277472660,4sleep00-21swapper/020:40:230
15481996529,4cyclictest41-21ksoftirqd/320:15:003
15481996431,7cyclictest41-21ksoftirqd/320:35:013
15481996229,7cyclictest41-21ksoftirqd/320:55:173
15481996228,8cyclictest41-21ksoftirqd/321:55:173
15481996128,4cyclictest41-21ksoftirqd/320:45:143
15481996127,8cyclictest41-21ksoftirqd/323:10:273
15481996125,10cyclictest41-21ksoftirqd/321:20:023
15481996029,5cyclictest41-21ksoftirqd/319:55:003
15481995926,9cyclictest41-21ksoftirqd/300:30:153
15481995925,5cyclictest41-21ksoftirqd/321:25:273
15481995924,8cyclictest41-21ksoftirqd/320:15:203
15481995920,4cyclictest41-21ksoftirqd/300:25:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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