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2026-02-18 - 04:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Feb 18, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206172,22phc2sys0-21swapper/319:06:483
266242202168,22sleep10-21swapper/119:09:091
264712202169,22sleep20-21swapper/219:07:092
266862200167,22sleep00-21swapper/019:09:560
3273821610,5sleep22698699cyclictest22:40:572
2698699701,28cyclictest1243-21fschecks_time20:30:172
2698699670,28cyclictest1416-1kworker/2:2H22:40:002
2698699651,22cyclictest25332-21timerandwakeup22:25:262
2698699640,22cyclictest4306-21date21:44:592
2698699631,22cyclictest9508-21phc2sys23:00:232
2698699621,20cyclictest11719-21missed_timers23:05:202
2698699620,22cyclictest3524-21appstreamcli22:50:022
2698699620,21cyclictest30053-21irqrtprio19:15:192
139391620,1ptp4l401ktimersoftd/323:56:363
2698699600,22cyclictest20444-21cat00:30:212
26985996026,7cyclictest25-21ksoftirqd/121:00:251
26985996025,9cyclictest25-21ksoftirqd/122:25:011
26985996025,6cyclictest25-21ksoftirqd/122:40:171
2698699590,29cyclictest23739-21/usr/sbin/munin20:10:142
26985995930,4cyclictest25-21ksoftirqd/120:50:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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