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2026-09-08 - 07:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Sep 08, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
265202224196,19sleep20-21swapper/219:07:582
139491206172,22phc2sys0-21swapper/319:08:393
266072205172,22sleep10-21swapper/119:09:071
265232205171,23sleep00-21swapper/019:08:000
291892620,2sleep10-21swapper/120:20:141
139391550,3ptp4l401ktimersoftd/300:03:153
139391540,1ptp4l401ktimersoftd/320:59:123
139391530,39ptp4l0-21swapper/319:10:003
26973994741,3cyclictest11362-21grep20:50:143
139391440,0ptp4l401ktimersoftd/323:26:593
139391440,0ptp4l401ktimersoftd/322:50:133
2697299430,40cyclictest3599-21ls20:35:002
139391420,4ptp4l401ktimersoftd/300:39:403
139391420,0ptp4l401ktimersoftd/319:50:213
139391410,1ptp4l401ktimersoftd/321:46:113
139391410,0ptp4l401ktimersoftd/323:40:213
26970993933,3cyclictest9-21ksoftirqd/020:40:000
26970993933,3cyclictest9-21ksoftirqd/020:40:000
26971993833,3cyclictest3681-21uname23:55:191
26971993732,3cyclictest25-21ksoftirqd/122:35:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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