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2026-09-05 - 05:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Sep 05, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114282206173,22sleep20-21swapper/219:08:132
113572206171,24sleep30-21swapper/319:07:183
112102206173,22sleep10-21swapper/119:05:311
115182205173,23sleep00-21swapper/019:09:240
1393911150,1ptp4l15205-21memory23:45:193
1393911150,1ptp4l15205-21memory23:45:193
11857996225,9cyclictest9-21ksoftirqd/023:50:220
11857996129,3cyclictest9-21ksoftirqd/022:15:110
11857996129,12cyclictest9-21ksoftirqd/023:05:150
11857996127,7cyclictest9-21ksoftirqd/019:55:180
11857996123,9cyclictest9-21ksoftirqd/021:40:200
11857996023,10cyclictest9-21ksoftirqd/023:20:250
11857996020,11cyclictest9-21ksoftirqd/022:35:230
11857995928,10cyclictest9-21ksoftirqd/019:40:160
11857995927,6cyclictest9-21ksoftirqd/020:35:000
11857995925,11cyclictest9-21ksoftirqd/020:20:200
11857995922,8cyclictest9-21ksoftirqd/021:35:170
11857995827,4cyclictest9-21ksoftirqd/019:45:150
11857995826,4cyclictest9-21ksoftirqd/019:35:010
11857995825,10cyclictest9-21ksoftirqd/023:30:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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