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2026-09-06 - 07:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Sep 06, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2532322650,27sleep20-21swapper/219:05:182
139491230162,23phc2sys0-21swapper/319:09:543
265342229164,22sleep10-21swapper/119:07:331
265432207174,22sleep00-21swapper/019:07:390
2213521510,5sleep32701999cyclictest20:05:223
1394918866,11phc2sys0-21swapper/319:10:003
1394918866,11phc2sys0-21swapper/319:10:003
23022570,5sleep125-21ksoftirqd/122:50:001
152822560,5sleep015286-21timerandwakeup19:50:270
269312510,2sleep30-21swapper/321:25:143
27019995028,10cyclictest41-21ksoftirqd/323:05:253
105632500,1sleep00-21swapper/020:50:200
2701999483,7cyclictest41-21ksoftirqd/320:19:593
27019994715,8cyclictest41-21ksoftirqd/320:00:003
27019994715,8cyclictest41-21ksoftirqd/320:00:003
27019994714,7cyclictest41-21ksoftirqd/320:50:183
27019994538,4cyclictest16735-21sh23:20:003
27019994433,9cyclictest41-21ksoftirqd/323:20:203
27019994415,3cyclictest41-21ksoftirqd/320:25:293
27019994410,7cyclictest41-21ksoftirqd/323:25:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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