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2026-01-13 - 02:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jan 12, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123302205172,22sleep30-21swapper/307:07:203
124522202169,22sleep10-21swapper/107:08:551
123292200168,22sleep20-21swapper/207:07:182
124512198164,23sleep00-21swapper/007:08:530
2416521320,7sleep01299699cyclictest07:30:270
2416521320,7sleep01299699cyclictest07:30:270
1394918362,11phc2sys0-21swapper/307:10:013
18342620,4sleep3391rcuc/311:15:153
1299799617,11cyclictest9466-21irqrtprio11:30:181
1299999609,9cyclictest14052-21chrt10:31:093
1299799607,11cyclictest30439-21cut07:45:201
69472590,2sleep30-21swapper/310:19:153
1299799597,11cyclictest15841-21date11:45:001
1299799587,17cyclictest13846-21cut07:10:181
1299799587,10cyclictest26631-21timerwakeupswit09:50:261
1299799571,10cyclictest23028-21readlink08:35:221
1299799558,17cyclictest18598-21sed09:35:181
1299999548,10cyclictest29429-21basename11:05:163
1299799547,15cyclictest2245-21ls09:00:201
1299799537,14cyclictest32487-21meminfo11:10:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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