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2026-03-25 - 07:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Mar 25, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491245199,35phc2sys0-21swapper/319:06:593
281782203171,21sleep10-21swapper/119:06:071
281792202168,23sleep20-21swapper/219:06:082
281722202169,22sleep00-21swapper/019:06:010
283392720,1sleep128343-21missed_timers22:30:221
139391660,1ptp4l401ktimersoftd/322:47:513
285862620,1sleep30-21swapper/320:15:173
146422570,2sleep20-21swapper/219:45:232
46542560,2sleep00-21swapper/023:55:260
22672520,2sleep10-21swapper/121:35:221
139391520,1ptp4l401ktimersoftd/300:29:373
139391450,0ptp4l401ktimersoftd/322:24:073
28779994332,9cyclictest41-21ksoftirqd/321:20:143
28776994328,13cyclictest9-21ksoftirqd/000:35:110
139391430,0ptp4l401ktimersoftd/323:49:553
139391430,0ptp4l401ktimersoftd/323:49:553
139391430,0ptp4l401ktimersoftd/319:44:333
139391430,0ptp4l401ktimersoftd/319:44:323
139391420,0ptp4l401ktimersoftd/319:45:053
28779994130,9cyclictest41-21ksoftirqd/300:30:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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