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2026-08-21 - 23:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Aug 21, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207163,33phc2sys0-21swapper/307:07:243
146962203170,22sleep10-21swapper/107:06:561
128082202168,23sleep20-21swapper/207:05:072
128012201168,22sleep00-21swapper/007:05:010
1393911150,1ptp4l24569-21apt07:30:013
139391800,2ptp4l391rcuc/311:35:213
139391800,1ptp4l391rcuc/312:10:223
15234996934,7cyclictest33-21ksoftirqd/210:30:002
15234996930,7cyclictest33-21ksoftirqd/211:55:262
15234996733,5cyclictest33-21ksoftirqd/210:35:002
15234996632,6cyclictest33-21ksoftirqd/208:00:002
15234996628,7cyclictest33-21ksoftirqd/211:15:242
15234996532,5cyclictest33-21ksoftirqd/208:25:012
15234996532,5cyclictest33-21ksoftirqd/208:25:012
15234996532,4cyclictest33-21ksoftirqd/212:35:002
15234996531,6cyclictest33-21ksoftirqd/209:40:212
15234996531,4cyclictest33-21ksoftirqd/211:35:152
15234996529,10cyclictest33-21ksoftirqd/209:50:012
15234996527,7cyclictest33-21ksoftirqd/212:10:242
15234996432,8cyclictest33-21ksoftirqd/207:25:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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