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2026-01-28 - 14:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jan 28, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
91672206174,21sleep20-21swapper/219:09:422
91662206173,22sleep10-21swapper/119:09:401
139491205171,22phc2sys0-21swapper/319:09:303
90162198165,22sleep00-21swapper/019:07:430
9483995728,4cyclictest9-21ksoftirqd/022:30:170
9483995728,4cyclictest9-21ksoftirqd/021:41:570
9483995724,11cyclictest9-21ksoftirqd/023:10:230
9483995628,4cyclictest9-21ksoftirqd/019:30:150
9483995627,4cyclictest9-21ksoftirqd/019:15:170
9483995625,4cyclictest9-21ksoftirqd/020:05:170
9483995528,5cyclictest9-21ksoftirqd/020:45:140
9483995425,4cyclictest9-21ksoftirqd/020:55:190
9483995424,4cyclictest9-21ksoftirqd/022:25:010
9483995423,7cyclictest9-21ksoftirqd/022:05:130
9483995421,5cyclictest9-21ksoftirqd/020:00:270
139391540,1ptp4l401ktimersoftd/323:16:483
9483995328,6cyclictest9-21ksoftirqd/022:45:280
9483995325,4cyclictest9-21ksoftirqd/021:45:200
9483995323,6cyclictest9-21ksoftirqd/020:40:200
9483995321,4cyclictest9-21ksoftirqd/021:15:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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