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2026-09-07 - 07:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Sep 07, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165762241195,35sleep30-21swapper/319:07:593
164102208175,22sleep10-21swapper/119:05:561
165422204171,22sleep00-21swapper/019:07:320
164862203169,22sleep20-21swapper/219:06:492
187522770,2sleep00-21swapper/019:10:280
17025996331,4cyclictest9-21ksoftirqd/021:40:200
93402620,2sleep10-21swapper/120:00:201
139391580,1ptp4l401ktimersoftd/319:18:183
139391570,1ptp4l391rcuc/300:20:193
294012540,7sleep31702899cyclictest20:40:253
17025995426,3cyclictest9-21ksoftirqd/021:40:000
139391540,1ptp4l401ktimersoftd/300:39:363
17026995318,7cyclictest25-21ksoftirqd/121:25:271
92282520,2sleep10-21swapper/121:05:271
17025995222,4cyclictest9-21ksoftirqd/020:30:220
300472510,1sleep20-21swapper/221:50:202
17026995020,4cyclictest25-21ksoftirqd/119:35:251
139391500,0ptp4l401ktimersoftd/300:07:573
17026994810,9cyclictest25-21ksoftirqd/123:30:141
17025994820,4cyclictest9-21ksoftirqd/019:50:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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