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2026-09-24 - 06:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Sep 24, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2490622180,6sleep124892-21sh19:08:321
3220722170,6sleep332204-21spawn19:05:533
192452202168,23sleep00-21swapper/019:06:510
191742202169,22sleep20-21swapper/219:06:242
315502860,5sleep315957-21looper19:11:153
162552710,3sleep2311rcuc/219:11:292
84632700,5sleep341-21ksoftirqd/300:20:003
7572690,4sleep0761-21fschecks_time19:10:150
1761099678,12cyclictest10199-21wc19:55:003
1761099668,13cyclictest834-21cut20:40:173
1761099658,18cyclictest3697-21latency_hist00:10:003
1761099658,11cyclictest13225-21latency_hist22:15:013
1761099657,11cyclictest17417-21grep20:10:003
1761099648,11cyclictest26542-21sed19:20:183
1761099637,11cyclictest4646-21cut00:10:153
216632620,4sleep121644-21sh19:12:231
129182620,1sleep00-21swapper/023:20:170
1761099617,11cyclictest22206-21latency_hist20:20:013
1761099608,19cyclictest27215-21cut21:35:183
1761099607,11cyclictest1749-21sed21:50:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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