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2026-01-20 - 23:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jan 20, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
312512208160,36sleep20-21swapper/207:07:182
313292203169,22sleep30-21swapper/307:08:193
313642202170,21sleep10-21swapper/107:08:451
313012199166,22sleep00-21swapper/007:07:570
1925021620,2sleep13176199cyclictest07:50:161
2098321600,7sleep33176399cyclictest07:55:003
139391630,7ptp4l3176399cyclictest11:40:183
159202620,3sleep00-21swapper/008:50:170
31762996110,23cyclictest28022-21latency_hist08:10:002
189032590,3sleep118900-21cpu10:05:111
255532570,1sleep10-21swapper/111:25:221
139391570,1ptp4l401ktimersoftd/310:01:043
49832560,4sleep24985-21fschecks_time09:35:162
139391540,1ptp4l391rcuc/307:20:223
44432530,1sleep10-21swapper/107:20:131
135922520,2sleep00-21swapper/011:00:180
202222500,1sleep00-21swapper/010:05:220
139391480,1ptp4l401ktimersoftd/311:38:423
3176199431,39cyclictest304-21wc08:20:001
139391420,0ptp4l401ktimersoftd/308:42:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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