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2026-05-17 - 20:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun May 17, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
269082218162,44sleep10-21swapper/107:08:061
269082218162,44sleep10-21swapper/107:08:051
139491205171,22phc2sys0-21swapper/307:09:223
139491205171,22phc2sys0-21swapper/307:09:213
267602202169,22sleep20-21swapper/207:06:102
267602202169,22sleep20-21swapper/207:06:102
267582202169,22sleep00-21swapper/007:06:080
267582202169,22sleep00-21swapper/007:06:080
2874921520,3sleep10-21swapper/111:40:231
139391670,1ptp4l401ktimersoftd/308:44:423
27356996124,7cyclictest25-21ksoftirqd/112:20:221
18592610,2sleep00-21swapper/009:39:590
27356995723,3cyclictest25-21ksoftirqd/109:20:451
27356995722,6cyclictest25-21ksoftirqd/107:40:201
27356995624,6cyclictest25-21ksoftirqd/109:40:001
139391560,1ptp4l401ktimersoftd/307:12:163
27356995423,7cyclictest25-21ksoftirqd/112:19:251
139391540,1ptp4l391rcuc/310:31:413
139391540,1ptp4l391rcuc/310:31:403
27356995324,8cyclictest25-21ksoftirqd/111:25:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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