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2026-09-04 - 05:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Sep 04, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39172223158,21sleep00-21swapper/019:09:360
38592215181,23sleep20-21swapper/219:08:502
38902204169,23sleep30-21swapper/319:09:163
38832204172,21sleep10-21swapper/119:09:101
575521530,6sleep2424299cyclictest22:35:022
139391760,0ptp4l391rcuc/323:10:223
4243996329,7cyclictest41-21ksoftirqd/319:35:003
4243996128,8cyclictest41-21ksoftirqd/320:20:263
4243996121,10cyclictest41-21ksoftirqd/322:45:003
4243996027,4cyclictest41-21ksoftirqd/321:05:143
4243996025,4cyclictest41-21ksoftirqd/320:15:163
4243995825,4cyclictest41-21ksoftirqd/323:40:143
4243995824,5cyclictest41-21ksoftirqd/322:35:193
4243995821,4cyclictest41-21ksoftirqd/323:05:013
4243995820,9cyclictest41-21ksoftirqd/321:35:113
4243995730,5cyclictest41-21ksoftirqd/322:05:163
4243995720,4cyclictest41-21ksoftirqd/322:00:143
4243995624,7cyclictest41-21ksoftirqd/319:40:273
4243995623,4cyclictest41-21ksoftirqd/319:25:243
4243995522,4cyclictest41-21ksoftirqd/320:50:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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