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2026-06-14 - 16:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jun 14, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
42352205172,22sleep10-21swapper/107:09:491
139491205171,22phc2sys0-21swapper/307:06:523
41192202169,22sleep20-21swapper/207:08:272
41172202168,22sleep00-21swapper/007:08:250
961321570,6sleep0454299cyclictest11:50:020
483421520,5sleep34838-21cpuspeed_turbos11:40:133
4545997538,3cyclictest41-21ksoftirqd/312:00:293
64302700,5sleep16431-21unixbench_singl11:40:271
4545996434,4cyclictest41-21ksoftirqd/310:10:173
4545996427,8cyclictest41-21ksoftirqd/309:15:003
4545996332,4cyclictest41-21ksoftirqd/310:15:253
4545996231,4cyclictest41-21ksoftirqd/310:05:303
4545996125,9cyclictest41-21ksoftirqd/309:20:003
4545996121,8cyclictest41-21ksoftirqd/307:35:233
4545996029,7cyclictest41-21ksoftirqd/310:20:153
4545995930,4cyclictest41-21ksoftirqd/309:55:263
4545995927,7cyclictest41-21ksoftirqd/312:35:253
4545995924,8cyclictest41-21ksoftirqd/311:50:183
4545995924,8cyclictest41-21ksoftirqd/310:50:233
4545995924,8cyclictest41-21ksoftirqd/310:50:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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