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2026-05-28 - 14:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu May 28, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491233168,22phc2sys0-21swapper/319:05:393
192242202169,22sleep10-21swapper/119:09:061
191282199166,22sleep20-21swapper/219:07:492
171572197164,22sleep00-21swapper/019:05:020
116121770,6sleep01958999cyclictest00:05:290
1702421370,5sleep01958999cyclictest20:10:170
1702421370,5sleep01958999cyclictest20:10:160
19589997214,10cyclictest29173-21gpgv19:30:000
19589996911,17cyclictest27123-21/usr/sbin/munin23:55:230
19589996811,15cyclictest14202-21expr20:05:130
19589996811,15cyclictest14202-21expr20:05:130
19589996514,9cyclictest6830-21ls00:20:000
19589996513,9cyclictest1775-21ls21:55:000
19589996512,11cyclictest27862-21cut21:40:170
19589996510,12cyclictest26661-21cut22:45:190
19589996413,9cyclictest28958-21cut22:50:180
19589996413,10cyclictest23484-21sort20:25:000
19589996411,15cyclictest1640-21irqrtprio20:45:170
19589996411,11cyclictest17273-21cut23:35:000
19589996410,10cyclictest18388-21latency_hist22:30:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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