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2026-01-21 - 06:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jan 21, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491227164,52phc2sys0-21swapper/319:08:483
197132201168,22sleep10-21swapper/119:06:151
198312199167,21sleep20-21swapper/219:07:402
197822199167,21sleep00-21swapper/019:07:020
139491135111,13phc2sys0-21swapper/319:10:013
139491135111,13phc2sys0-21swapper/319:10:013
29662870,2sleep3401ktimersoftd/300:07:313
2030499677,17cyclictest0-21swapper/223:55:252
20304996712,18cyclictest30228-21grep20:35:232
2030499669,16cyclictest0-21swapper/222:00:152
2030499618,15cyclictest0-21swapper/221:17:462
2030499617,16cyclictest0-21swapper/219:30:162
20304996110,10cyclictest23744-21apt-get22:40:032
2030499609,16cyclictest27254-21sed22:45:182
2030499608,20cyclictest0-21swapper/221:30:122
2030499598,17cyclictest0-21swapper/219:35:242
2030499597,17cyclictest0-21swapper/223:35:222
2030499588,16cyclictest0-21swapper/220:50:252
2030499586,14cyclictest0-21swapper/200:10:162
20304995810,10cyclictest0-21swapper/219:20:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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