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2026-08-04 - 12:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Aug 04, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246592205172,22sleep00-21swapper/019:08:360
139491205170,23phc2sys0-21swapper/319:05:053
246262202169,22sleep20-21swapper/219:08:102
244562202170,21sleep10-21swapper/119:06:041
2476728363,11sleep00-21swapper/019:10:010
209132740,2sleep00-21swapper/023:30:150
139391600,1ptp4l401ktimersoftd/319:30:143
25062995326,7cyclictest33-21ksoftirqd/221:20:002
139391530,1ptp4l401ktimersoftd/321:21:303
139391520,1ptp4l401ktimersoftd/320:09:273
25062995126,3cyclictest33-21ksoftirqd/220:55:202
25062995123,7cyclictest33-21ksoftirqd/223:40:022
25062995123,4cyclictest33-21ksoftirqd/200:30:222
25062995022,6cyclictest33-21ksoftirqd/221:10:272
25062995021,4cyclictest33-21ksoftirqd/220:25:152
190152500,1sleep20-21swapper/223:25:192
25062994928,3cyclictest33-21ksoftirqd/222:35:252
25062994922,4cyclictest33-21ksoftirqd/220:20:272
25062994921,3cyclictest33-21ksoftirqd/222:10:252
25062994919,3cyclictest33-21ksoftirqd/223:20:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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