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2026-07-31 - 09:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jul 31, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
226192205171,23sleep00-21swapper/019:07:230
227072204171,22sleep10-21swapper/119:08:321
225532204171,22sleep20-21swapper/219:06:322
139491204171,22phc2sys0-21swapper/319:09:123
139491163124,13phc2sys0-21swapper/319:10:013
23114997816,60cyclictest0-21swapper/119:30:521
139391740,1ptp4l391rcuc/320:15:263
139391660,1ptp4l401ktimersoftd/319:15:593
139391640,0ptp4l401ktimersoftd/320:59:233
139391620,1ptp4l401ktimersoftd/323:00:293
16762600,2sleep20-21swapper/219:30:272
23114995612,42cyclictest0-21swapper/123:30:331
23113995424,7cyclictest9-21ksoftirqd/021:15:150
23113995216,7cyclictest9-21ksoftirqd/022:45:240
14952520,2sleep30-21swapper/320:40:113
139391510,0ptp4l401ktimersoftd/322:18:343
23115995022,4cyclictest33-21ksoftirqd/222:40:192
23113995021,5cyclictest9-21ksoftirqd/021:00:270
294922490,2sleep10-21swapper/122:45:181
23113994917,6cyclictest9-21ksoftirqd/020:13:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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