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2026-02-03 - 05:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Feb 03, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207163,33phc2sys0-21swapper/319:08:473
291432202169,22sleep00-21swapper/019:09:560
288932202169,22sleep10-21swapper/119:06:481
290562201169,21sleep20-21swapper/219:08:502
139391780,1ptp4l30478-21/usr/sbin/munin20:20:243
29439997525,8cyclictest9-21ksoftirqd/021:45:000
29439997229,5cyclictest9-21ksoftirqd/023:05:100
29441997136,3cyclictest33-21ksoftirqd/221:40:182
139391690,6ptp4l401ktimersoftd/321:30:103
29439996824,7cyclictest9-21ksoftirqd/022:10:140
29439996622,7cyclictest9-21ksoftirqd/023:25:280
29439996619,7cyclictest9-21ksoftirqd/023:15:220
29441996540,7cyclictest33-21ksoftirqd/222:50:012
29441996425,6cyclictest33-21ksoftirqd/221:00:012
29439996421,3cyclictest9-21ksoftirqd/022:50:180
29441996338,12cyclictest33-21ksoftirqd/223:30:282
29439996322,12cyclictest9-21ksoftirqd/000:05:200
29439996223,8cyclictest9-21ksoftirqd/020:20:150
139391620,9ptp4l401ktimersoftd/321:25:293
29439996024,5cyclictest9-21ksoftirqd/023:55:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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