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2026-05-07 - 17:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu May 07, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
206962207172,23sleep30-21swapper/307:06:223
208102202168,23sleep00-21swapper/007:07:520
208892200167,22sleep20-21swapper/207:08:552
209602198165,22sleep10-21swapper/107:09:501
139391670,1ptp4l401ktimersoftd/312:35:183
2141999584,10cyclictest19760-21sed11:35:192
139391570,1ptp4l401ktimersoftd/310:02:013
2141999563,8cyclictest3511-21phc2sys11:00:222
2141999562,11cyclictest17534-21irqrtprio09:15:182
139391560,1ptp4l401ktimersoftd/311:30:213
2141999550,16cyclictest0-21swapper/212:15:232
2141999534,17cyclictest9569-21grep09:00:122
2141999533,17cyclictest15595-21egrep12:35:142
2141999533,11cyclictest29841-21latency_hist10:49:592
2141999530,17cyclictest0-21swapper/210:20:212
2141999523,17cyclictest14153-21date09:10:012
2141999523,17cyclictest14074-21cat10:15:212
2141999523,16cyclictest8278-21grep12:20:112
2141999523,11cyclictest4845-21cat08:50:122
2141999523,11cyclictest2920-21awk07:35:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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