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2026-06-30 - 06:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jun 30, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
80412205170,24sleep20-21swapper/219:05:282
62792205171,22sleep30-21swapper/319:05:053
80802203170,22sleep00-21swapper/019:05:450
80592201168,22sleep10-21swapper/119:05:311
1121921360,6sleep1870599cyclictest21:30:121
139391730,1ptp4l391rcuc/323:25:233
8705996328,4cyclictest25-21ksoftirqd/120:55:001
8704996334,5cyclictest9-21ksoftirqd/000:25:240
8704996227,5cyclictest9-21ksoftirqd/022:15:230
8704996226,8cyclictest9-21ksoftirqd/022:40:260
8705996128,10cyclictest25-21ksoftirqd/121:20:251
8705996124,9cyclictest25-21ksoftirqd/123:25:141
8705996124,10cyclictest25-21ksoftirqd/121:00:151
8704996133,3cyclictest9-21ksoftirqd/000:10:200
8704996130,3cyclictest9-21ksoftirqd/021:25:280
8704996128,3cyclictest9-21ksoftirqd/000:35:190
8705996030,3cyclictest25-21ksoftirqd/120:20:201
8705996024,8cyclictest25-21ksoftirqd/123:50:201
8705996023,10cyclictest25-21ksoftirqd/119:45:001
8705996021,9cyclictest25-21ksoftirqd/120:25:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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