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2026-01-27 - 00:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jan 26, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206173,22phc2sys0-21swapper/307:08:143
139491206173,22phc2sys0-21swapper/307:08:143
80352202169,22sleep20-21swapper/207:08:282
80352202169,22sleep20-21swapper/207:08:282
80332202169,22sleep00-21swapper/007:08:260
80332202169,22sleep00-21swapper/007:08:260
78582202169,22sleep10-21swapper/107:06:101
78582202169,22sleep10-21swapper/107:06:101
139491162123,13phc2sys0-21swapper/307:10:023
166352650,6sleep3845899cyclictest11:55:143
161402540,2sleep20-21swapper/207:25:162
139391540,1ptp4l401ktimersoftd/310:36:103
845799441,40cyclictest13550-21grep11:50:012
139391420,1ptp4l401ktimersoftd/308:06:203
139391420,1ptp4l401ktimersoftd/308:06:203
57898410,2rtkit-daemon0-21swapper/109:37:401
139391410,0ptp4l401ktimersoftd/312:30:133
139391400,0ptp4l401ktimersoftd/309:20:263
57898390,1rtkit-daemon0-21swapper/109:34:301
8455993833,3cyclictest16661-21idleruntime-cro10:50:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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