You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-18 - 01:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jan 17, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
322232202169,22sleep10-21swapper/107:09:511
321742202169,22sleep00-21swapper/007:09:170
139491200166,23phc2sys0-21swapper/307:06:283
319702199167,21sleep20-21swapper/207:06:382
2873121320,2sleep30-21swapper/312:35:263
611821270,7sleep23267299cyclictest07:20:192
611821270,7sleep23267299cyclictest07:20:192
139391860,1ptp4l20044-21/usr/sbin/munin11:10:243
165432590,2sleep20-21swapper/209:55:262
32672995724,4cyclictest33-21ksoftirqd/210:30:222
139391570,1ptp4l401ktimersoftd/310:22:353
139391570,1ptp4l401ktimersoftd/309:59:533
52162560,6sleep09-21ksoftirqd/007:20:130
52162560,6sleep09-21ksoftirqd/007:20:130
32672995624,10cyclictest33-21ksoftirqd/210:45:202
32672995551,2cyclictest321ktimersoftd/210:40:142
32672995525,4cyclictest33-21ksoftirqd/212:15:192
32672995423,4cyclictest33-21ksoftirqd/212:20:192
96042530,5sleep125-21ksoftirqd/110:50:171
3267299536,9cyclictest33-21ksoftirqd/210:50:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional