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2025-12-26 - 20:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Dec 26, 2025 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
228872204170,22sleep30-21swapper/307:06:063
229172203170,22sleep10-21swapper/107:06:281
229132201168,22sleep20-21swapper/207:06:252
228892198165,22sleep00-21swapper/007:06:070
840021740,2sleep02349099cyclictest12:15:150
1835121600,3sleep22349299cyclictest10:20:202
1193721550,6sleep22349299cyclictest09:00:132
1193721550,6sleep22349299cyclictest09:00:132
23491996630,3cyclictest25-21ksoftirqd/111:45:161
23491996422,6cyclictest25-21ksoftirqd/107:55:211
23490996013,4cyclictest9-21ksoftirqd/008:20:010
23492995934,3cyclictest33-21ksoftirqd/211:20:002
23491995928,6cyclictest25-21ksoftirqd/109:05:161
23491995926,7cyclictest25-21ksoftirqd/112:35:001
23490995925,9cyclictest9-21ksoftirqd/012:35:010
23491995730,9cyclictest25-21ksoftirqd/108:35:011
23491995627,7cyclictest25-21ksoftirqd/107:10:141
23491995627,6cyclictest25-21ksoftirqd/110:50:141
23491995614,9cyclictest25-21ksoftirqd/107:50:201
23490995624,8cyclictest9-21ksoftirqd/010:40:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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