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2026-02-12 - 06:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Feb 12, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491226165,50phc2sys0-21swapper/319:07:063
234272202169,22sleep20-21swapper/219:09:002
234562200168,21sleep10-21swapper/119:09:241
232672195162,22sleep00-21swapper/019:06:570
2401399730,70cyclictest0-21swapper/123:40:341
2401499627,10cyclictest30881-21fschecks_time22:45:172
2401499618,11cyclictest32411-21cut23:55:162
2401499618,11cyclictest32411-21cut23:55:162
154542610,2sleep10-21swapper/123:20:141
154542610,2sleep10-21swapper/123:20:141
2401499607,11cyclictest24478-21fschecks_time21:25:162
2401499607,10cyclictest2371-21sed21:45:212
2401499605,16cyclictest20667-21timedrift21:15:242
2401499597,10cyclictest12394-21latency_hist23:14:592
2401499595,11cyclictest16462-21cut22:15:182
24014995910,11cyclictest26917-21timedrift22:35:252
2401499585,11cyclictest13346-21cut23:15:172
2401499583,16cyclictest0-21swapper/200:10:192
24014995810,11cyclictest14688-21awk19:55:242
2401499577,18cyclictest449-21dbus-daemon20:00:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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