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2026-01-21 - 21:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jan 21, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
90032204170,23sleep20-21swapper/207:08:392
139491203169,23phc2sys0-21swapper/307:06:073
90072200168,21sleep10-21swapper/107:08:421
90062200167,22sleep00-21swapper/007:08:410
704421190,7sleep2940999cyclictest10:25:222
940799610,11cyclictest14414-21ps10:40:230
940799600,11cyclictest23460-21sendmail07:40:010
139391580,1ptp4l401ktimersoftd/308:54:593
940799570,16cyclictest0-21swapper/009:20:230
32962570,6sleep3941099cyclictest12:30:273
940799560,12cyclictest20266-21cat08:40:010
940799540,11cyclictest11862-21date09:30:010
940799530,18cyclictest20317-21ps09:45:220
940799530,17cyclictest24311-21/usr/sbin/munin12:10:220
940799520,11cyclictest24107-21cut11:00:220
139391520,39ptp4l0-21swapper/307:10:013
940799510,17cyclictest1300-21snmpd09:13:530
940799510,16cyclictest0-21swapper/008:15:180
297452510,2sleep00-21swapper/009:00:010
297452510,2sleep00-21swapper/009:00:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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