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2026-08-23 - 23:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Aug 23, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
214902220193,18sleep30-21swapper/307:08:583
214892202169,22sleep20-21swapper/207:08:582
214402202169,22sleep00-21swapper/007:08:200
214212201168,22sleep10-21swapper/107:08:041
281362680,6sleep12187099cyclictest09:35:271
139391660,1ptp4l401ktimersoftd/307:26:413
139391650,1ptp4l401ktimersoftd/308:14:183
139391640,1ptp4l401ktimersoftd/312:13:573
139391640,1ptp4l401ktimersoftd/312:13:573
139391530,1ptp4l401ktimersoftd/312:39:033
263762480,5sleep026374-21irqrtprio08:25:170
2187099481,43cyclictest26548-21basename11:50:011
2187099460,45cyclictest0-21swapper/110:27:431
2187099460,45cyclictest0-21swapper/110:27:431
57898450,2rtkit-daemon577-21rtkit-daemon09:13:380
21870994516,27cyclictest0-21swapper/107:15:441
98512440,2sleep20-21swapper/210:05:242
139391420,0ptp4l401ktimersoftd/311:10:183
139391410,0ptp4l401ktimersoftd/310:33:353
21872994035,3cyclictest41-21ksoftirqd/310:00:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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