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2026-02-16 - 10:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Feb 16, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
113042214182,21sleep10-21swapper/119:05:081
132112205171,23sleep30-21swapper/319:07:033
132102202170,21sleep20-21swapper/219:07:012
132082201171,20sleep00-21swapper/019:06:580
13905995724,4cyclictest41-21ksoftirqd/319:15:153
1390099567,4cyclictest9-21ksoftirqd/021:20:010
13905995424,6cyclictest41-21ksoftirqd/300:35:013
139391530,1ptp4l401ktimersoftd/323:18:293
13905995321,4cyclictest41-21ksoftirqd/319:20:263
13905995223,4cyclictest41-21ksoftirqd/322:25:003
13905995221,4cyclictest41-21ksoftirqd/323:50:273
13905995221,4cyclictest41-21ksoftirqd/321:45:273
13900995222,9cyclictest9-21ksoftirqd/022:25:200
13905995118,4cyclictest41-21ksoftirqd/319:50:173
13905995021,7cyclictest41-21ksoftirqd/321:25:263
13905995016,3cyclictest41-21ksoftirqd/320:45:193
13905995015,7cyclictest41-21ksoftirqd/320:20:003
1390599501,2cyclictest121rcu_preempt21:00:233
13905994920,3cyclictest41-21ksoftirqd/320:00:003
13905994919,3cyclictest41-21ksoftirqd/319:35:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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