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2026-01-15 - 16:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jan 15, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
321692207173,23sleep20-21swapper/207:08:062
139491205171,23phc2sys0-21swapper/307:06:073
321772203170,22sleep00-21swapper/007:08:120
321682198165,21sleep10-21swapper/107:08:051
198532750,2sleep00-21swapper/007:50:150
13042740,2sleep10-21swapper/108:20:001
79802640,2sleep20-21swapper/208:30:252
219772640,2sleep10-21swapper/107:55:141
32618996330,9cyclictest33-21ksoftirqd/209:05:012
32619996211,17cyclictest22537-21timedrift11:15:243
32619996211,17cyclictest22537-21timedrift11:15:243
32618996230,4cyclictest33-21ksoftirqd/208:45:002
3261799625,18cyclictest20830-21awk11:15:001
32618995928,4cyclictest33-21ksoftirqd/207:15:212
32618995928,4cyclictest33-21ksoftirqd/207:15:212
32618995927,3cyclictest33-21ksoftirqd/207:25:142
32618995923,6cyclictest33-21ksoftirqd/212:30:232
3261999587,19cyclictest325112chrt11:37:163
32618995830,7cyclictest33-21ksoftirqd/212:15:002
32618995828,7cyclictest33-21ksoftirqd/211:30:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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