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2026-05-16 - 19:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat May 16, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491204170,22phc2sys0-21swapper/307:06:243
189812202168,22sleep10-21swapper/107:08:441
188982202169,22sleep00-21swapper/007:07:370
189272199167,21sleep20-21swapper/207:07:592
3255921590,2sleep00-21swapper/011:00:000
275472680,19sleep1241ktimersoftd/107:25:191
139391680,1ptp4l401ktimersoftd/310:21:293
139391590,1ptp4l401ktimersoftd/310:45:263
139391560,1ptp4l401ktimersoftd/311:22:153
139391520,1ptp4l401ktimersoftd/308:40:253
19384995043,4cyclictest10745-21grep12:29:593
19383994830,16cyclictest33-21ksoftirqd/208:25:002
19384994412,6cyclictest41-21ksoftirqd/312:00:173
1938499435,8cyclictest41-21ksoftirqd/309:25:003
19384994332,5cyclictest41-21ksoftirqd/310:05:003
139391430,1ptp4l401ktimersoftd/307:59:463
139391430,0ptp4l401ktimersoftd/310:09:553
139391430,0ptp4l401ktimersoftd/308:00:363
19381994237,3cyclictest31079-21cron07:35:010
1938199421,38cyclictest14780-21grep09:15:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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