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2026-02-13 - 21:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Feb 13, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
125542201168,22sleep00-21swapper/007:08:240
123752201168,21sleep30-21swapper/307:06:063
124582198164,23sleep10-21swapper/107:07:091
123342198165,22sleep20-21swapper/207:05:332
681821540,7sleep21297899cyclictest09:10:212
1297799670,30cyclictest972-21df11:15:131
139391640,1ptp4l401ktimersoftd/310:40:183
12978996030,4cyclictest33-21ksoftirqd/207:35:242
297902590,5sleep09-21ksoftirqd/011:05:240
297902590,5sleep09-21ksoftirqd/011:05:240
139391550,1ptp4l401ktimersoftd/307:25:373
139391530,1ptp4l401ktimersoftd/311:50:153
139391520,1ptp4l12195-21ls09:20:253
1297799512,46cyclictest12839-21wc09:25:011
1297899494,7cyclictest23361-21sed07:30:152
282552480,1sleep10-21swapper/112:10:231
1297899487,5cyclictest33-21ksoftirqd/211:30:132
12978994819,3cyclictest33-21ksoftirqd/209:50:202
12978994817,3cyclictest33-21ksoftirqd/211:44:182
139391470,1ptp4l401ktimersoftd/311:41:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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