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2026-01-13 - 23:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jan 13, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491208173,23phc2sys0-21swapper/307:08:203
177782203170,22sleep10-21swapper/107:07:541
177082203169,23sleep00-21swapper/007:07:010
176272200166,23sleep20-21swapper/207:05:582
1544821400,2sleep10-21swapper/108:15:091
215512610,7sleep11824099cyclictest11:50:261
139391550,1ptp4l401ktimersoftd/308:12:353
18240994740,4cyclictest13440-21basename10:30:001
18241994540,3cyclictest22004-21latency_hist11:55:012
18239994312,7cyclictest9-21ksoftirqd/008:35:190
139391430,1ptp4l401ktimersoftd/309:31:293
18239994236,3cyclictest9-21ksoftirqd/011:05:010
139391410,1ptp4l401ktimersoftd/311:20:153
139391410,0ptp4l401ktimersoftd/311:43:433
18241994035,3cyclictest28845-21cron09:54:592
18241994035,2cyclictest33-21ksoftirqd/208:40:002
139391400,0ptp4l401ktimersoftd/312:03:413
18241993934,3cyclictest33-21ksoftirqd/211:20:192
18239993935,2cyclictest9-21ksoftirqd/012:20:000
18239993933,3cyclictest9-21ksoftirqd/007:25:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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