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2026-04-16 - 14:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Apr 16, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491229164,22phc2sys0-21swapper/319:06:493
168072205172,22sleep20-21swapper/219:05:502
168112201168,22sleep10-21swapper/119:05:531
168052201168,22sleep00-21swapper/019:05:480
171362162125,13sleep30-21swapper/319:10:003
57898690,2rtkit-daemon577-21rtkit-daemon22:10:261
139391560,1ptp4l401ktimersoftd/320:05:533
52662520,2sleep0111rcuc/000:20:180
139391510,1ptp4l391rcuc/319:53:453
223622480,1sleep30-21swapper/323:50:123
17430994537,5cyclictest12170-21dump-pmu-power21:15:011
139391440,1ptp4l401ktimersoftd/321:38:043
139391440,0ptp4l401ktimersoftd/320:38:513
17429994135,3cyclictest9-21ksoftirqd/023:45:000
1742999410,38cyclictest15902-21cron22:30:000
139391410,1ptp4l401ktimersoftd/321:56:473
1742999401,37cyclictest11027-21cron20:05:000
139391400,0ptp4l401ktimersoftd/320:03:453
17431993932,5cyclictest33-21ksoftirqd/220:30:012
17430993932,5cyclictest25-21ksoftirqd/121:27:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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