The Zephyr reference system of the OSADL QA Farm undergoes repeated periods of load conditions and latency measurements with Zephyr's zyclictest module. The two measurement periods to determine the system's worst case latency start at 7:10 a.m. and 7:10 p.m. and have a duration of five hours and 33 minutes (100.000.000 cycles at an interval of 200 µs). The zyclictest program itself creates a relatively high interrupt load but no other relevant load that may interfere with the system. Therefor additional background load is generated by the continuous reading of a sensor. Currently all tests are run on a Olimex STM32-E407 board with Zephyr 4.3.0 and zyclictest from the related pull request (Zephyr was built with this prj.conf. More information on building Zephyr can be found here). The results of the latest test run are printed below:

• STM32F407ZG: 1 core Arm Cortex-M4 @ 168 MHz