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2026-03-06 - 02:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Thu Mar 05, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2148321760,5sleep133165599cyclictest21:47:535
3235321380,1sleep43164299cyclictest21:59:1410
1885621350,5sleep123165499cyclictest21:54:174
1015421210,2sleep120-21swapper/1223:36:434
309022119102,13sleep00-21swapper/019:07:300
310102116103,9sleep120-21swapper/1219:09:034
310862113102,7sleep130-21swapper/1319:10:085
1901921120,1sleep10-21swapper/122:44:071
31189211091,14sleep90-21swapper/919:10:5215
31087210992,13sleep140-21swapper/1419:10:096
30907210993,12sleep40-21swapper/419:07:3410
2103021080,1sleep70-21swapper/721:34:5613
1234121070,6sleep63164799cyclictest00:36:4812
1796421060,4sleep03163799cyclictest21:21:430
2395021050,2sleep12114-21ksoftirqd/1200:17:384
30929210290,8sleep50-21swapper/519:07:5111
865121000,3sleep1241ktimersoftd/100:03:011
71872970,0sleep110-21swapper/1119:56:363
71872970,0sleep110-21swapper/1119:56:363
301342960,2sleep1230136-21sshd00:22:114
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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