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2026-05-03 - 15:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Sun May 03, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491227165,50phc2sys0-21swapper/307:09:573
238602204170,22sleep10-21swapper/107:06:151
240292203170,22sleep00-21swapper/007:08:280
239482203169,23sleep20-21swapper/207:07:262
987221700,6sleep32444999cyclictest12:15:223
2415528363,11sleep00-21swapper/007:10:010
24448996734,5cyclictest33-21ksoftirqd/210:50:002
24448996733,5cyclictest33-21ksoftirqd/211:19:592
24448996531,7cyclictest33-21ksoftirqd/212:40:002
24448996529,7cyclictest33-21ksoftirqd/212:05:122
24448996425,6cyclictest33-21ksoftirqd/207:45:182
24448996330,5cyclictest33-21ksoftirqd/209:35:162
2444699630,22cyclictest17092-21cut12:30:230
2444699630,22cyclictest17092-21cut12:30:230
2444699630,21cyclictest8682-21date07:45:000
2444699630,21cyclictest18382-21date10:20:010
24448996231,6cyclictest33-21ksoftirqd/209:45:132
24448996231,5cyclictest33-21ksoftirqd/208:20:152
24448996229,5cyclictest33-21ksoftirqd/207:25:142
2444699620,22cyclictest20759-21date10:25:020
55452610,6sleep02444699cyclictest09:50:260
24448996129,4cyclictest33-21ksoftirqd/209:10:152
24448996129,4cyclictest33-21ksoftirqd/208:45:172
24448996128,5cyclictest33-21ksoftirqd/207:15:202
24448996127,5cyclictest33-21ksoftirqd/208:20:002
24448996126,4cyclictest33-21ksoftirqd/211:05:232
2444699610,21cyclictest20499-21date12:40:010
2444699610,21cyclictest17175-21date09:10:010
24448996028,5cyclictest33-21ksoftirqd/212:30:152
24448996028,5cyclictest33-21ksoftirqd/212:30:152
24448996028,5cyclictest33-21ksoftirqd/210:40:242
24448996027,5cyclictest33-21ksoftirqd/212:25:262
24448996027,5cyclictest33-21ksoftirqd/210:15:242
24448996026,6cyclictest33-21ksoftirqd/211:10:232
24448996026,4cyclictest33-21ksoftirqd/211:55:262
24448996026,3cyclictest33-21ksoftirqd/208:30:182
24448996025,4cyclictest33-21ksoftirqd/209:00:252
24448996024,6cyclictest33-21ksoftirqd/208:10:172
2444699600,20cyclictest3775-21cat12:05:010
24448995927,6cyclictest33-21ksoftirqd/210:10:192
24448995927,5cyclictest33-21ksoftirqd/209:50:252
24448995926,7cyclictest33-21ksoftirqd/207:30:202
24448995926,7cyclictest33-21ksoftirqd/207:30:202
24448995926,5cyclictest33-21ksoftirqd/210:50:232
24448995926,5cyclictest33-21ksoftirqd/208:40:182
24448995925,5cyclictest33-21ksoftirqd/211:25:252
24448995830,7cyclictest33-21ksoftirqd/208:05:012
24448995826,6cyclictest33-21ksoftirqd/209:15:132
24448995825,7cyclictest33-21ksoftirqd/208:55:162
24448995825,6cyclictest33-21ksoftirqd/211:30:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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