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2026-03-02 - 16:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Mon Mar 02, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491223160,51phc2sys0-21swapper/307:05:103
302402203170,22sleep20-21swapper/207:09:542
302342201169,22sleep10-21swapper/107:09:501
300882196163,22sleep00-21swapper/007:07:560
590621360,6sleep13054599cyclictest11:55:191
17862780,1sleep20-21swapper/207:15:222
139391430,0ptp4l401ktimersoftd/310:31:473
139391430,0ptp4l401ktimersoftd/307:29:383
30546994223,17cyclictest33-21ksoftirqd/209:30:002
30546994223,16cyclictest33-21ksoftirqd/208:05:002
139391420,0ptp4l401ktimersoftd/311:25:163
139391420,0ptp4l401ktimersoftd/309:34:583
139391420,0ptp4l401ktimersoftd/309:16:213
139391420,0ptp4l401ktimersoftd/308:27:553
139391410,1ptp4l401ktimersoftd/311:06:233
30545994035,3cyclictest25-21ksoftirqd/109:35:011
3054599394,3cyclictest25-21ksoftirqd/108:30:191
30545993934,3cyclictest25-21ksoftirqd/109:10:001
30547993833,3cyclictest24127-21cron08:05:013
30546993825,11cyclictest33-21ksoftirqd/211:50:002
30545993834,3cyclictest25-21ksoftirqd/108:44:591
30545993834,2cyclictest25-21ksoftirqd/108:00:011
30545993833,3cyclictest25-21ksoftirqd/108:05:011
30546993732,3cyclictest33-21ksoftirqd/212:40:002
30546993731,4cyclictest33-21ksoftirqd/211:25:322
30546993731,3cyclictest33-21ksoftirqd/208:19:592
30546993719,16cyclictest33-21ksoftirqd/211:35:012
3054599374,3cyclictest121rcu_preempt09:10:171
30545993734,2cyclictest25-21ksoftirqd/109:20:011
30545993734,2cyclictest25-21ksoftirqd/109:00:001
30545993732,3cyclictest25-21ksoftirqd/110:45:231
30545993732,3cyclictest25-21ksoftirqd/110:00:001
30545993732,3cyclictest25-21ksoftirqd/108:20:001
30545993732,3cyclictest25-21ksoftirqd/108:15:001
30545993732,3cyclictest25-21ksoftirqd/107:20:181
30545993731,3cyclictest25-21ksoftirqd/111:45:001
139391370,0ptp4l401ktimersoftd/311:35:253
30547993631,3cyclictest41-21ksoftirqd/312:40:003
30547993630,4cyclictest41-21ksoftirqd/312:16:033
30547993630,4cyclictest41-21ksoftirqd/310:17:093
30547993630,4cyclictest41-21ksoftirqd/309:27:353
30546993632,2cyclictest33-21ksoftirqd/211:40:002
30546993632,2cyclictest33-21ksoftirqd/208:30:012
30546993631,3cyclictest33-21ksoftirqd/211:10:002
30546993631,3cyclictest33-21ksoftirqd/210:55:202
30546993631,3cyclictest33-21ksoftirqd/210:25:122
30546993631,3cyclictest33-21ksoftirqd/208:50:182
30546993631,3cyclictest33-21ksoftirqd/208:50:182
30546993631,3cyclictest33-21ksoftirqd/207:40:202
30546993629,4cyclictest33-21ksoftirqd/207:39:302
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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