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2026-03-08 - 08:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Sun Mar 08, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
203712234168,23sleep30-21swapper/319:07:173
204532230167,21sleep10-21swapper/119:08:191
202412203170,22sleep00-21swapper/019:05:410
202432201168,22sleep20-21swapper/219:05:432
1597921810,6sleep22087799cyclictest22:20:232
2277321700,6sleep32087899cyclictest22:35:203
427321500,4sleep20-21swapper/220:50:132
2503921400,6sleep32087899cyclictest19:15:263
1394918162,10phc2sys0-21swapper/319:10:003
140582590,2sleep2321ktimersoftd/223:25:142
322132560,6sleep22087799cyclictest22:55:172
304142560,1sleep10-21swapper/119:30:011
82632540,2sleep20-21swapper/222:05:192
140982540,4sleep32087899cyclictest20:00:283
14312530,7sleep02087599cyclictest23:00:000
52682520,1sleep30-21swapper/323:05:203
2087799522,47cyclictest21539-21dump-pmu-power22:34:592
139391450,0ptp4l401ktimersoftd/322:52:463
139391420,0ptp4l401ktimersoftd/323:55:083
139391420,0ptp4l401ktimersoftd/322:49:133
139391410,0ptp4l401ktimersoftd/322:56:193
20878994029,9cyclictest41-21ksoftirqd/323:20:153
139391400,1ptp4l401ktimersoftd/321:01:103
139391400,1ptp4l401ktimersoftd/321:01:103
20877993934,3cyclictest33-21ksoftirqd/219:20:002
20876993934,3cyclictest25-21ksoftirqd/120:35:001
20876993933,4cyclictest25-21ksoftirqd/122:39:191
20876993932,5cyclictest25-21ksoftirqd/122:35:001
139391390,1ptp4l401ktimersoftd/319:22:053
139391390,0ptp4l401ktimersoftd/320:40:153
20877993834,2cyclictest33-21ksoftirqd/220:40:002
20876993832,3cyclictest25-21ksoftirqd/123:00:001
20876993832,3cyclictest25-21ksoftirqd/119:40:001
20878993732,3cyclictest12020-21cron22:15:013
20878993731,3cyclictest41-21ksoftirqd/323:20:013
2087799373,3cyclictest131rcu_sched21:00:002
20876993732,3cyclictest25-21ksoftirqd/123:30:281
20876993732,3cyclictest25-21ksoftirqd/121:25:171
20876993732,3cyclictest25-21ksoftirqd/100:20:011
20876993731,4cyclictest25-21ksoftirqd/122:27:561
20876993731,4cyclictest25-21ksoftirqd/100:09:001
20875993731,4cyclictest9-21ksoftirqd/022:50:010
20875993714,4cyclictest10515-21acpi00:25:110
20878993631,3cyclictest41-21ksoftirqd/320:25:003
20878993630,3cyclictest41-21ksoftirqd/322:35:003
20878993630,3cyclictest41-21ksoftirqd/321:15:003
20878993629,5cyclictest41-21ksoftirqd/320:51:143
20878993620,3cyclictest41-21ksoftirqd/321:45:123
20877993632,3cyclictest33-21ksoftirqd/222:40:002
20877993631,3cyclictest33-21ksoftirqd/222:00:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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