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2026-02-20 - 15:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Fri Feb 20, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
324572205172,22sleep20-21swapper/207:07:422
139491204171,22phc2sys0-21swapper/307:07:453
325992201168,22sleep10-21swapper/107:09:251
324602201167,22sleep00-21swapper/007:07:440
15842600,2sleep20-21swapper/209:25:202
118902600,7sleep148299cyclictest10:55:171
294202570,2sleep20-21swapper/210:25:012
296022540,4sleep229606-21cpuspeed_turbos08:10:142
139391530,1ptp4l401ktimersoftd/309:30:003
249732510,2sleep10-21swapper/108:00:151
48199501,46cyclictest5293-21idleruntime-cro11:50:000
60172490,1sleep36019-21df11:50:153
134391490,2getstats0-21swapper/308:45:263
41572480,2sleep10-21swapper/110:40:001
48199450,4cyclictest20667-21runrttasks11:14:160
139391450,1ptp4l401ktimersoftd/312:32:023
484994433,9cyclictest41-21ksoftirqd/307:20:273
484994432,9cyclictest41-21ksoftirqd/309:25:273
139391440,0ptp4l401ktimersoftd/311:38:363
484994337,4cyclictest17310-21sh07:45:003
139391430,2ptp4l0-21swapper/309:55:223
139391430,0ptp4l401ktimersoftd/312:38:173
139391420,0ptp4l401ktimersoftd/309:10:303
139391420,0ptp4l401ktimersoftd/307:50:163
484993934,3cyclictest41-21ksoftirqd/307:29:593
484993934,3cyclictest41-21ksoftirqd/307:15:003
484993933,4cyclictest41-21ksoftirqd/310:24:143
139391390,1ptp4l391rcuc/311:40:183
134391390,2getstats0-21swapper/308:35:263
484993833,3cyclictest41-21ksoftirqd/310:20:013
484993833,3cyclictest41-21ksoftirqd/308:20:013
484993833,2cyclictest41-21ksoftirqd/309:20:013
484993832,3cyclictest41-21ksoftirqd/307:40:003
483993832,3cyclictest33-21ksoftirqd/210:05:002
48399381,34cyclictest2766-21sh07:15:002
48199386,18cyclictest23624-21grep07:55:230
134491380,2getstats0-21swapper/310:55:163
484993733,2cyclictest41-21ksoftirqd/308:55:013
484993732,2cyclictest41-21ksoftirqd/308:55:243
484993731,3cyclictest41-21ksoftirqd/307:50:003
483993731,4cyclictest33-21ksoftirqd/207:19:072
48399371,3cyclictest121rcu_preempt10:35:212
482993731,4cyclictest25-21ksoftirqd/109:58:361
482993730,5cyclictest25-21ksoftirqd/111:22:041
484993632,2cyclictest41-21ksoftirqd/312:05:143
484993632,2cyclictest41-21ksoftirqd/310:50:203
484993632,2cyclictest41-21ksoftirqd/309:10:003
484993632,2cyclictest41-21ksoftirqd/309:10:003
484993630,4cyclictest41-21ksoftirqd/308:25:403
484993630,3cyclictest41-21ksoftirqd/312:25:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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