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2026-03-11 - 12:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Wed Mar 11, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35432422267194,59sleep00-21swapper/019:05:590
35432552240198,28sleep10-21swapper/119:06:091
37382472620,1sleep10-21swapper/100:33:471
37355072540,9sleep013-21ksoftirqd/000:30:250
37108122430,1sleep10-21swapper/123:54:541
35459442430,3sleep13543730-21cyclictest19:15:021
179699430,3rtkit-daemon0-21swapper/123:32:041
354373499427,2cyclictest141rcu_preempt00:30:020
354373899418,3cyclictest141rcu_preempt00:00:001
354373499418,2cyclictest141rcu_preempt00:05:000
3543734994111,6cyclictest13-21ksoftirqd/023:25:000
36806152400,4sleep013-21ksoftirqd/023:10:370
3543738994015,4cyclictest26-21ksoftirqd/100:20:001
3543738994012,5cyclictest26-21ksoftirqd/100:10:001
354373499406,2cyclictest141rcu_preempt00:00:020
3543738993912,5cyclictest26-21ksoftirqd/122:10:011
3543734993911,5cyclictest13-21ksoftirqd/021:20:000
3543738993812,7cyclictest26-21ksoftirqd/123:40:011
3543738993812,5cyclictest26-21ksoftirqd/123:00:001
3543738993811,5cyclictest26-21ksoftirqd/123:05:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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