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2025-10-24 - 03:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Thu Oct 23, 2025 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25341942265187,27sleep00-21swapper/007:09:270
25338762246205,27sleep10-21swapper/107:06:021
125899600,4rtkit-daemon1257-21rtkit-daemon12:12:331
2534370995512,12cyclictest2649179-21latency_hist10:35:011
2534370995413,14cyclictest2667958-21sh11:00:001
2534370995413,12cyclictest2553085-21ls07:55:001
125899540,4rtkit-daemon1257-21rtkit-daemon12:29:560
2534370995312,12cyclictest2698761-21sh11:40:001
125899530,4rtkit-daemon1257-21rtkit-daemon12:04:471
2534370995218,11cyclictest2626377-21sshd10:05:011
2534370995213,12cyclictest2707207-21irqstats11:50:191
2534370995212,11cyclictest2604303-21tr09:35:231
125899520,4rtkit-daemon1257-21rtkit-daemon10:00:361
2534370995119,13cyclictest2641706-21ssh10:25:111
2534370995116,12cyclictest2588044-21cut09:15:231
2534370995113,10cyclictest2652768-21munin-run10:40:001
2534370995111,11cyclictest2661851-21switchtime10:50:251
2534370995111,11cyclictest2661851-21switchtime10:50:251
2534370995019,11cyclictest2582934-21diskmemload09:20:071
2534370995013,12cyclictest2729558-21/usr/sbin/munin12:20:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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