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2025-12-04 - 12:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Thu Dec 04, 2025 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15878562258218,26sleep00-21swapper/019:05:580
15864792245202,28sleep10-21swapper/119:05:071
16450252520,1chrt1644465-21/usr/sbin/munin21:20:200
158833199438,8cyclictest13-21ksoftirqd/022:15:010
125899430,3rtkit-daemon1257-21rtkit-daemon00:17:500
158833399417,7cyclictest26-21ksoftirqd/121:50:251
1588333994023,15cyclictest26-21ksoftirqd/123:05:001
158833399397,9cyclictest26-21ksoftirqd/122:45:141
158833399391,10cyclictest26-21ksoftirqd/100:20:011
158833399380,9cyclictest1769350-21latency_hist00:15:011
158833399380,8cyclictest26-21ksoftirqd/119:18:461
1588331993813,8cyclictest13-21ksoftirqd/019:25:050
125899380,5rtkit-daemon1589094-21memory19:10:191
125899380,3rtkit-daemon0-21swapper/121:55:131
125899380,3rtkit-daemon0-21swapper/121:55:131
158833399372,5cyclictest26-21ksoftirqd/100:25:011
158833399372,4cyclictest26-21ksoftirqd/100:35:001
158833399370,9cyclictest1762243-21sshd00:03:261
158833399370,8cyclictest1786800-21sh00:40:001
125899370,4rtkit-daemon1643047-21ssh21:17:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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