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2026-09-16 - 02:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Wed Sep 16, 2026 00:46:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
129303299350349,1cyclictest1361559-21kworker/u40:3+events_unbound23:43:5213
129303299344344,0cyclictest1472196-21kworker/u40:6+events_unbound23:08:0513
129304299342342,0cyclictest1395563-21kworker/u40:5+events_unbound22:15:3316
129302599342341,1cyclictest1430264-21kworker/1:2+events23:55:051
129302599331330,1cyclictest1430264-21kworker/1:2+events22:15:331
129304299325325,0cyclictest98350irq/154-snd_hda_intel:card122:10:5516
129304299324324,0cyclictest98350irq/154-snd_hda_intel:card122:21:1916
129302599313313,0cyclictest144850irq/131-eno123:43:521
129302599308308,0cyclictest144850irq/131-eno122:45:431
129302599308308,0cyclictest144850irq/131-eno120:32:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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