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2025-11-23 - 19:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Sun Nov 23, 2025 00:45:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
342681199401399,1cyclictest0-21swapper/420:06:5110
342681199399399,0cyclictest0-21swapper/421:02:1610
342683999391390,1cyclictest107156-21StreamT~5
342683999391390,1cyclictest107156-21StreamT~5
342679799384380,3cyclictest0-21swapper/021:57:510
342683799372368,3cyclictest3616566-21kthreadcore19:55:264
342684799362360,1cyclictest0-21swapper/1521:57:517
342682999352351,1cyclictest29450irq/128-xhci_hcd19:43:022
342682999347346,1cyclictest29450irq/128-xhci_hcd19:25:492
342681199342341,1cyclictest323654-21Xorg19:55:2510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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