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2026-05-03 - 13:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Sun May 03, 2026 00:46:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
193817399412412,0cyclictest1921058-21kworker/u40:1+events_unbound19:52:271
193818099378378,0cyclictest2114845-21kworker/u40:0+events_unbound22:51:1913
193819399297297,0cyclictest99250irq/154-snd_hda_intel:card122:42:1116
193819799294288,5cyclictest13400-21Renderer19:10:0117
193820399288283,5cyclictest13400-21Renderer21:27:4819
193819399288283,5cyclictest13400-21Renderer22:28:5116
193820399287283,3cyclictest13400-21Renderer21:45:4519
193820199287283,3cyclictest13400-21Renderer22:04:1618
193819799287283,4cyclictest13400-21Renderer23:06:0317
193819799287283,4cyclictest13400-21Renderer20:13:5617
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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