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2025-12-07 - 15:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Sun Dec 07, 2025 00:46:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21977829944619,28cyclictest0-21swapper/519:50:1511
21977779944415,27cyclictest651rcuc/420:44:2010
2197806994320,29cyclictest2821023-21/usr/sbin/munin21:40:384
21977829943210,27cyclictest2011-21mdadm21:19:2011
2197782994320,26cyclictest0-21swapper/520:44:3811
2197807994305,27cyclictest0-21swapper/1320:56:465
2197794994305,27cyclictest323624-21systemd19:51:4315
2197794994290,428cyclictest323674-21dbus-daemon21:37:5515
219778799429427,2cyclictest3149201-21kworker/u64:4+events_unbound23:54:2813
219776499427422,5cyclictest2600688-21kworker/u64:6+events_unbound21:34:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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