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2025-08-30 - 01:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Sat Aug 30, 2025 00:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6261239945120,28cyclictest0-21swapper/522:58:5911
6261219945121,28cyclictest2802765-21Isolated15:07:449
6261229945019,28cyclictest3461668-21Socket15:07:4410
6261229945019,28cyclictest3461668-21Socket15:07:4410
6261239944718,27cyclictest0-21swapper/500:00:5211
626123994428,28cyclictest0-21swapper/522:38:4511
626123994418,431cyclictest0-21swapper/500:12:4511
626133994384,27cyclictest0-21swapper/1120:26:593
626127994375,27cyclictest0-21swapper/923:40:2215
626127994364,426cyclictest0-21swapper/921:41:5115
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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