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2026-08-01 - 13:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Sat Aug 01, 2026 00:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
334948999426425,1cyclictest3387519-21kworker/u40:2+events_unbound20:16:1119
334946399425424,1cyclictest3449382-21kworker/u40:4+events_unbound21:40:121
334948999423422,1cyclictest3290107-21kworker/u40:6+events_unbound19:25:3419
334948999421420,1cyclictest3415508-21kworker/u40:2+events_unbound22:00:2519
334947999413413,0cyclictest3444892-21kworker/u40:3+events_unbound21:15:1316
334947999412412,0cyclictest98350irq/154-snd_hda_intel:card120:06:2616
334947999409408,1cyclictest3368607-21kworker/u40:3+events_unbound19:34:4316
334945899404403,1cyclictest3395442-21kworker/0:0+pm20:16:110
334945899403402,1cyclictest3382497-21kworker/0:1+pm19:47:310
334945899402402,0cyclictest3395442-21kworker/0:0+pm22:01:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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