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2025-12-09 - 05:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Tue Dec 09, 2025 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3415780994340,433cyclictest0-21swapper/1500:13:417
34157809941822,395cyclictest0-21swapper/1500:32:597
34157809941822,395cyclictest0-21swapper/1500:32:597
34157419941813,401cyclictest0-21swapper/400:14:3310
34157579941710,403cyclictest0-21swapper/800:27:2214
34157579941710,403cyclictest0-21swapper/800:27:2214
34157419941612,402cyclictest0-21swapper/400:18:2110
34157419941410,401cyclictest0-21swapper/400:38:5910
341573599409409,0cyclictest0-21swapper/200:25:248
341573599409409,0cyclictest0-21swapper/200:25:248
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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