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2025-12-23 - 03:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Tue Dec 23, 2025 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24412959947115,55cyclictest1957723-21Isolated12:10:194
24412929947110,460cyclictest139-21ksoftirqd/1119:57:153
24412559946910,56cyclictest31616-21Isolated12:10:190
24412859945724,28cyclictest0-21swapper/923:20:2215
24412719945623,28cyclictest0-21swapper/522:44:2111
24412719945622,28cyclictest0-21swapper/520:26:2611
24412719945523,27cyclictest3617452-21Timer20:55:4911
24412859945322,27cyclictest0-21swapper/920:49:2315
24412589945220,27cyclictest203150irq/139-enp2s0-rx-023:56:211
24412859945118,28cyclictest3011244-21kthreadcore21:25:2415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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