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2025-12-28 - 08:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot7.osadl.org (updated Sun Dec 28, 2025 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12715749948921,56cyclictest1815267-21StreamT~0
1271583994719,29cyclictest2000733-21dd22:03:459
1271589994698,27cyclictest0-21swapper/521:11:2911
1271589994679,55cyclictest3342169-21Isolated12:10:1911
12715749946227,27cyclictest0-21swapper/023:43:520
12715749946023,28cyclictest0-21swapper/022:35:440
12715839945522,27cyclictest0-21swapper/320:33:209
12716009945321,28cyclictest0-21swapper/1023:08:172
12715989945120,27cyclictest0-21swapper/920:06:5915
12715839945123,27cyclictest0-21swapper/319:57:299
12715839944715,27cyclictest0-21swapper/323:30:339
12715939944621,423cyclictest0-21swapper/700:34:5413
12716009944312,27cyclictest0-21swapper/1023:51:592
1271574994430,29cyclictest441173-21Timer21:38:210
1271606994407,28cyclictest3844424-21Isolated12:10:194
1271580994396,27cyclictest0-21swapper/223:28:478
1271610994355,430cyclictest0-21swapper/1422:02:476
1271607994340,28cyclictest0-21swapper/1320:38:375
1271589994340,28cyclictest0-21swapper/519:53:2711
12716009943326,406cyclictest1815267-21StreamT~2
12716009943326,406cyclictest1815267-21StreamT~2
12715989943312,420cyclictest0-21swapper/923:00:3715
1271583994330,31cyclictest0-21swapper/323:55:509
1271580994320,27cyclictest0-21swapper/221:42:598
12716109943115,416cyclictest0-21swapper/1423:10:566
12716109943115,416cyclictest0-21swapper/1423:10:566
12716109943024,405cyclictest0-21swapper/1420:13:446
12716109943023,406cyclictest0-21swapper/1421:48:216
1271610994300,430cyclictest0-21swapper/1423:05:346
12716109942924,405cyclictest0-21swapper/1422:42:226
12716109942922,406cyclictest0-21swapper/1423:52:456
12716109942822,405cyclictest0-21swapper/1420:24:306
12716069942822,405cyclictest85950irq/168-nvme1q520:04:144
12715899942823,405cyclictest0-21swapper/519:40:4411
12715839942822,404cyclictest0-21swapper/319:47:489
12715839942821,402cyclictest0-21swapper/323:45:259
12715809942818,409cyclictest0-21swapper/222:36:218
12716109942722,405cyclictest0-21swapper/1420:47:436
12716109942721,405cyclictest0-21swapper/1419:41:456
12715839942724,402cyclictest0-21swapper/300:13:139
12715749942719,401cyclictest0-21swapper/019:43:230
12716039942617,405cyclictest0-21swapper/1123:00:133
127159099426425,1cyclictest871ktimers/620:01:0712
12715839942617,408cyclictest0-21swapper/320:16:229
12715839942521,401cyclictest0-21swapper/320:07:589
1271613994240,424cyclictest0-21swapper/1521:43:217
1271613994240,421cyclictest87250irq/171-nvme1q820:52:237
127157499424421,3cyclictest0-21swapper/021:45:440
127160399423421,2cyclictest1835746-21kworker/11:2+pm22:03:353
127159099423421,2cyclictest1432909-21kworker/6:2+pm00:28:4912
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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