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2025-10-28 - 00:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot8.osadl.org (updated Mon Oct 27, 2025 12:45:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7137319944715,28cyclictest0-21swapper/511:28:5811
7137399944520,27cyclictest0-21swapper/1311:07:585
7137319944541,403cyclictest2259468-21Socket13:59:1211
7137309944236,403cyclictest0-21swapper/409:17:4010
7137419944116,28cyclictest0-21swapper/1412:26:596
7137419944116,28cyclictest0-21swapper/1412:26:586
71373799431431,0cyclictest0-21swapper/1110:50:193
7137319943121,409cyclictest2167422-21IPC11
713742994303,426cyclictest0-21swapper/1512:33:517
713742994303,426cyclictest0-21swapper/1512:33:517
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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