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2025-11-18 - 02:15
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Note that this system runs a non-RT kernel.
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot8.osadl.org (updated Sat Nov 15, 2025 12:45:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25548729910700,1069cyclictest2793968-21modprobe11:11:1115
2554875997060,703cyclictest2719298-21meminfo09:55:234
2554875994900,484cyclictest2877896-21meminfo12:35:264
2554862994860,485cyclictest2763116-21meminfo10:40:241
2554861994740,472cyclictest2868220-21meminfo12:25:220
2554861994610,459cyclictest2842687-21meminfo12:00:230
2554866993500,348cyclictest2772682-21meminfo10:50:2311
2554866993500,348cyclictest2772682-21meminfo10:50:2211
2554875993400,338cyclictest2763117-21meminfo10:40:244
2554866993100,308cyclictest2758297-21meminfo10:35:2311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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