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2026-03-18 - 08:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot8.osadl.org (updated Sat Mar 14, 2026 12:45:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
336782699443439,3cyclictest0-21swapper/1509:20:567
336782699429428,0cyclictest0-21swapper/1508:39:327
336782499429425,3cyclictest3372807-21kworker/u64:6+events_unbound07:31:105
336782499429425,3cyclictest3372807-21kworker/u64:6+events_unbound07:31:105
336782499429422,3cyclictest3383367-21kworker/u64:0+events_unbound08:44:085
336782699428427,0cyclictest0-21swapper/1507:55:437
336782699428425,1cyclictest0-21swapper/1509:30:567
3367825994280,427cyclictest0-21swapper/1409:15:126
336782499428425,2cyclictest3453096-21kworker/u64:2+events_unbound09:01:495
336782499428425,2cyclictest3412923-21kworker/u64:1+events_unbound08:09:125
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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