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2025-09-18 - 13:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot8.osadl.org (updated Thu Sep 18, 2025 12:45:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
168000299433433,0cyclictest0-21swapper/1510:59:267
167998999423420,2cyclictest1815623-21kworker/u64:1+events_unbound10:11:429
167998899422422,0cyclictest0-21swapper/211:14:448
167999799421417,3cyclictest1773432-21kworker/u64:0+events_unbound09:22:073
167998899421418,2cyclictest52787-21kworker/u64:7+events_unbound07:35:588
167999599419416,1cyclictest56450usb-storage11:52:4215
167998999419417,1cyclictest0-21swapper/309:22:599
167998999418418,0cyclictest0-21swapper/309:57:229
167999599415414,1cyclictest0-21swapper/910:35:5915
167999599415414,1cyclictest0-21swapper/910:35:5915
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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