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2026-03-03 - 01:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot8.osadl.org (updated Mon Mar 02, 2026 12:45:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2606848995850,582cyclictest2715906-21meminfo09:00:100
2606851995550,553cyclictest2926757-21meminfo12:35:109
260684999430425,4cyclictest2803098-21kworker/u64:1+events_unbound12:14:081
260684999430425,4cyclictest2803098-21kworker/u64:1+events_unbound12:14:081
2606849994260,0cyclictest0-21swapper/111:03:581
260685099425420,4cyclictest2680323-21kworker/u64:0+events_unbound10:09:128
260684999425423,1cyclictest183150irq/155-enp1s0-rx-010:15:311
260684999425421,3cyclictest2674676-21kworker/u64:1+events_unbound08:30:171
260684999424421,2cyclictest0-21swapper/109:19:371
260684999424420,3cyclictest2857853-21kworker/u64:6+events_unbound11:51:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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