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2024-04-26 - 13:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot8.osadl.org (updated Fri Apr 26, 2024 12:46:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35453899707407,166cyclictest441908-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
12:15:040
35453899706429,144cyclictest300593-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
07:10:100
35453899685407,144cyclictest366080-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
07:35:050
35453899684407,144cyclictest589272-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
12:35:430
35453899684407,144cyclictest551882-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
10:55:230
35453899684407,144cyclictest501048-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
10:35:090
35453899684407,144cyclictest441908-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
10:40:070
35453899684407,144cyclictest408427-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
08:55:060
35453899684407,144cyclictest381651-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
09:05:220
35453899684406,144cyclictest468592-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
09:30:030
35453899683407,143cyclictest606490-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
12:10:550
35453899683407,143cyclictest589272-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
12:05:170
35453899683407,143cyclictest551882-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
11:25:080
35453899683407,143cyclictest531226-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
11:15:040
35453899683407,143cyclictest531226-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
11:15:040
35453899683407,143cyclictest478214-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
09:55:510
35453899683407,143cyclictest408427-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
08:50:550
35453899683407,143cyclictest353899-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
08:25:050
35453899683407,143cyclictest353899-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
08:25:050
35453899683407,143cyclictest301374-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
07:40:020
35453899683406,144cyclictest606490-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
12:00:020
35453899683406,144cyclictest478214-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
10:10:010
35453899683406,144cyclictest441908-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
12:20:020
35453899683406,143cyclictest353899-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
07:50:150
35453899683405,144cyclictest551882-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
11:00:310
35453899682406,143cyclictest478214-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
09:35:100
35453899682406,143cyclictest441908-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
09:50:060
35453899682406,143cyclictest408427-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
08:30:060
35453899682406,143cyclictest408427-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
08:30:050
35453899682406,143cyclictest408427-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
08:20:090
35453899682406,143cyclictest408427-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
08:20:090
35453899638407,93cyclictest501048-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
10:32:370
35453899618407,77cyclictest543372-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
10:45:080
35453899618407,77cyclictest501048-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
11:35:330
35453899617407,77cyclictest381651-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
08:35:060
35453899617406,77cyclictest478214-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
09:46:060
35453899617406,77cyclictest373297-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
07:30:380
35453899616407,76cyclictest441908-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
09:11:000
35453899616406,77cyclictest589272-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
11:46:090
35453899616406,77cyclictest551882-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
11:30:260
35453899616406,77cyclictest491127-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
10:00:590
35453899616406,77cyclictest309300-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
07:15:070
35453899616406,76cyclictest468592-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
10:15:400
35453899616406,143cyclictest551882-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
11:05:080
35453899616406,143cyclictest551882-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
11:05:080
35453899616406,143cyclictest538383-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
11:10:540
35453899616406,143cyclictest538383-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
11:10:540
35453899616406,143cyclictest501048-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
11:55:350
35453899615406,142cyclictest551882-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
11:20:270
35453899572406,94cyclictest381651-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
08:40:590
35453899570407,91cyclictest606490-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
12:26:110
35453899570407,91cyclictest353783-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
07:21:390
35453899567411,88cyclictest468592-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
10:24:360
35453899558414,76cyclictest468592-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
09:25:280
35453899555411,76cyclictest366080-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
07:27:160
35453899555410,77cyclictest433078-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
09:04:180
35453899553407,78cyclictest551882-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
11:42:280
35453899553407,78cyclictest373297-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
07:56:040
35453899552407,78cyclictest551882-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
10:50:580
35453899552407,78cyclictest381651-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
08:15:540
35453899552406,78cyclictest491127-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
10:26:200
35453899551407,77cyclictest606490-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
12:30:490
35453899551407,77cyclictest433078-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
09:15:570
35453899551407,77cyclictest381970-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
07:45:540
35453899550406,77cyclictest468592-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
09:40:430
35453899547410,69cyclictest478214-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
10:05:500
35455199498424,2cyclictest538383-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
10:53:072
35455299497423,2cyclictest381651-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
08:48:323
35455299492419,1cyclictest468592-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
09:20:363
35455299492419,1cyclictest366080-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
07:32:023
35455299491419,1cyclictest381970-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
07:44:203
35455299490417,1cyclictest309300-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
07:13:353
35455199486414,1cyclictest441908-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
09:41:022
35454199449373,2cyclictest501048-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
10:36:419
35454199443370,1cyclictest501048-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
10:19:139
35454199440368,1cyclictest606490-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
12:29:159
35454199440367,1cyclictest638493-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
12:35:589
35454199438366,1cyclictest366080-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
07:21:449
35455599429429,0cyclictest0-21swapper/1410:05:516
35454999429356,1cyclictest408427-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
09:44:2615
354555994280,427cyclictest0-21swapper/1411:46:166
354555994270,426cyclictest0-21swapper/1412:08:076
35454999427354,1cyclictest441908-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
10:39:5715
35454999426353,1cyclictest408427-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
08:57:4515
35454999425352,1cyclictest584677-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
11:45:1315
35454999425352,1cyclictest301374-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
07:18:4715
354552994240,423cyclictest0-21swapper/1110:36:413
35453899424420,3cyclictest0-21swapper/008:48:320
35453899423419,4cyclictest605976-21cat11:50:390
35455299420420,0cyclictest0-21swapper/1110:19:133
354547994200,2cyclictest0-21swapper/809:35:0914
354547994200,133cyclictest0-21swapper/812:00:0314
35453899419416,3cyclictest0-21swapper/009:20:360
35455299418418,0cyclictest0-21swapper/1112:29:163
35454699418344,2cyclictest615912-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
12:07:5813
35455299417417,0cyclictest0-21swapper/1112:35:583
35454699417343,2cyclictest501048-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
10:47:3613
35454699417343,2cyclictest381970-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
07:51:0313
35455299416416,0cyclictest0-21swapper/1107:21:443
35454399414340,2cyclictest501048-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
11:48:5611
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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