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2025-05-02 - 12:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot8.osadl.org (updated Thu May 01, 2025 12:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
347275899910,90cyclictest3620027-21meminfo09:45:214
347275599890,88cyclictest3592216-21meminfo09:15:2315
347275099870,85cyclictest3694511-21meminfo11:05:2511
347275099840,83cyclictest3480811-21meminfo07:15:2211
347275499830,82cyclictest3685342-21meminfo10:55:2314
347275499830,82cyclictest3685342-21meminfo10:55:2314
347275299830,82cyclictest3564320-21meminfo08:45:2113
347275299830,82cyclictest3564320-21meminfo08:45:2113
347275499820,81cyclictest3671181-21meminfo10:40:2214
347274799820,81cyclictest3717810-21meminfo11:30:208
347275599810,81cyclictest3638883-21meminfo10:05:2315
347275199810,80cyclictest3475196-21meminfo07:10:2312
347274999790,78cyclictest3550826-21meminfo08:30:2110
347274999790,78cyclictest3508596-21meminfo07:45:2110
347274699790,77cyclictest3601884-21meminfo09:25:231
347274999780,76cyclictest3754671-21meminfo12:10:2110
347274599770,76cyclictest3690004-21meminfo11:00:200
347274699760,74cyclictest3745633-21meminfo12:00:201
347275699740,73cyclictest3740980-21meminfo11:55:212
347275999730,72cyclictest3495122-21meminfo07:30:215
347274999730,72cyclictest3643391-21meminfo10:10:2110
347274899730,72cyclictest3624516-21meminfo09:50:229
347275799720,71cyclictest3606548-21meminfo09:30:213
347275599720,71cyclictest3611038-21meminfo09:35:2015
347275799710,70cyclictest3754672-21meminfo12:10:213
347275099710,70cyclictest3522978-21meminfo08:00:2111
347274899710,70cyclictest3759145-21meminfo12:15:219
347274699710,70cyclictest3690002-21meminfo11:00:201
347275999700,70cyclictest3522976-21meminfo08:00:205
347274599700,67cyclictest3675658-21meminfo10:45:230
347275799690,68cyclictest3652356-21meminfo10:20:233
347274899690,69cyclictest3546152-21meminfo08:25:219
347274899690,68cyclictest3513076-21meminfo07:50:229
347275999680,67cyclictest3480809-21meminfo07:15:225
347275899680,67cyclictest3722291-21meminfo11:35:224
347275899680,67cyclictest3568798-21meminfo08:50:204
347275299680,67cyclictest3532005-21meminfo08:10:2313
347274599680,66cyclictest3680131-21meminfo10:50:210
347274599680,66cyclictest3680131-21meminfo10:50:210
347275999670,66cyclictest3707976-21meminfo11:20:235
347275899670,66cyclictest3713148-21meminfo11:25:214
347275499670,64cyclictest3536486-21meminfo08:15:2114
347275499670,63cyclictest3703501-21meminfo11:15:2414
347275299670,66cyclictest3657530-21meminfo10:25:2213
347275299670,66cyclictest3638885-21meminfo10:05:2313
347275299670,66cyclictest3499599-21meminfo07:35:2313
347275299670,66cyclictest3495121-21meminfo07:30:2213
347275199670,66cyclictest3750150-21meminfo12:05:2012
347275199670,66cyclictest3583204-21meminfo09:05:2112
347275199670,66cyclictest3504113-21meminfo07:40:2212
347275099670,66cyclictest3518304-21meminfo07:55:2311
347274699670,66cyclictest3536487-21meminfo08:15:231
347275999660,65cyclictest3647877-21meminfo10:15:245
347275899660,65cyclictest3615567-21meminfo09:40:234
347275499660,65cyclictest3726812-21meminfo11:40:2214
347275299660,66cyclictest3587731-21meminfo09:10:2213
347275299660,65cyclictest3722293-21meminfo11:35:2213
347275199660,65cyclictest3773472-21meminfo12:30:2112
347275199660,65cyclictest3763622-21meminfo12:20:2212
347275199660,65cyclictest3596703-21meminfo09:20:2512
347275199660,65cyclictest3559836-21meminfo08:40:2412
347275199660,65cyclictest3559836-21meminfo08:40:2412
347275199660,65cyclictest3508598-21meminfo07:45:2112
347275099660,65cyclictest3735769-21meminfo11:50:2211
347274699660,65cyclictest3662187-21meminfo10:30:191
347275999650,64cyclictest3699021-21meminfo11:10:225
347275999650,64cyclictest3652354-21meminfo10:20:235
347275999650,64cyclictest3615566-21meminfo09:40:225
347275799650,65cyclictest3759146-21meminfo12:15:223
347275699650,64cyclictest3680127-21meminfo10:50:202
347275699650,64cyclictest3680127-21meminfo10:50:202
347275699650,64cyclictest3666681-21meminfo10:35:272
347275699650,64cyclictest3634385-21meminfo10:00:202
347275599650,65cyclictest3671180-21meminfo10:40:2115
347275599650,64cyclictest3657531-21meminfo10:25:2215
347275599650,64cyclictest3629727-21meminfo09:55:2215
347275499650,64cyclictest3662189-21meminfo10:30:1914
347275199650,65cyclictest3601885-21meminfo09:25:2412
347275099650,64cyclictest3777952-21meminfo12:35:2111
347275099650,64cyclictest3699020-21meminfo11:10:2111
347274999650,64cyclictest3768806-21meminfo12:25:2210
347274999650,64cyclictest3540962-21meminfo08:20:2010
347274799650,64cyclictest3685345-21meminfo10:55:238
347274799650,64cyclictest3685345-21meminfo10:55:238
347274799650,64cyclictest3675657-21meminfo10:45:248
347274799650,64cyclictest3634386-21meminfo10:00:208
347274799650,64cyclictest3499601-21meminfo07:35:238
347274699650,64cyclictest3624510-21meminfo09:50:211
347275999640,63cyclictest3583203-21meminfo09:05:215
347275999640,63cyclictest3518305-21meminfo07:55:235
347275899640,64cyclictest3592218-21meminfo09:15:234
347275899640,63cyclictest3485283-21meminfo07:20:214
347275799640,63cyclictest3694510-21meminfo11:05:243
347275799640,63cyclictest3555309-21meminfo08:35:223
347275699640,63cyclictest3611039-21meminfo09:35:202
347275699640,63cyclictest3578695-21meminfo09:00:212
347275599640,64cyclictest3620026-21meminfo09:45:2115
347275499640,63cyclictest3768804-21meminfo12:25:2214
347275499640,63cyclictest3527480-21meminfo08:05:2114
347275299640,63cyclictest3647876-21meminfo10:15:2313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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