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2026-02-11 - 10:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot8.osadl.org (updated Tue Feb 10, 2026 12:45:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23521759911230,1115cyclictest2504578-21meminfo09:35:122
2352166998413,829cyclictest2504578-21meminfo09:35:138
2352176997260,720cyclictest2565827-21meminfo10:30:123
2352169996930,689cyclictest2571366-21meminfo10:35:1410
2352174996361,633cyclictest2406937-21meminfo08:00:1015
2352168996011,598cyclictest2526417-21meminfo09:55:109
2352168995950,592cyclictest2558853-21meminfo10:25:129
2352168995771,573cyclictest2542364-21meminfo10:10:119
2352175995560,552cyclictest2531923-21meminfo10:00:092
2352176994810,479cyclictest2576578-21meminfo10:40:113
2352176994810,479cyclictest2576578-21meminfo10:40:113
2352174994732,470cyclictest2395592-21meminfo07:50:1015
2352176994641,459cyclictest2582836-21meminfo10:45:113
2352176994641,459cyclictest2582836-21meminfo10:45:113
2352173994611,456cyclictest2390457-21meminfo07:45:1414
2352164994321,425cyclictest2558855-21meminfo10:25:121
235217199424421,2cyclictest2387053-21kworker/u64:5+events_unbound08:24:2312
235216699422420,1cyclictest34759450usb-storage08:23:278
235216699411410,1cyclictest0-21swapper/211:55:008
235216699409407,1cyclictest0-21swapper/208:19:088
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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