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2025-11-05 - 19:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot8.osadl.org (updated Wed Nov 05, 2025 12:45:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137017699930,92cyclictest1690774-21meminfo12:30:2310
137017399910,90cyclictest1556798-21meminfo10:15:211
137018199900,88cyclictest1620899-21meminfo11:20:1915
137017799900,89cyclictest1497343-21meminfo09:15:2011
137017399900,88cyclictest1423415-21meminfo08:00:181
137018199890,88cyclictest1507611-21meminfo09:25:1915
137018299880,87cyclictest1522313-21meminfo09:40:202
137018299880,87cyclictest1522313-21meminfo09:40:192
137018299880,87cyclictest1403352-21meminfo07:40:212
137017799880,86cyclictest1641023-21meminfo11:40:2111
137017399880,87cyclictest1477850-21meminfo08:55:201
137017699850,83cyclictest1656059-21meminfo11:55:2010
137017699850,83cyclictest1656059-21meminfo11:55:2010
137017399850,84cyclictest1631458-21meminfo11:30:241
137017499840,82cyclictest1442654-21meminfo08:20:228
137018599830,82cyclictest1372531-21meminfo07:10:215
137018599830,82cyclictest1372531-21meminfo07:10:205
137018599830,81cyclictest1695591-21meminfo12:35:215
137018199830,82cyclictest1383311-21meminfo07:20:2115
137018099830,82cyclictest1561578-21meminfo10:20:2014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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