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2025-05-03 - 01:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot8.osadl.org (updated Fri May 02, 2025 12:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
100723499900,89cyclictest1293720-21meminfo12:15:201
100724599880,87cyclictest1280241-21meminfo12:00:203
100724699820,81cyclictest1075641-21meminfo08:20:244
100724499820,81cyclictest1113343-21meminfo09:00:232
100723399820,80cyclictest1192106-21meminfo10:25:210
100723899810,80cyclictest1261393-21meminfo11:40:2211
100724199730,72cyclictest1159068-21meminfo09:50:2414
100723899730,72cyclictest1280240-21meminfo12:00:2011
100723599720,72cyclictest1265871-21meminfo11:45:208
100723599720,72cyclictest1265871-21meminfo11:45:208
100723399710,70cyclictest1062139-21meminfo08:05:210
100724599700,68cyclictest1233616-21meminfo11:10:213
100724499700,69cyclictest1229100-21meminfo11:05:222
100723599700,69cyclictest1080821-21meminfo08:25:248
100724799680,67cyclictest1289237-21meminfo12:10:195
100724599680,67cyclictest1117827-21meminfo09:05:223
100724599680,67cyclictest1052755-21meminfo07:55:243
100724599680,67cyclictest1019748-21meminfo07:20:203
1007241996865,1cyclictest11216-21Timer09:59:0814
100723499680,67cyclictest1047520-21meminfo07:50:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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