You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-05-02 - 12:40
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Thu May 01, 2025 12:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
347275899910,90cyclictest3620027-21meminfo09:45:214
347275599890,88cyclictest3592216-21meminfo09:15:2315
347275099870,85cyclictest3694511-21meminfo11:05:2511
347275099840,83cyclictest3480811-21meminfo07:15:2211
347275499830,82cyclictest3685342-21meminfo10:55:2314
347275499830,82cyclictest3685342-21meminfo10:55:2314
347275299830,82cyclictest3564320-21meminfo08:45:2113
347275299830,82cyclictest3564320-21meminfo08:45:2113
347275499820,81cyclictest3671181-21meminfo10:40:2214
347274799820,81cyclictest3717810-21meminfo11:30:208
347275599810,81cyclictest3638883-21meminfo10:05:2315
347275199810,80cyclictest3475196-21meminfo07:10:2312
347274999790,78cyclictest3550826-21meminfo08:30:2110
347274999790,78cyclictest3508596-21meminfo07:45:2110
347274699790,77cyclictest3601884-21meminfo09:25:231
347274999780,76cyclictest3754671-21meminfo12:10:2110
347274599770,76cyclictest3690004-21meminfo11:00:200
347274699760,74cyclictest3745633-21meminfo12:00:201
347275699740,73cyclictest3740980-21meminfo11:55:212
347275999730,72cyclictest3495122-21meminfo07:30:215
347274999730,72cyclictest3643391-21meminfo10:10:2110
347274899730,72cyclictest3624516-21meminfo09:50:229
347275799720,71cyclictest3606548-21meminfo09:30:213
347275599720,71cyclictest3611038-21meminfo09:35:2015
347275799710,70cyclictest3754672-21meminfo12:10:213
347275099710,70cyclictest3522978-21meminfo08:00:2111
347274899710,70cyclictest3759145-21meminfo12:15:219
347274699710,70cyclictest3690002-21meminfo11:00:201
347275999700,70cyclictest3522976-21meminfo08:00:205
347274599700,67cyclictest3675658-21meminfo10:45:230
347275799690,68cyclictest3652356-21meminfo10:20:233
347274899690,69cyclictest3546152-21meminfo08:25:219
347274899690,68cyclictest3513076-21meminfo07:50:229
347275999680,67cyclictest3480809-21meminfo07:15:225
347275899680,67cyclictest3722291-21meminfo11:35:224
347275899680,67cyclictest3568798-21meminfo08:50:204
347275299680,67cyclictest3532005-21meminfo08:10:2313
347274599680,66cyclictest3680131-21meminfo10:50:210
347274599680,66cyclictest3680131-21meminfo10:50:210
347275999670,66cyclictest3707976-21meminfo11:20:235
347275899670,66cyclictest3713148-21meminfo11:25:214
347275499670,64cyclictest3536486-21meminfo08:15:2114
347275499670,63cyclictest3703501-21meminfo11:15:2414
347275299670,66cyclictest3657530-21meminfo10:25:2213
347275299670,66cyclictest3638885-21meminfo10:05:2313
347275299670,66cyclictest3499599-21meminfo07:35:2313
347275299670,66cyclictest3495121-21meminfo07:30:2213
347275199670,66cyclictest3750150-21meminfo12:05:2012
347275199670,66cyclictest3583204-21meminfo09:05:2112
347275199670,66cyclictest3504113-21meminfo07:40:2212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional