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2025-06-17 - 01:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Mon Jun 16, 2025 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1560864991200,119cyclictest1568985-21meminfo07:15:215
1560851991150,114cyclictest1692272-21meminfo09:25:231
156085299770,76cyclictest1563250-21meminfo07:10:198
156086299760,74cyclictest1729984-21meminfo10:05:223
156086299760,74cyclictest1729984-21meminfo10:05:213
156086099760,75cyclictest1616555-21meminfo08:05:212
156086099760,75cyclictest1616555-21meminfo08:05:212
156085599750,74cyclictest1578793-21meminfo07:25:2011
156085199750,75cyclictest1800543-21meminfo11:20:231
156085599730,72cyclictest1782227-21meminfo11:00:2211
156085099730,71cyclictest1838950-21meminfo12:00:240
156086099720,71cyclictest1777437-21meminfo10:55:212
156085599720,71cyclictest1668682-21meminfo09:00:2511
156085199720,71cyclictest1734569-21meminfo10:10:221
156086499700,69cyclictest1725416-21meminfo10:00:235
156086499700,69cyclictest1725416-21meminfo10:00:235
156086299700,68cyclictest1824339-21meminfo11:45:253
156086099700,69cyclictest1805803-21meminfo11:25:232
156085999700,69cyclictest1791388-21meminfo11:10:2615
156085999700,69cyclictest1644863-21meminfo08:35:2515
156085399700,69cyclictest1635531-21meminfo08:25:209
156085199700,69cyclictest1791387-21meminfo11:10:251
156086099690,68cyclictest1573554-21meminfo07:20:222
156085899690,68cyclictest1611970-21meminfo08:00:2014
1560857996961,2cyclictest0-21swapper/711:05:0213
156085199690,68cyclictest1616551-21meminfo08:05:211
156085199690,68cyclictest1616551-21meminfo08:05:211
156085099690,68cyclictest1706184-21meminfo09:40:210
156086299680,67cyclictest1848104-21meminfo12:10:243
156086299680,67cyclictest1848104-21meminfo12:10:243
156086099680,67cyclictest1838948-21meminfo12:00:232
156086099680,67cyclictest1815145-21meminfo11:35:212
156085899680,67cyclictest1795978-21meminfo11:15:2214
156085899680,67cyclictest1601924-21meminfo07:50:2214
156085799680,67cyclictest1871908-21meminfo12:35:2313
156085599680,67cyclictest1649425-21meminfo08:40:2211
156085199680,68cyclictest1819701-21meminfo11:40:251
156085199680,67cyclictest1687015-21meminfo09:20:241
156085199680,67cyclictest1630280-21meminfo08:20:221
156085099680,67cyclictest1601926-21meminfo07:50:220
156086399670,66cyclictest1635533-21meminfo08:25:204
156086099670,67cyclictest1852718-21meminfo12:15:252
156085999670,66cyclictest1867345-21meminfo12:30:2415
156085999670,66cyclictest1734568-21meminfo10:10:2215
156085899670,66cyclictest1862544-21meminfo12:25:2314
156085899670,66cyclictest1786828-21meminfo11:05:2214
156085899670,66cyclictest1663884-21meminfo08:55:2414
156085599670,66cyclictest1673296-21meminfo09:05:2511
156085499670,66cyclictest1673297-21meminfo09:05:2610
156085499670,66cyclictest1588141-21meminfo07:35:2110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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