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2025-07-03 - 08:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot8.osadl.org (updated Wed Jul 02, 2025 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3765728994380,437cyclictest0-21swapper/810:08:1314
376572899433431,1cyclictest28550irq/127-xhci_hcd10:01:2414
376572599425422,2cyclictest3924216-21kworker/u64:0+events_unbound10:21:1712
376572899421420,1cyclictest0-21swapper/810:21:1714
376572099417415,1cyclictest0-21swapper/110:08:131
376572599415411,3cyclictest4021858-21kworker/u64:1+events_unbound12:26:5112
376572099415413,1cyclictest0-21swapper/110:01:251
376572599414411,2cyclictest4008653-21kworker/u64:2+events_unbound11:45:0012
376572599412408,3cyclictest3862433-21kworker/u64:1+events_unbound10:17:0612
376572299407406,1cyclictest0-21swapper/309:39:059
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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