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2024-09-16 - 00:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot8.osadl.org (updated Sun Sep 15, 2024 12:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3730979995601,555cyclictest3775146-21meminfo07:55:222
373098499438436,1cyclictest0-21swapper/1509:56:227
373098499435434,0cyclictest0-21swapper/1511:20:387
373098199419417,1cyclictest3918954-21kworker/u64:4+events_unbound11:20:394
373097299413411,1cyclictest3839366-21kworker/u64:3+events_unbound10:20:3012
373097299412410,1cyclictest3878830-21kworker/u64:1+events_unbound10:31:1312
373098199411411,0cyclictest0-21swapper/1209:23:224
373098199411411,0cyclictest0-21swapper/1209:23:224
373098199409406,2cyclictest7647-21seamonkey12:15:584
373098499407405,1cyclictest0-21swapper/1510:16:267
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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