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2026-02-09 - 10:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot8.osadl.org (updated Sun Feb 08, 2026 12:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
58301997580,754cyclictest333846-21meminfo11:40:069
58302995560,552cyclictest151386-21meminfo08:40:0810
58308995210,519cyclictest348981-21meminfo11:55:0614
58302994931,490cyclictest343540-21meminfo11:50:0610
58313994750,472cyclictest94888-21meminfo07:45:095
5830899431426,3cyclictest0-21swapper/809:15:5814
5831599430426,1cyclictest0-21swapper/1507:11:037
5831099428421,4cyclictest222773-21kworker/u64:2+events_unbound11:01:042
5831599425424,0cyclictest0-21swapper/1509:54:147
5830899422419,1cyclictest0-21swapper/811:01:0414
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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