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2025-12-31 - 16:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot3.osadl.org (updated Wed Dec 31, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
285466699130,11cyclictest0-21swapper/309:10:143
2854666991211,0cyclictest0-21swapper/311:45:123
285466699120,1cyclictest0-21swapper/308:00:123
285466699120,11cyclictest0-21swapper/312:10:023
285466699120,11cyclictest0-21swapper/307:20:163
2854666991110,0cyclictest0-21swapper/312:25:153
2854666991110,0cyclictest0-21swapper/312:15:163
2854666991110,0cyclictest0-21swapper/309:00:143
2854666991110,0cyclictest0-21swapper/307:55:103
285466699110,10cyclictest0-21swapper/312:23:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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