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2026-05-15 - 23:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot3.osadl.org (updated Fri May 15, 2026 12:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3296222991311,1cyclictest0-21swapper/311:45:123
329622299130,11cyclictest0-21swapper/311:05:113
329622299129,1cyclictest0-21swapper/308:35:113
329622299120,11cyclictest0-21swapper/312:35:013
329622299120,11cyclictest0-21swapper/311:11:513
329622299120,11cyclictest0-21swapper/309:40:013
329622299120,11cyclictest0-21swapper/309:00:123
329622299119,1cyclictest0-21swapper/311:15:123
329622299119,0cyclictest0-21swapper/310:05:123
3296222991111,0cyclictest0-21swapper/307:50:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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