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2026-03-31 - 19:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot3.osadl.org (updated Tue Mar 31, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2748700991513,0cyclictest0-21swapper/312:30:103
2748700991413,0cyclictest0-21swapper/307:37:143
274870099130,8cyclictest0-21swapper/311:30:123
274870099130,11cyclictest0-21swapper/307:40:123
2748700991210,1cyclictest0-21swapper/310:15:133
274870099120,1cyclictest0-21swapper/309:35:183
274870099120,11cyclictest0-21swapper/311:45:163
274870099120,11cyclictest0-21swapper/308:25:103
274870099119,1cyclictest0-21swapper/309:05:133
2748700991111,0cyclictest0-21swapper/312:14:573
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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