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2026-06-30 - 01:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot3.osadl.org (updated Tue Jun 30, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
271829991413,0cyclictest0-21swapper/323:33:473
271829991413,0cyclictest0-21swapper/321:00:103
271829991313,0cyclictest0-21swapper/323:21:303
271829991313,0cyclictest0-21swapper/323:06:083
271829991313,0cyclictest0-21swapper/322:13:543
271829991313,0cyclictest0-21swapper/321:59:343
271829991313,0cyclictest0-21swapper/320:55:043
271829991313,0cyclictest0-21swapper/319:43:223
271829991313,0cyclictest0-21swapper/319:38:163
271829991313,0cyclictest0-21swapper/300:35:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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