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2026-01-21 - 18:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot3.osadl.org (updated Wed Jan 21, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121468991411,1cyclictest0-21swapper/312:25:093
121468991312,0cyclictest0-21swapper/311:05:133
12146899130,2cyclictest0-21swapper/308:00:113
12146899130,11cyclictest0-21swapper/307:40:123
12146899130,11cyclictest0-21swapper/307:35:123
12146899129,1cyclictest0-21swapper/310:15:123
121468991211,0cyclictest0-21swapper/308:10:113
121468991211,0cyclictest0-21swapper/307:55:133
121468991210,1cyclictest0-21swapper/308:05:103
12146899120,9cyclictest0-21swapper/311:55:103
12146899120,11cyclictest0-21swapper/312:35:133
12146899120,11cyclictest0-21swapper/312:30:123
12146899120,11cyclictest0-21swapper/309:25:173
12146899120,11cyclictest0-21swapper/308:55:113
12146899120,11cyclictest0-21swapper/307:45:133
12146899120,0cyclictest0-21swapper/310:40:123
121468991110,0cyclictest0-21swapper/307:15:013
12146899110,10cyclictest0-21swapper/311:45:013
12146899110,0cyclictest0-21swapper/310:00:013
12146899110,0cyclictest0-21swapper/309:30:183
12146899110,0cyclictest0-21swapper/307:30:123
12146899109,0cyclictest0-21swapper/312:20:093
12146899109,0cyclictest0-21swapper/311:27:003
12146899109,0cyclictest0-21swapper/311:14:033
12146899109,0cyclictest0-21swapper/308:25:133
121468991010,0cyclictest0-21swapper/312:15:133
121468991010,0cyclictest0-21swapper/310:46:563
121468991010,0cyclictest0-21swapper/309:55:133
121468991010,0cyclictest0-21swapper/308:30:123
121468991010,0cyclictest0-21swapper/308:25:013
12146899100,9cyclictest0-21swapper/311:00:153
12146899100,9cyclictest0-21swapper/310:25:183
12146899100,0cyclictest0-21swapper/309:05:163
12146899100,0cyclictest0-21swapper/307:10:103
1214689999,0cyclictest0-21swapper/311:30:403
1214689999,0cyclictest0-21swapper/310:35:113
1214689999,0cyclictest0-21swapper/310:20:103
1214689999,0cyclictest0-21swapper/308:40:173
1214689998,0cyclictest0-21swapper/311:19:513
1214689988,0cyclictest0-21swapper/311:51:283
1214689988,0cyclictest0-21swapper/310:05:133
1214689988,0cyclictest0-21swapper/309:45:133
1214689988,0cyclictest0-21swapper/307:50:153
1214689988,0cyclictest0-21swapper/307:20:013
1214689987,0cyclictest0-21swapper/311:35:133
1214689987,0cyclictest0-21swapper/310:55:123
1214689987,0cyclictest0-21swapper/309:35:163
1214689986,1cyclictest0-21swapper/309:20:113
1214689980,7cyclictest0-21swapper/308:45:183
1214689977,0cyclictest0-21swapper/312:10:203
1214689977,0cyclictest0-21swapper/311:47:513
1214689977,0cyclictest0-21swapper/308:35:173
1214689976,0cyclictest0-21swapper/312:08:243
1214689976,0cyclictest0-21swapper/312:08:243
1214689976,0cyclictest0-21swapper/310:10:183
1214689970,6cyclictest0-21swapper/312:05:013
121003271,1sleep20-21swapper/207:06:232
14039860,2rtkit-daemon328-21plymouthd07:05:190
1214689960,4cyclictest0-21swapper/310:30:113
1214689960,0cyclictest0-21swapper/309:15:183
119991261,3sleep30-21swapper/307:05:163
14039850,2rtkit-daemon157693-21df08:40:130
1214689955,0cyclictest0-21swapper/309:50:163
1214689955,0cyclictest0-21swapper/309:10:163
1214689955,0cyclictest0-21swapper/308:50:173
1214689954,0cyclictest0-21swapper/309:00:123
1214689950,4cyclictest0-21swapper/307:25:153
167464240,1sleep0167613-21ntp_states09:05:160
14039840,2rtkit-daemon766-21snmpd12:25:061
14039840,2rtkit-daemon766-21snmpd11:15:101
14039840,2rtkit-daemon766-21snmpd11:08:251
14039840,2rtkit-daemon691-21gmain10:28:280
14039840,2rtkit-daemon592-21rpcbind10:44:141
14039840,2rtkit-daemon168522-21diskmemload11:30:201
14039840,2rtkit-daemon168522-21diskmemload10:17:400
14039840,2rtkit-daemon1-21systemd11:59:241
14039840,1rtkit-daemon328-21plymouthd11:00:121
1214689944,0cyclictest0-21swapper/311:20:123
1214689944,0cyclictest0-21swapper/310:50:173
1214689940,2cyclictest0-21swapper/309:40:123
1214689940,2cyclictest0-21swapper/308:15:123
119621242,1sleep10-21swapper/107:05:101
194036230,2sleep0194152-21telnet10:10:120
182834230,2sleep2182886-21cut09:45:012
177373230,2sleep2177551-21sed09:30:162
160540230,0sleep20-21swapper/208:46:052
14039830,2rtkit-daemon769-21ntpd09:50:170
14039830,2rtkit-daemon766-21snmpd11:25:191
14039830,2rtkit-daemon766-21snmpd09:15:150
14039830,2rtkit-daemon766-21snmpd07:50:160
14039830,2rtkit-daemon592-21rpcbind09:00:100
14039830,2rtkit-daemon328-21plymouthd07:43:230
14039830,1rtkit-daemon772-21lldpd12:15:051
14039830,1rtkit-daemon769-21ntpd07:37:010
14039830,1rtkit-daemon766-21snmpd09:22:510
14039830,1rtkit-daemon622-21wpa_supplicant12:36:281
14039830,1rtkit-daemon622-21wpa_supplicant12:20:071
14039830,1rtkit-daemon606-21avahi-daemon10:51:061
14039830,1rtkit-daemon328-21plymouthd09:41:280
14039830,1rtkit-daemon234647-21strings11:45:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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