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2026-01-22 - 20:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot3.osadl.org (updated Thu Jan 22, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19448499130,12cyclictest0-21swapper/309:00:183
194484991211,1cyclictest0-21swapper/307:35:113
194484991211,0cyclictest0-21swapper/312:15:123
194484991211,0cyclictest0-21swapper/312:00:143
19448499120,1cyclictest0-21swapper/312:30:103
19448499120,11cyclictest0-21swapper/311:15:123
19448499120,11cyclictest0-21swapper/310:40:023
19448499120,10cyclictest0-21swapper/308:22:413
194484991111,0cyclictest0-21swapper/311:20:113
194484991110,0cyclictest0-21swapper/312:05:123
194484991110,0cyclictest0-21swapper/311:10:123
19448499110,10cyclictest0-21swapper/311:50:163
19448499110,10cyclictest0-21swapper/307:43:373
19448499110,10cyclictest0-21swapper/307:15:003
19448499110,10cyclictest0-21swapper/307:10:163
19448499110,0cyclictest0-21swapper/312:25:013
19448499110,0cyclictest0-21swapper/311:05:123
19448499110,0cyclictest0-21swapper/310:10:123
19448499110,0cyclictest0-21swapper/308:30:123
19448499109,0cyclictest0-21swapper/312:25:133
19448499109,0cyclictest0-21swapper/309:51:383
19448499108,1cyclictest0-21swapper/312:10:113
194484991010,0cyclictest0-21swapper/310:05:193
194484991010,0cyclictest0-21swapper/309:55:133
194484991010,0cyclictest0-21swapper/308:50:133
194484991010,0cyclictest0-21swapper/308:40:113
19448499100,9cyclictest0-21swapper/311:55:123
19448499100,9cyclictest0-21swapper/310:00:123
19448499100,0cyclictest0-21swapper/307:30:173
1944849999,0cyclictest0-21swapper/311:40:003
1944849999,0cyclictest0-21swapper/311:00:113
1944849999,0cyclictest0-21swapper/308:55:193
1944849999,0cyclictest0-21swapper/308:45:113
1944849999,0cyclictest0-21swapper/308:10:183
1944849999,0cyclictest0-21swapper/307:50:123
1944849990,8cyclictest0-21swapper/310:25:123
1944849990,0cyclictest0-21swapper/311:50:003
1944849988,0cyclictest0-21swapper/311:35:223
1944849988,0cyclictest0-21swapper/310:15:143
1944849988,0cyclictest0-21swapper/309:50:023
1944849988,0cyclictest0-21swapper/309:15:173
1944849986,1cyclictest0-21swapper/311:30:123
1944849985,1cyclictest0-21swapper/309:40:103
1944849980,8cyclictest0-21swapper/307:10:013
1944849980,7cyclictest0-21swapper/310:46:413
1944849980,0cyclictest0-21swapper/310:25:013
1944849980,0cyclictest0-21swapper/308:30:013
1944849977,0cyclictest0-21swapper/311:25:123
1944849977,0cyclictest0-21swapper/310:30:133
1944849977,0cyclictest0-21swapper/308:15:173
1944849977,0cyclictest0-21swapper/307:25:003
1944849970,7cyclictest0-21swapper/310:55:143
1944849970,0cyclictest0-21swapper/310:45:013
1944849966,0cyclictest0-21swapper/310:55:023
1944849966,0cyclictest0-21swapper/309:05:193
1944849966,0cyclictest0-21swapper/308:05:163
1944849966,0cyclictest0-21swapper/307:45:133
1944849960,5cyclictest0-21swapper/307:28:193
1944849955,0cyclictest0-21swapper/312:35:153
1944849955,0cyclictest0-21swapper/309:30:123
1944849955,0cyclictest0-21swapper/309:25:123
1944849955,0cyclictest0-21swapper/309:10:123
1944849955,0cyclictest0-21swapper/308:35:113
1944849955,0cyclictest0-21swapper/307:55:113
1944849954,0cyclictest0-21swapper/309:20:213
194284251,2sleep10-21swapper/107:09:371
14039850,3rtkit-daemon243523-21sed09:10:192
14039850,3rtkit-daemon0-21swapper/207:05:092
203927240,3sleep0204075-21threads07:30:170
1944849940,4cyclictest0-21swapper/309:35:173
1944849940,3cyclictest214650-21chrt08:00:093
14039840,2rtkit-daemon766-21snmpd09:37:422
14039840,2rtkit-daemon766-21snmpd09:30:572
14039840,2rtkit-daemon766-21snmpd09:21:412
14039840,2rtkit-daemon418-21systemd-journal11:45:022
14039840,2rtkit-daemon196656-21munin-node10:25:142
14039840,2rtkit-daemon1410-21sendmail-mta09:02:332
14039840,2rtkit-daemon1-21systemd09:53:032
292721230,2sleep2291855-21/usr/sbin/munin11:20:182
277675230,2sleep1277678-21sshd10:39:381
224352230,1sleep0224380-40unattended-upgr08:22:410
192655231,1sleep00-21swapper/007:05:120
14039830,2rtkit-daemon769-21ntpd08:12:152
14039830,2rtkit-daemon1-21systemd12:31:272
14039830,2rtkit-daemon1-21systemd08:07:412
14039830,1rtkit-daemon769-21ntpd12:10:212
14039830,1rtkit-daemon769-21ntpd12:05:102
14039830,1rtkit-daemon766-21snmpd11:55:432
14039830,1rtkit-daemon766-21snmpd11:37:102
14039830,1rtkit-daemon766-21snmpd09:45:372
14039830,1rtkit-daemon766-21snmpd08:56:412
14039830,1rtkit-daemon622-21wpa_supplicant10:33:092
14039830,1rtkit-daemon622-21wpa_supplicant09:40:162
14039830,1rtkit-daemon606-21avahi-daemon08:00:262
14039830,1rtkit-daemon328-21plymouthd11:10:132
14039830,1rtkit-daemon328-21plymouthd10:58:352
14039830,1rtkit-daemon328-21plymouthd10:12:292
14039830,1rtkit-daemon328-21plymouthd09:17:262
14039830,1rtkit-daemon328-21plymouthd07:42:402
14039830,1rtkit-daemon325254-21cron12:40:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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