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2025-05-03 - 01:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sat May 03, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
335852999151,12cyclictest0-21swapper/321:40:153
335852999130,11cyclictest0-21swapper/322:30:133
335852999130,11cyclictest0-21swapper/321:15:143
335852999130,11cyclictest0-21swapper/319:22:113
3358529991211,0cyclictest0-21swapper/323:35:133
3358529991210,1cyclictest0-21swapper/322:15:133
335852999120,11cyclictest0-21swapper/323:20:123
335852999120,11cyclictest0-21swapper/322:35:153
335852999120,11cyclictest0-21swapper/320:30:023
335852999120,11cyclictest0-21swapper/300:15:133
335852999120,11cyclictest0-21swapper/300:00:253
3358529991111,0cyclictest0-21swapper/322:00:133
3358529991111,0cyclictest0-21swapper/321:45:193
3358529991111,0cyclictest0-21swapper/321:25:133
3358529991110,0cyclictest0-21swapper/320:10:123
3358529991110,0cyclictest0-21swapper/300:20:153
335852999110,10cyclictest3379546-21chrt20:00:203
335852999110,10cyclictest0-21swapper/322:05:133
335852999110,10cyclictest0-21swapper/300:35:013
335852999110,0cyclictest0-21swapper/323:50:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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