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2026-01-28 - 10:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Wed Jan 28, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2530608991610,5cyclictest0-21swapper/319:20:103
2530608991511,0cyclictest0-21swapper/300:05:133
253060899130,2cyclictest0-21swapper/322:25:123
253060899130,11cyclictest0-21swapper/320:05:133
253060899130,11cyclictest0-21swapper/319:50:103
253060899130,11cyclictest0-21swapper/300:30:133
2530608991211,0cyclictest0-21swapper/319:45:133
253060899120,11cyclictest0-21swapper/321:30:113
253060899120,11cyclictest0-21swapper/320:40:183
253060899120,11cyclictest0-21swapper/320:00:013
2530608991111,0cyclictest0-21swapper/319:15:013
2530608991111,0cyclictest0-21swapper/300:20:133
2530608991110,0cyclictest0-21swapper/320:55:123
253060899110,11cyclictest0-21swapper/319:45:013
253060899110,10cyclictest0-21swapper/323:59:593
253060899110,10cyclictest0-21swapper/323:30:013
253060899110,10cyclictest0-21swapper/323:05:183
253060899110,10cyclictest0-21swapper/321:55:113
253060899110,10cyclictest0-21swapper/321:10:173
253060899110,0cyclictest0-21swapper/323:30:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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