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2026-05-13 - 18:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Wed May 13, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
353009399160,13cyclictest0-21swapper/308:05:113
3530093991311,1cyclictest0-21swapper/307:40:123
353009399130,1cyclictest0-21swapper/308:30:123
353009399130,11cyclictest0-21swapper/311:55:123
353009399130,11cyclictest0-21swapper/311:15:123
3530093991211,0cyclictest0-21swapper/312:20:123
3530093991211,0cyclictest0-21swapper/310:35:163
3530093991211,0cyclictest0-21swapper/308:15:123
3530093991210,1cyclictest0-21swapper/310:55:123
353009399120,1cyclictest0-21swapper/310:40:103
353009399120,11cyclictest0-21swapper/309:20:013
3530093991110,0cyclictest0-21swapper/309:05:133
3530093991110,0cyclictest0-21swapper/307:25:123
353009399110,8cyclictest0-21swapper/310:00:013
353009399110,11cyclictest0-21swapper/311:15:023
353009399110,10cyclictest0-21swapper/310:45:193
353009399110,10cyclictest0-21swapper/308:35:163
353009399110,0cyclictest0-21swapper/308:20:133
353009399110,0cyclictest0-21swapper/307:34:593
353009399109,0cyclictest0-21swapper/311:40:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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