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2025-06-28 - 22:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sat Jun 28, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
207757799140,12cyclictest0-21swapper/307:25:133
207757799130,1cyclictest0-21swapper/307:35:233
207757799130,11cyclictest0-21swapper/312:30:143
207757799130,11cyclictest0-21swapper/310:40:163
2077577991211,0cyclictest0-21swapper/308:55:143
2077577991211,0cyclictest0-21swapper/308:45:143
207757799120,1cyclictest2137064-21chrt09:40:163
207757799120,11cyclictest0-21swapper/312:05:163
207757799120,11cyclictest0-21swapper/312:00:153
207757799120,11cyclictest0-21swapper/310:15:013
207757799120,11cyclictest0-21swapper/310:10:013
207757799120,11cyclictest0-21swapper/309:00:213
2077577991111,0cyclictest0-21swapper/311:15:193
2077577991110,0cyclictest0-21swapper/311:55:133
2077577991110,0cyclictest0-21swapper/309:20:123
207757799110,8cyclictest0-21swapper/311:30:013
207757799110,10cyclictest0-21swapper/309:50:203
207757799110,10cyclictest0-21swapper/309:10:143
207757799110,10cyclictest0-21swapper/308:20:003
207757799110,0cyclictest0-21swapper/310:45:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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