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2025-12-15 - 01:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sun Dec 14, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
204580699121,0cyclictest0-21swapper/309:45:133
204580699120,1cyclictest0-21swapper/312:35:143
2045806991111,0cyclictest0-21swapper/311:40:153
2045806991110,1cyclictest0-21swapper/308:05:123
2045806991110,0cyclictest0-21swapper/311:50:113
2045806991110,0cyclictest0-21swapper/307:20:203
204580699110,10cyclictest0-21swapper/309:20:193
204580699110,10cyclictest0-21swapper/307:25:163
204580699110,10cyclictest0-21swapper/307:15:013
204580699110,0cyclictest0-21swapper/310:35:123
204580699110,0cyclictest0-21swapper/310:30:013
204580699110,0cyclictest0-21swapper/310:25:013
204580699110,0cyclictest0-21swapper/308:55:133
204580699109,1cyclictest0-21swapper/310:25:133
204580699109,0cyclictest0-21swapper/308:40:183
2045806991010,0cyclictest0-21swapper/311:05:153
2045806991010,0cyclictest0-21swapper/309:35:183
2045806991010,0cyclictest0-21swapper/308:10:133
204580699100,9cyclictest0-21swapper/307:30:133
204580699100,10cyclictest0-21swapper/312:30:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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