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2025-11-09 - 08:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sun Nov 09, 2025 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2758054991611,0cyclictest0-21swapper/320:35:003
275805499140,12cyclictest0-21swapper/321:35:133
2758054991311,1cyclictest0-21swapper/321:40:143
2758054991310,2cyclictest0-21swapper/320:20:133
2758054991310,1cyclictest0-21swapper/319:40:123
275805499130,11cyclictest0-21swapper/322:55:133
275805499121,10cyclictest69450irq/121-eno100:15:133
2758054991211,0cyclictest0-21swapper/320:40:133
275805499120,1cyclictest0-21swapper/321:25:013
275805499120,11cyclictest0-21swapper/322:40:133
275805499120,11cyclictest0-21swapper/322:30:133
275805499120,11cyclictest0-21swapper/322:25:163
275805499120,11cyclictest0-21swapper/322:10:173
275805499120,11cyclictest0-21swapper/321:55:173
275805499120,11cyclictest0-21swapper/321:45:203
2758054991111,0cyclictest0-21swapper/320:35:133
2758054991111,0cyclictest0-21swapper/300:08:373
2758054991110,1cyclictest69450irq/121-eno122:19:263
2758054991110,0cyclictest69450irq/121-eno121:51:003
2758054991110,0cyclictest0-21swapper/323:50:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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