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2025-12-03 - 18:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Wed Dec 03, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
408964799137,5cyclictest0-21swapper/310:45:023
408964799126,5cyclictest0-21swapper/308:20:143
4089647991211,0cyclictest0-21swapper/312:00:203
4089647991211,0cyclictest0-21swapper/308:55:133
4089647991210,1cyclictest69450irq/121-eno112:15:133
4089647991210,1cyclictest0-21swapper/311:35:123
408964799120,11cyclictest69450irq/121-eno111:44:463
408964799120,11cyclictest0-21swapper/309:35:143
408964799120,11cyclictest0-21swapper/308:40:213
408964799120,11cyclictest0-21swapper/308:25:123
408964799120,10cyclictest0-21swapper/310:55:183
408964799119,0cyclictest0-21swapper/312:05:023
4089647991111,0cyclictest69450irq/121-eno109:15:183
4089647991111,0cyclictest0-21swapper/308:45:133
408964799111,0cyclictest0-21swapper/309:05:003
4089647991110,1cyclictest69450irq/121-eno110:28:113
4089647991110,0cyclictest0-21swapper/311:10:123
4089647991110,0cyclictest0-21swapper/309:15:003
408964799110,9cyclictest0-21swapper/310:30:133
408964799110,10cyclictest69450irq/121-eno109:50:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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