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2025-08-31 - 02:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sun Aug 31, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
241895199141,12cyclictest0-21swapper/321:45:133
241895199140,13cyclictest0-21swapper/322:30:123
241895199140,11cyclictest0-21swapper/320:17:223
241895199140,11cyclictest0-21swapper/320:17:213
2418951991310,1cyclictest0-21swapper/323:45:123
241895199130,11cyclictest0-21swapper/323:40:123
2418951991211,1cyclictest69450irq/121-eno100:00:143
241895199120,11cyclictest69450irq/121-eno123:20:203
241895199120,11cyclictest69450irq/121-eno123:17:303
241895199120,11cyclictest0-21swapper/321:55:133
241895199120,11cyclictest0-21swapper/321:35:013
241895199120,0cyclictest0-21swapper/321:05:163
241895199119,1cyclictest69450irq/121-eno122:25:003
2418951991111,0cyclictest69450irq/121-eno120:47:533
2418951991110,0cyclictest0-21swapper/320:55:123
241895199110,10cyclictest69450irq/121-eno121:20:123
241895199110,10cyclictest0-21swapper/323:59:593
241895199110,10cyclictest0-21swapper/322:55:143
241895199110,10cyclictest0-21swapper/322:45:193
241895199110,10cyclictest0-21swapper/322:25:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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