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2026-03-14 - 14:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sat Mar 14, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3445617991412,1cyclictest0-21swapper/308:45:113
3445617991310,1cyclictest0-21swapper/312:30:123
3445617991211,0cyclictest0-21swapper/312:40:013
344561799120,11cyclictest0-21swapper/311:35:123
344561799120,11cyclictest0-21swapper/310:45:183
344561799120,11cyclictest0-21swapper/310:14:563
344561799120,11cyclictest0-21swapper/309:15:113
3445617991111,0cyclictest0-21swapper/307:10:013
3445617991110,0cyclictest0-21swapper/307:50:123
344561799110,9cyclictest0-21swapper/312:10:123
344561799110,9cyclictest0-21swapper/308:35:123
344561799110,11cyclictest0-21swapper/308:30:183
344561799110,10cyclictest0-21swapper/310:50:173
344561799110,0cyclictest0-21swapper/312:15:113
344561799110,0cyclictest0-21swapper/307:35:133
344561799109,0cyclictest0-21swapper/307:30:113
3445617991010,0cyclictest0-21swapper/311:55:173
3445617991010,0cyclictest0-21swapper/311:50:183
3445617991010,0cyclictest0-21swapper/311:25:123
3445617991010,0cyclictest0-21swapper/310:20:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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