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2025-11-16 - 09:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sun Nov 16, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2419404991311,1cyclictest0-21swapper/300:25:153
241940499130,12cyclictest0-21swapper/323:25:173
241940499129,1cyclictest0-21swapper/322:50:153
241940499120,11cyclictest0-21swapper/322:30:193
241940499120,11cyclictest0-21swapper/321:00:133
241940499120,11cyclictest0-21swapper/320:50:193
241940499120,11cyclictest0-21swapper/320:45:013
241940499120,11cyclictest0-21swapper/320:10:193
241940499120,11cyclictest0-21swapper/320:05:193
241940499120,11cyclictest0-21swapper/319:55:163
241940499120,11cyclictest0-21swapper/300:30:243
241940499112,8cyclictest69450irq/121-eno100:04:183
2419404991110,1cyclictest69450irq/121-eno123:39:563
241940499110,9cyclictest69450irq/121-eno123:50:163
241940499110,10cyclictest69450irq/121-eno123:09:593
241940499110,10cyclictest69450irq/121-eno122:35:153
241940499110,10cyclictest69450irq/121-eno121:45:193
241940499110,10cyclictest69450irq/121-eno120:00:153
241940499110,10cyclictest0-21swapper/319:25:173
241940499110,0cyclictest0-21swapper/323:00:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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