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2026-05-31 - 13:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Sun May 31, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
85230999148,5cyclictest0-21swapper/311:40:113
852309991410,1cyclictest0-21swapper/309:55:123
85230999120,1cyclictest0-21swapper/310:10:103
85230999120,1cyclictest0-21swapper/308:40:133
85230999120,11cyclictest0-21swapper/310:33:353
85230999120,11cyclictest0-21swapper/309:30:103
85230999120,11cyclictest0-21swapper/309:25:103
852309991110,0cyclictest0-21swapper/311:55:143
852309991110,0cyclictest0-21swapper/311:25:153
85230999110,10cyclictest0-21swapper/312:25:013
85230999110,10cyclictest0-21swapper/310:40:133
85230999110,10cyclictest0-21swapper/309:15:173
85230999110,0cyclictest0-21swapper/311:45:133
85230999109,0cyclictest0-21swapper/311:37:353
852309991010,0cyclictest0-21swapper/312:30:173
852309991010,0cyclictest0-21swapper/311:30:133
852309991010,0cyclictest0-21swapper/310:20:173
852309991010,0cyclictest0-21swapper/310:20:013
852309991010,0cyclictest0-21swapper/310:00:133
852309991010,0cyclictest0-21swapper/309:15:013
85230999100,9cyclictest0-21swapper/308:15:193
85230999100,10cyclictest0-21swapper/307:25:173
85230999100,0cyclictest0-21swapper/312:15:023
85230999100,0cyclictest0-21swapper/312:05:143
85230999100,0cyclictest0-21swapper/310:55:013
8523099999,0cyclictest0-21swapper/312:35:133
8523099999,0cyclictest0-21swapper/310:05:123
8523099999,0cyclictest0-21swapper/309:05:183
8523099999,0cyclictest0-21swapper/308:50:003
8523099999,0cyclictest0-21swapper/307:45:193
8523099999,0cyclictest0-21swapper/307:40:183
8523099998,0cyclictest0-21swapper/309:35:163
8523099990,8cyclictest0-21swapper/310:45:183
8523099990,0cyclictest0-21swapper/311:00:173
8523099990,0cyclictest0-21swapper/308:10:163
8523099988,0cyclictest0-21swapper/310:35:183
8523099988,0cyclictest0-21swapper/309:45:183
8523099988,0cyclictest0-21swapper/309:44:293
8523099988,0cyclictest0-21swapper/309:25:013
8523099988,0cyclictest0-21swapper/309:00:133
8523099988,0cyclictest0-21swapper/308:50:133
8523099988,0cyclictest0-21swapper/307:20:113
8523099988,0cyclictest0-21swapper/307:10:153
8523099980,7cyclictest0-21swapper/312:15:123
8523099977,0cyclictest0-21swapper/311:20:073
8523099977,0cyclictest0-21swapper/308:55:013
8523099977,0cyclictest0-21swapper/307:55:113
8523099977,0cyclictest0-21swapper/307:50:353
8523099977,0cyclictest0-21swapper/307:15:173
850539271,4sleep30-21swapper/307:05:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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