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2025-10-17 - 09:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Fri Oct 17, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325928299138,1cyclictest0-21swapper/323:20:143
3259282991210,1cyclictest0-21swapper/323:15:153
325928299120,9cyclictest0-21swapper/320:50:013
325928299120,1cyclictest0-21swapper/322:10:143
325928299120,1cyclictest0-21swapper/319:50:113
325928299120,11cyclictest0-21swapper/323:00:013
325928299120,11cyclictest0-21swapper/321:45:003
325928299120,11cyclictest0-21swapper/300:15:143
325928299120,0cyclictest0-21swapper/323:05:153
3259282991111,0cyclictest69450irq/121-eno122:15:193
3259282991111,0cyclictest69450irq/121-eno122:08:493
3259282991111,0cyclictest0-21swapper/320:10:203
3259282991111,0cyclictest0-21swapper/300:25:153
325928299110,10cyclictest69450irq/121-eno121:05:243
325928299110,10cyclictest0-21swapper/323:35:143
325928299110,10cyclictest0-21swapper/323:10:123
325928299110,10cyclictest0-21swapper/322:50:203
325928299110,10cyclictest0-21swapper/320:20:003
325928299110,0cyclictest0-21swapper/322:00:143
325928299110,0cyclictest0-21swapper/319:25:013
325928299109,0cyclictest0-21swapper/319:25:023
325928299107,2cyclictest0-21swapper/320:10:003
325928299107,1cyclictest0-21swapper/300:20:173
3259282991010,0cyclictest69450irq/121-eno123:44:293
3259282991010,0cyclictest69450irq/121-eno119:35:203
3259282991010,0cyclictest69450irq/121-eno100:00:423
3259282991010,0cyclictest0-21swapper/300:15:023
325928299100,9cyclictest69450irq/121-eno123:32:393
325928299100,9cyclictest69450irq/121-eno122:40:193
325928299100,9cyclictest69450irq/121-eno122:25:143
325928299100,9cyclictest69450irq/121-eno100:34:583
325928299100,9cyclictest0-21swapper/321:20:003
325928299100,8cyclictest0-21swapper/300:35:173
325928299100,1cyclictest0-21swapper/320:25:143
325928299100,10cyclictest0-21swapper/321:25:013
325928299100,10cyclictest0-21swapper/320:30:103
325928299100,0cyclictest0-21swapper/320:00:113
32592829999,0cyclictest69450irq/121-eno122:30:043
32592829999,0cyclictest69450irq/121-eno121:34:393
32592829999,0cyclictest69450irq/121-eno121:13:563
32592829999,0cyclictest69450irq/121-eno120:38:383
32592829999,0cyclictest69450irq/121-eno119:10:163
32592829999,0cyclictest0-21swapper/323:25:153
32592829999,0cyclictest0-21swapper/322:40:013
32592829999,0cyclictest0-21swapper/321:20:013
32592829999,0cyclictest0-21swapper/320:40:173
32592829999,0cyclictest0-21swapper/319:30:163
32592829999,0cyclictest0-21swapper/319:15:003
32592829990,8cyclictest69450irq/121-eno123:55:123
32592829990,8cyclictest69450irq/121-eno119:55:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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