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2025-11-21 - 15:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Fri Nov 21, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
279882991410,2cyclictest0-21swapper/312:10:133
279882991311,1cyclictest0-21swapper/311:05:133
27988299130,12cyclictest0-21swapper/311:00:143
279882991211,0cyclictest0-21swapper/309:50:113
27988299120,11cyclictest69450irq/121-eno111:17:363
27988299120,11cyclictest0-21swapper/309:45:123
27988299120,11cyclictest0-21swapper/307:25:093
27988299120,11cyclictest0-21swapper/307:10:003
27988299111,4cyclictest0-21swapper/307:40:153
279882991111,0cyclictest0-21swapper/312:15:193
279882991111,0cyclictest0-21swapper/311:50:013
279882991111,0cyclictest0-21swapper/311:10:103
279882991111,0cyclictest0-21swapper/308:35:193
279882991110,1cyclictest304469-21turbostat08:10:003
279882991110,0cyclictest0-21swapper/311:20:143
27988299110,11cyclictest0-21swapper/312:35:163
27988299110,11cyclictest0-21swapper/309:55:153
27988299110,10cyclictest0-21swapper/310:20:003
27988299110,10cyclictest0-21swapper/310:00:163
27988299110,10cyclictest0-21swapper/309:35:013
27988299110,10cyclictest0-21swapper/308:50:023
27988299110,10cyclictest0-21swapper/308:25:173
27988299110,0cyclictest0-21swapper/312:20:213
27988299110,0cyclictest0-21swapper/310:35:133
27988299110,0cyclictest0-21swapper/309:15:123
27988299110,0cyclictest0-21swapper/308:40:133
27988299110,0cyclictest0-21swapper/307:25:013
27988299109,0cyclictest69450irq/121-eno107:45:153
27988299108,1cyclictest0-21swapper/311:30:123
279882991010,0cyclictest69450irq/121-eno111:57:263
279882991010,0cyclictest69450irq/121-eno111:39:213
279882991010,0cyclictest69450irq/121-eno111:28:363
279882991010,0cyclictest69450irq/121-eno109:05:163
279882991010,0cyclictest0-21swapper/312:00:143
279882991010,0cyclictest0-21swapper/310:14:563
279882991010,0cyclictest0-21swapper/308:45:193
279882991010,0cyclictest0-21swapper/308:30:123
279882991010,0cyclictest0-21swapper/308:10:113
279882991010,0cyclictest0-21swapper/307:50:123
279882991010,0cyclictest0-21swapper/307:30:113
27988299100,9cyclictest69450irq/121-eno110:56:433
27988299100,9cyclictest69450irq/121-eno109:40:413
27988299100,9cyclictest69450irq/121-eno109:24:223
27988299100,9cyclictest69450irq/121-eno108:55:153
27988299100,0cyclictest0-21swapper/312:30:053
27988299100,0cyclictest0-21swapper/310:40:223
2798829999,0cyclictest69450irq/121-eno110:53:503
2798829999,0cyclictest69450irq/121-eno110:32:273
2798829999,0cyclictest69450irq/121-eno110:05:213
2798829999,0cyclictest69450irq/121-eno108:03:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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