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2025-12-01 - 17:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Mon Dec 01, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
407922899150,13cyclictest0-21swapper/310:50:123
4079228991211,0cyclictest0-21swapper/309:00:113
407922899120,1cyclictest0-21swapper/308:45:023
407922899120,11cyclictest0-21swapper/309:35:203
407922899120,11cyclictest0-21swapper/308:55:133
407922899120,0cyclictest0-21swapper/308:35:153
4079228991111,0cyclictest0-21swapper/312:00:123
4079228991111,0cyclictest0-21swapper/311:45:133
4079228991111,0cyclictest0-21swapper/311:40:143
4079228991110,1cyclictest69450irq/121-eno111:56:593
407922899110,9cyclictest69450irq/121-eno112:25:013
407922899110,11cyclictest0-21swapper/308:50:013
407922899110,11cyclictest0-21swapper/308:27:503
407922899110,10cyclictest69450irq/121-eno108:30:183
407922899110,10cyclictest0-21swapper/312:20:023
407922899110,10cyclictest0-21swapper/309:30:113
407922899110,0cyclictest0-21swapper/312:35:133
407922899110,0cyclictest0-21swapper/312:10:143
407922899110,0cyclictest0-21swapper/311:30:013
407922899110,0cyclictest0-21swapper/310:15:173
407922899109,1cyclictest69450irq/121-eno110:10:183
407922899109,0cyclictest69450irq/121-eno111:35:143
4079228991010,0cyclictest69450irq/121-eno112:05:173
4079228991010,0cyclictest69450irq/121-eno111:51:133
4079228991010,0cyclictest69450irq/121-eno110:55:163
4079228991010,0cyclictest69450irq/121-eno110:21:043
4079228991010,0cyclictest69450irq/121-eno110:06:043
4079228991010,0cyclictest0-21swapper/307:20:013
407922899100,9cyclictest69450irq/121-eno110:27:043
407922899100,9cyclictest69450irq/121-eno108:10:193
407922899100,10cyclictest0-21swapper/309:15:283
407922899100,0cyclictest0-21swapper/312:30:143
407922899100,0cyclictest0-21swapper/309:40:123
407922899100,0cyclictest0-21swapper/308:50:223
407922899100,0cyclictest0-21swapper/308:00:113
407922899100,0cyclictest0-21swapper/308:00:103
40792289999,0cyclictest69450irq/121-eno107:25:203
40792289999,0cyclictest69450irq/121-eno107:10:173
40792289999,0cyclictest0-21swapper/311:00:143
40792289999,0cyclictest0-21swapper/310:35:013
40792289999,0cyclictest0-21swapper/309:45:143
40792289999,0cyclictest0-21swapper/307:35:153
40792289991,6cyclictest69450irq/121-eno107:20:113
40792289990,8cyclictest69450irq/121-eno112:20:123
40792289990,8cyclictest69450irq/121-eno111:20:203
40792289990,8cyclictest69450irq/121-eno110:45:133
40792289990,8cyclictest0-21swapper/310:00:203
40792289990,8cyclictest0-21swapper/308:15:223
40792289990,0cyclictest0-21swapper/309:20:133
40792289988,0cyclictest69450irq/121-eno111:15:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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