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2026-08-29 - 12:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Sat Aug 29, 2026 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
302753599150,11cyclictest0-21swapper/321:25:013
302753599130,11cyclictest0-21swapper/323:40:123
302753599130,11cyclictest0-21swapper/300:00:003
302753599120,8cyclictest0-21swapper/319:45:003
302753599120,11cyclictest0-21swapper/322:30:123
302753599120,11cyclictest0-21swapper/322:15:163
302753599120,11cyclictest0-21swapper/300:25:203
302753599120,10cyclictest0-21swapper/323:15:133
302753599119,0cyclictest0-21swapper/323:20:013
3027535991110,1cyclictest0-21swapper/323:05:133
3027535991110,1cyclictest0-21swapper/319:50:123
3027535991110,0cyclictest0-21swapper/319:40:003
302753599110,8cyclictest0-21swapper/300:30:183
302753599110,10cyclictest3122716-21taskset23:02:523
302753599110,10cyclictest0-21swapper/321:55:143
302753599110,10cyclictest0-21swapper/321:25:183
302753599110,10cyclictest0-21swapper/320:35:173
302753599110,10cyclictest0-21swapper/320:10:003
302753599110,10cyclictest0-21swapper/320:00:003
302753599110,10cyclictest0-21swapper/319:10:163
302753599110,0cyclictest0-21swapper/323:45:173
302753599110,0cyclictest0-21swapper/322:10:113
302753599110,0cyclictest0-21swapper/321:45:013
302753599110,0cyclictest0-21swapper/320:00:013
302753599109,0cyclictest0-21swapper/322:25:133
302753599109,0cyclictest0-21swapper/300:10:133
3027535991010,0cyclictest0-21swapper/319:15:183
302753599100,0cyclictest0-21swapper/322:45:023
302753599100,0cyclictest0-21swapper/322:20:183
302753599100,0cyclictest0-21swapper/321:00:113
302753599100,0cyclictest0-21swapper/300:20:013
302753599100,0cyclictest0-21swapper/300:00:133
30275359999,0cyclictest0-21swapper/323:35:113
30275359999,0cyclictest0-21swapper/323:25:213
30275359999,0cyclictest0-21swapper/322:05:193
30275359999,0cyclictest0-21swapper/319:25:123
30275359998,0cyclictest0-21swapper/321:50:013
30275359998,0cyclictest0-21swapper/320:30:023
30275359997,1cyclictest0-21swapper/320:50:123
30275359988,0cyclictest0-21swapper/323:10:113
30275359988,0cyclictest0-21swapper/322:55:203
30275359988,0cyclictest0-21swapper/322:35:193
30275359986,2cyclictest3055012-21turbostat20:24:553
30275359980,3cyclictest0-21swapper/320:11:033
30275359977,0cyclictest0-21swapper/322:50:123
30275359977,0cyclictest0-21swapper/321:14:353
30275359977,0cyclictest0-21swapper/320:30:113
30275359976,1cyclictest0-21swapper/320:50:013
30275359975,1cyclictest0-21swapper/321:05:103
30275359974,1cyclictest0-21swapper/323:30:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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