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2025-12-04 - 20:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Thu Dec 04, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
416765699149,1cyclictest0-21swapper/308:20:133
4167656991311,1cyclictest0-21swapper/311:35:133
416765699130,12cyclictest0-21swapper/310:55:143
416765699130,11cyclictest0-21swapper/312:35:143
416765699129,1cyclictest0-21swapper/308:50:143
416765699120,1cyclictest0-21swapper/309:45:013
416765699120,11cyclictest0-21swapper/310:40:013
416765699120,11cyclictest0-21swapper/309:50:143
416765699120,11cyclictest0-21swapper/309:05:013
416765699120,10cyclictest0-21swapper/310:00:103
4167656991111,0cyclictest69450irq/121-eno110:15:193
4167656991111,0cyclictest0-21swapper/312:05:133
4167656991111,0cyclictest0-21swapper/311:25:003
4167656991110,0cyclictest0-21swapper/311:30:143
416765699110,10cyclictest69450irq/121-eno111:50:113
416765699110,10cyclictest69450irq/121-eno111:47:403
416765699110,10cyclictest69450irq/121-eno108:15:143
416765699110,10cyclictest0-21swapper/310:20:203
416765699110,0cyclictest0-21swapper/311:25:133
416765699110,0cyclictest0-21swapper/311:15:163
416765699110,0cyclictest0-21swapper/310:05:143
416765699110,0cyclictest0-21swapper/309:34:563
416765699110,0cyclictest0-21swapper/309:20:133
416765699110,0cyclictest0-21swapper/308:40:143
416765699110,0cyclictest0-21swapper/307:10:123
4167656991010,0cyclictest69450irq/121-eno112:00:163
4167656991010,0cyclictest69450irq/121-eno111:10:203
4167656991010,0cyclictest69450irq/121-eno110:45:193
4167656991010,0cyclictest69450irq/121-eno108:07:233
4167656991010,0cyclictest0-21swapper/312:20:133
4167656991010,0cyclictest0-21swapper/311:55:133
4167656991010,0cyclictest0-21swapper/310:50:183
4167656991010,0cyclictest0-21swapper/307:59:563
4167656991010,0cyclictest0-21swapper/307:25:193
416765699100,9cyclictest69450irq/121-eno112:15:583
416765699100,9cyclictest69450irq/121-eno109:15:353
416765699100,9cyclictest69450irq/121-eno109:05:233
416765699100,9cyclictest0-21swapper/309:45:383
416765699100,9cyclictest0-21swapper/309:35:143
416765699100,9cyclictest0-21swapper/308:10:123
416765699100,10cyclictest0-21swapper/309:10:193
416765699100,0cyclictest0-21swapper/307:40:033
41676569999,0cyclictest69450irq/121-eno112:33:073
41676569999,0cyclictest69450irq/121-eno112:25:223
41676569999,0cyclictest69450irq/121-eno111:41:013
41676569999,0cyclictest69450irq/121-eno110:12:123
41676569999,0cyclictest69450irq/121-eno109:55:213
41676569999,0cyclictest69450irq/121-eno109:25:183
41676569999,0cyclictest0-21swapper/308:40:013
41676569999,0cyclictest0-21swapper/308:25:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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