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2026-02-15 - 08:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Sun Feb 15, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2786240991310,1cyclictest0-21swapper/321:05:103
278624099130,12cyclictest0-21swapper/321:15:193
278624099130,11cyclictest0-21swapper/323:05:133
278624099129,1cyclictest0-21swapper/319:55:143
2786240991211,0cyclictest0-21swapper/322:35:133
278624099120,11cyclictest0-21swapper/321:25:133
278624099120,11cyclictest0-21swapper/320:30:113
278624099120,11cyclictest0-21swapper/319:35:123
278624099119,1cyclictest0-21swapper/323:55:143
2786240991110,0cyclictest0-21swapper/323:15:183
2786240991110,0cyclictest0-21swapper/322:05:133
2786240991110,0cyclictest0-21swapper/321:30:113
278624099110,1cyclictest0-21swapper/300:15:183
278624099110,10cyclictest0-21swapper/323:45:123
278624099110,10cyclictest0-21swapper/323:35:013
278624099109,0cyclictest0-21swapper/323:40:173
278624099109,0cyclictest0-21swapper/322:25:013
278624099109,0cyclictest0-21swapper/322:15:133
2786240991010,0cyclictest0-21swapper/320:15:123
2786240991010,0cyclictest0-21swapper/320:10:153
2786240991010,0cyclictest0-21swapper/319:45:173
2786240991010,0cyclictest0-21swapper/300:05:013
278624099100,0cyclictest0-21swapper/322:10:153
278624099100,0cyclictest0-21swapper/319:20:123
278624099100,0cyclictest0-21swapper/300:35:173
27862409999,0cyclictest0-21swapper/322:25:153
27862409999,0cyclictest0-21swapper/319:30:003
27862409998,0cyclictest0-21swapper/321:59:073
27862409998,0cyclictest0-21swapper/321:50:123
27862409997,1cyclictest29138352sleep300:20:133
27862409997,1cyclictest0-21swapper/320:35:123
27862409990,8cyclictest0-21swapper/323:20:133
27862409990,8cyclictest0-21swapper/321:45:013
27862409990,8cyclictest0-21swapper/319:30:173
27862409990,8cyclictest0-21swapper/319:15:193
27862409990,0cyclictest0-21swapper/321:45:183
27862409988,0cyclictest0-21swapper/321:20:123
27862409988,0cyclictest0-21swapper/320:45:123
27862409988,0cyclictest0-21swapper/320:05:173
27862409988,0cyclictest0-21swapper/300:25:183
27862409988,0cyclictest0-21swapper/300:11:593
27862409987,0cyclictest0-21swapper/322:40:113
27862409980,7cyclictest0-21swapper/322:55:233
27862409980,7cyclictest0-21swapper/300:05:133
27862409977,0cyclictest0-21swapper/323:12:053
27862409977,0cyclictest0-21swapper/319:15:013
27862409976,0cyclictest0-21swapper/320:25:193
2785372270,5sleep02785601-21grep19:05:190
2784230271,4sleep30-21swapper/319:05:013
14039870,3rtkit-daemon0-21swapper/219:06:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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