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2025-12-22 - 23:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Mon Dec 22, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243396999140,12cyclictest0-21swapper/307:50:133
2433969991211,0cyclictest0-21swapper/310:00:133
2433969991210,0cyclictest0-21swapper/311:15:133
243396999120,11cyclictest0-21swapper/311:55:133
243396999120,11cyclictest0-21swapper/311:10:143
243396999120,11cyclictest0-21swapper/310:35:123
243396999120,11cyclictest0-21swapper/309:30:133
243396999120,11cyclictest0-21swapper/309:20:133
243396999120,11cyclictest0-21swapper/309:00:183
2433969991111,0cyclictest0-21swapper/308:00:193
2433969991110,0cyclictest0-21swapper/312:20:113
2433969991110,0cyclictest0-21swapper/312:20:113
2433969991110,0cyclictest0-21swapper/310:05:133
243396999110,10cyclictest0-21swapper/310:40:193
243396999110,10cyclictest0-21swapper/307:12:253
243396999110,0cyclictest0-21swapper/308:50:003
243396999110,0cyclictest0-21swapper/308:30:133
243396999109,0cyclictest0-21swapper/312:15:133
243396999109,0cyclictest0-21swapper/311:05:203
243396999109,0cyclictest0-21swapper/307:25:013
2433969991010,0cyclictest0-21swapper/309:50:013
2433969991010,0cyclictest0-21swapper/309:15:123
2433969991010,0cyclictest0-21swapper/309:10:123
2433969991010,0cyclictest0-21swapper/307:40:123
243396999100,9cyclictest0-21swapper/310:55:013
243396999100,0cyclictest0-21swapper/310:45:133
243396999100,0cyclictest0-21swapper/307:50:013
24339699999,0cyclictest0-21swapper/312:35:153
24339699999,0cyclictest0-21swapper/311:50:413
24339699999,0cyclictest0-21swapper/309:55:153
24339699998,0cyclictest0-21swapper/311:45:143
24339699990,8cyclictest0-21swapper/307:25:173
24339699988,0cyclictest0-21swapper/312:25:133
24339699988,0cyclictest0-21swapper/311:00:133
24339699988,0cyclictest0-21swapper/310:15:123
24339699988,0cyclictest0-21swapper/310:10:123
24339699988,0cyclictest0-21swapper/308:59:593
24339699988,0cyclictest0-21swapper/308:15:013
24339699988,0cyclictest0-21swapper/307:30:133
24339699987,0cyclictest0-21swapper/311:35:143
24339699987,0cyclictest0-21swapper/310:55:003
24339699987,0cyclictest0-21swapper/310:20:163
24339699987,0cyclictest0-21swapper/308:45:173
24339699987,0cyclictest0-21swapper/308:20:143
24339699980,8cyclictest0-21swapper/311:30:013
24339699980,7cyclictest0-21swapper/308:40:193
2431613281,4sleep30-21swapper/307:05:013
24339699977,0cyclictest0-21swapper/312:00:203
24339699977,0cyclictest0-21swapper/310:30:123
24339699977,0cyclictest0-21swapper/310:29:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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