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2024-06-02 - 10:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Sun Jun 02, 2024 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
277392799148,5cyclictest0-21swapper/322:30:133
2773927991311,1cyclictest0-21swapper/300:30:163
277392799120,1cyclictest0-21swapper/320:35:103
277392799120,11cyclictest0-21swapper/322:45:103
277392799120,0cyclictest0-21swapper/323:25:233
2773927991111,0cyclictest0-21swapper/323:10:113
2773927991111,0cyclictest0-21swapper/320:15:103
2773927991111,0cyclictest0-21swapper/319:35:113
277392799110,8cyclictest0-21swapper/323:59:593
277392799110,11cyclictest0-21swapper/323:00:133
277392799110,11cyclictest0-21swapper/322:00:133
277392799110,11cyclictest0-21swapper/320:50:133
277392799110,11cyclictest0-21swapper/319:55:263
277392799110,11cyclictest0-21swapper/300:15:143
277392799110,11cyclictest0-21swapper/300:00:143
277392799110,10cyclictest0-21swapper/322:20:113
277392799110,0cyclictest0-21swapper/323:40:143
277392799110,0cyclictest0-21swapper/320:40:123
277392799109,0cyclictest0-21swapper/322:35:143
2773927991010,0cyclictest0-21swapper/322:55:003
2773927991010,0cyclictest0-21swapper/321:25:123
2773927991010,0cyclictest0-21swapper/319:30:123
277392799100,10cyclictest0-21swapper/321:45:173
277392799100,10cyclictest0-21swapper/320:35:013
277392799100,0cyclictest0-21swapper/319:15:123
277392799100,0cyclictest0-21swapper/300:35:253
27739279999,0cyclictest0-21swapper/323:50:023
27739279999,0cyclictest0-21swapper/322:55:263
27739279999,0cyclictest0-21swapper/321:30:553
27739279999,0cyclictest0-21swapper/321:05:123
27739279999,0cyclictest0-21swapper/321:05:113
27739279999,0cyclictest0-21swapper/320:05:003
27739279999,0cyclictest0-21swapper/319:25:183
27739279990,9cyclictest0-21swapper/323:15:113
27739279990,9cyclictest0-21swapper/319:40:243
27739279990,0cyclictest0-21swapper/321:35:233
27739279990,0cyclictest0-21swapper/320:10:133
27739279988,0cyclictest0-21swapper/323:35:143
27739279988,0cyclictest0-21swapper/321:45:013
27739279988,0cyclictest0-21swapper/321:25:013
27739279988,0cyclictest0-21swapper/319:50:003
27739279985,2cyclictest0-21swapper/322:40:133
2773076281,1sleep10-21swapper/119:05:251
27739279977,0cyclictest0-21swapper/323:30:113
27739279977,0cyclictest0-21swapper/322:25:493
27739279977,0cyclictest0-21swapper/321:55:143
27739279977,0cyclictest0-21swapper/321:55:013
27739279977,0cyclictest0-21swapper/320:25:133
27739279970,7cyclictest0-21swapper/319:55:013
27739279970,0cyclictest0-21swapper/321:15:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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