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2026-01-16 - 07:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Fri Jan 16, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1826143991811,5cyclictest0-21swapper/319:30:113
1826143991310,1cyclictest0-21swapper/322:50:123
182614399130,2cyclictest0-21swapper/319:25:123
182614399130,11cyclictest0-21swapper/321:20:133
182614399130,11cyclictest0-21swapper/320:25:113
182614399120,8cyclictest0-21swapper/322:45:133
182614399120,1cyclictest0-21swapper/320:55:123
182614399120,11cyclictest0-21swapper/322:35:133
182614399120,11cyclictest0-21swapper/300:00:193
18247512121,6sleep30-21swapper/319:05:153
1826143991111,0cyclictest0-21swapper/322:40:113
1826143991111,0cyclictest0-21swapper/321:30:023
1826143991111,0cyclictest0-21swapper/319:50:113
1826143991110,0cyclictest0-21swapper/323:50:123
1826143991110,0cyclictest0-21swapper/320:30:193
182614399110,10cyclictest0-21swapper/321:30:013
182614399110,10cyclictest0-21swapper/320:50:013
182614399110,10cyclictest0-21swapper/300:25:193
182614399110,0cyclictest0-21swapper/319:45:123
1826143991010,0cyclictest0-21swapper/323:55:133
1826143991010,0cyclictest0-21swapper/323:15:123
1826143991010,0cyclictest0-21swapper/322:35:013
1826143991010,0cyclictest0-21swapper/322:10:123
1826143991010,0cyclictest0-21swapper/321:55:133
1826143991010,0cyclictest0-21swapper/321:55:123
1826143991010,0cyclictest0-21swapper/320:40:133
1826143991010,0cyclictest0-21swapper/319:55:093
182614399100,9cyclictest0-21swapper/319:15:103
18261439999,0cyclictest0-21swapper/323:45:183
18261439999,0cyclictest0-21swapper/322:25:203
18261439999,0cyclictest0-21swapper/322:05:153
18261439999,0cyclictest0-21swapper/320:20:123
18261439998,0cyclictest0-21swapper/323:20:173
18261439998,0cyclictest0-21swapper/322:55:113
18261439998,0cyclictest0-21swapper/322:20:163
18261439998,0cyclictest0-21swapper/321:50:173
18261439990,8cyclictest0-21swapper/323:35:013
18261439990,8cyclictest0-21swapper/323:05:013
18261439990,8cyclictest0-21swapper/322:00:163
18261439990,8cyclictest0-21swapper/320:15:563
18261439990,0cyclictest0-21swapper/320:10:183
18261439988,0cyclictest0-21swapper/323:35:073
18261439988,0cyclictest0-21swapper/319:40:113
18261439988,0cyclictest0-21swapper/319:35:013
18261439988,0cyclictest0-21swapper/319:25:003
18261439987,0cyclictest0-21swapper/321:05:113
18261439977,0cyclictest0-21swapper/320:35:163
18261439977,0cyclictest0-21swapper/300:37:183
18261439977,0cyclictest0-21swapper/300:10:183
18261439976,0cyclictest0-21swapper/323:10:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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