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2026-04-30 - 19:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot3.osadl.org (updated Thu Apr 30, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
78699499130,1cyclictest0-21swapper/307:10:083
78699499130,11cyclictest0-21swapper/311:50:123
78699499130,11cyclictest0-21swapper/311:35:143
78699499130,11cyclictest0-21swapper/310:45:123
786994991210,2cyclictest0-21swapper/309:35:013
786994991210,1cyclictest0-21swapper/309:35:113
78699499120,1cyclictest0-21swapper/310:35:163
78699499120,1cyclictest0-21swapper/310:10:133
78699499120,1cyclictest0-21swapper/307:50:113
78699499120,11cyclictest0-21swapper/312:00:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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