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2026-06-17 - 03:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot3.osadl.org (updated Wed Jun 17, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4030226993630,362cyclictest40831942sleep321:24:563
4030226991312,0cyclictest0-21swapper/321:45:113
403022699130,12cyclictest0-21swapper/323:35:113
403022699130,11cyclictest0-21swapper/319:55:133
403022699120,8cyclictest0-21swapper/323:20:113
403022699120,11cyclictest0-21swapper/323:05:133
403022699120,11cyclictest0-21swapper/320:55:123
403022699120,11cyclictest0-21swapper/320:35:503
403022699120,11cyclictest0-21swapper/320:15:013
403022699120,11cyclictest0-21swapper/319:10:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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