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2026-05-01 - 23:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Fri May 01, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74949899121,0cyclictest0-21swapper/312:15:103
74949899120,11cyclictest0-21swapper/312:35:123
74949899120,11cyclictest0-21swapper/312:25:123
74949899120,11cyclictest0-21swapper/311:05:173
74949899120,11cyclictest0-21swapper/310:10:013
74949899120,11cyclictest0-21swapper/308:10:113
749498991111,0cyclictest0-21swapper/311:55:183
749498991111,0cyclictest0-21swapper/310:00:103
749498991110,0cyclictest0-21swapper/311:05:013
749498991110,0cyclictest0-21swapper/308:20:123
74949899110,10cyclictest0-21swapper/312:30:173
74949899110,10cyclictest0-21swapper/311:45:133
74949899110,10cyclictest0-21swapper/308:45:183
74949899110,10cyclictest0-21swapper/308:25:173
74949899110,0cyclictest0-21swapper/309:00:133
74949899109,0cyclictest0-21swapper/312:10:163
74949899109,0cyclictest0-21swapper/311:30:093
74949899109,0cyclictest0-21swapper/311:20:163
74949899109,0cyclictest0-21swapper/310:20:173
74949899109,0cyclictest0-21swapper/309:24:293
749498991010,0cyclictest0-21swapper/312:00:113
74949899100,9cyclictest0-21swapper/310:50:163
74949899100,8cyclictest0-21swapper/312:05:133
74949899100,0cyclictest0-21swapper/310:55:113
74949899100,0cyclictest0-21swapper/309:10:003
74949899100,0cyclictest0-21swapper/308:35:183
74949899100,0cyclictest0-21swapper/308:00:163
7494989999,0cyclictest0-21swapper/312:25:023
7494989999,0cyclictest0-21swapper/310:44:353
7494989999,0cyclictest0-21swapper/310:25:163
7494989999,0cyclictest0-21swapper/310:10:163
7494989999,0cyclictest0-21swapper/307:30:023
7494989999,0cyclictest0-21swapper/307:20:123
7494989999,0cyclictest0-21swapper/307:19:563
7494989998,0cyclictest0-21swapper/309:55:113
7494989998,0cyclictest0-21swapper/308:40:113
7494989997,1cyclictest0-21swapper/307:50:123
7494989988,0cyclictest0-21swapper/311:40:013
7494989988,0cyclictest0-21swapper/308:10:013
7494989980,0cyclictest0-21swapper/310:35:013
747710281,5sleep30-21swapper/307:05:123
7494989977,0cyclictest0-21swapper/309:45:123
7494989977,0cyclictest0-21swapper/309:40:163
7494989977,0cyclictest0-21swapper/309:27:093
7494989977,0cyclictest0-21swapper/308:50:133
7494989976,0cyclictest0-21swapper/309:50:103
7494989976,0cyclictest0-21swapper/309:35:123
7494989976,0cyclictest0-21swapper/309:30:133
7494989976,0cyclictest0-21swapper/309:10:173
7494989970,7cyclictest0-21swapper/307:30:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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