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2026-02-06 - 05:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Fri Feb 06, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
275688299140,12cyclictest0-21swapper/320:45:123
2756882991311,1cyclictest0-21swapper/300:10:153
275688299120,1cyclictest0-21swapper/322:40:123
275688299120,1cyclictest0-21swapper/321:45:133
275688299120,11cyclictest0-21swapper/321:25:183
275688299120,11cyclictest0-21swapper/319:45:003
275688299120,11cyclictest0-21swapper/319:20:123
275688299120,11cyclictest0-21swapper/300:20:223
275688299119,1cyclictest0-21swapper/322:15:153
2756882991111,0cyclictest0-21swapper/320:10:123
2756882991111,0cyclictest0-21swapper/319:45:133
275688299110,1cyclictest0-21swapper/323:50:113
275688299110,1cyclictest0-21swapper/321:20:223
275688299110,11cyclictest0-21swapper/321:50:183
275688299110,11cyclictest0-21swapper/319:15:003
275688299110,10cyclictest0-21swapper/323:40:223
275688299110,10cyclictest0-21swapper/323:35:173
275688299110,10cyclictest0-21swapper/322:25:183
275688299110,10cyclictest0-21swapper/321:30:183
275688299110,10cyclictest0-21swapper/320:50:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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