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2025-09-18 - 15:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Thu Sep 18, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112769991312,1cyclictest0-21swapper/308:05:143
11276999130,12cyclictest0-21swapper/307:36:003
11276999130,11cyclictest0-21swapper/310:05:163
11276999130,11cyclictest0-21swapper/310:00:123
11276999130,11cyclictest0-21swapper/308:45:143
11276999130,11cyclictest0-21swapper/308:25:093
112769991211,0cyclictest0-21swapper/307:50:013
112769991210,1cyclictest0-21swapper/310:30:133
11276999120,11cyclictest69450irq/121-eno109:30:283
11276999120,11cyclictest0-21swapper/312:20:013
11276999118,1cyclictest0-21swapper/307:25:173
112769991111,0cyclictest69450irq/121-eno112:09:363
112769991111,0cyclictest69450irq/121-eno111:46:353
112769991111,0cyclictest0-21swapper/311:40:013
112769991110,1cyclictest69450irq/121-eno108:39:553
112769991110,0cyclictest69450irq/121-eno111:50:203
112769991110,0cyclictest0-21swapper/312:30:173
112769991110,0cyclictest0-21swapper/312:25:143
112769991110,0cyclictest0-21swapper/309:55:133
11276999110,9cyclictest0-21swapper/309:00:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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