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2025-12-26 - 00:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Thu Dec 25, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28477572580,0sleep22847758-21unixbench_singl12:00:212
272776599140,12cyclictest0-21swapper/311:40:103
272776599130,12cyclictest0-21swapper/311:05:113
272776599130,11cyclictest0-21swapper/312:05:113
272776599130,11cyclictest0-21swapper/311:00:133
272776599130,11cyclictest0-21swapper/308:15:123
2727765991211,1cyclictest0-21swapper/309:40:123
2727765991211,0cyclictest0-21swapper/307:20:013
272776599120,1cyclictest0-21swapper/307:15:123
272776599120,11cyclictest0-21swapper/310:35:183
272776599120,11cyclictest0-21swapper/309:35:173
272776599120,11cyclictest0-21swapper/309:25:173
272776599120,11cyclictest0-21swapper/308:35:003
2727765991111,0cyclictest0-21swapper/310:21:303
2727765991111,0cyclictest0-21swapper/309:25:003
2727765991111,0cyclictest0-21swapper/308:05:183
2727765991110,0cyclictest0-21swapper/309:10:133
272776599110,11cyclictest0-21swapper/308:35:193
272776599110,10cyclictest0-21swapper/312:10:113
272776599110,10cyclictest0-21swapper/311:15:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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