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2026-03-08 - 06:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sun Mar 08, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1843015991611,4cyclictest0-21swapper/320:25:113
1843015991311,1cyclictest0-21swapper/320:35:113
184301599130,12cyclictest0-21swapper/319:55:123
184301599120,1cyclictest0-21swapper/320:10:123
184301599120,11cyclictest0-21swapper/323:55:183
184301599120,11cyclictest0-21swapper/322:30:133
184301599120,11cyclictest0-21swapper/321:00:133
184301599120,11cyclictest0-21swapper/319:20:133
1843015991111,0cyclictest0-21swapper/323:50:013
1843015991111,0cyclictest0-21swapper/322:20:163
1843015991110,0cyclictest0-21swapper/321:45:103
1843015991110,0cyclictest0-21swapper/320:45:003
1843015991110,0cyclictest0-21swapper/320:00:123
184301599110,11cyclictest0-21swapper/319:40:023
184301599110,10cyclictest0-21swapper/321:30:163
184301599110,10cyclictest0-21swapper/321:25:183
184301599110,10cyclictest0-21swapper/300:00:203
184301599110,0cyclictest0-21swapper/323:50:183
184301599110,0cyclictest0-21swapper/323:21:133
184301599110,0cyclictest0-21swapper/320:30:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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