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2026-06-06 - 07:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sat Jun 06, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1857562991711,5cyclictest0-21swapper/322:25:113
185756299130,12cyclictest0-21swapper/321:10:113
185756299130,11cyclictest0-21swapper/321:50:123
1857562991211,0cyclictest0-21swapper/322:50:133
1857562991210,1cyclictest0-21swapper/321:45:123
185756299120,1cyclictest0-21swapper/321:25:113
185756299120,1cyclictest0-21swapper/300:10:123
185756299120,11cyclictest0-21swapper/323:30:203
185756299120,11cyclictest0-21swapper/322:45:123
185756299120,11cyclictest0-21swapper/319:40:103
185756299120,11cyclictest0-21swapper/300:40:013
185756299120,10cyclictest0-21swapper/300:20:113
1857562991111,0cyclictest0-21swapper/300:15:183
1857562991110,0cyclictest0-21swapper/321:20:143
1857562991110,0cyclictest0-21swapper/319:55:173
185756299110,1cyclictest0-21swapper/319:45:213
185756299110,10cyclictest0-21swapper/322:30:193
185756299110,10cyclictest0-21swapper/320:25:003
185756299110,10cyclictest0-21swapper/300:25:183
185756299110,0cyclictest0-21swapper/322:55:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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