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2024-04-26 - 06:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Fri Apr 26, 2024 00:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4193162991312,1cyclictest0-21swapper/320:35:103
419316299130,12cyclictest0-21swapper/319:40:113
4193162991211,1cyclictest0-21swapper/322:15:123
419316299120,9cyclictest0-21swapper/323:20:123
419316299120,1cyclictest0-21swapper/320:25:003
419316299120,11cyclictest0-21swapper/319:55:103
4193162991111,0cyclictest0-21swapper/321:25:113
4193162991111,0cyclictest0-21swapper/300:05:113
4193162991110,1cyclictest0-21swapper/323:45:123
4193162991110,1cyclictest0-21swapper/300:35:123
419316299110,11cyclictest0-21swapper/319:30:243
419316299110,11cyclictest0-21swapper/319:25:133
419316299110,0cyclictest0-21swapper/323:10:123
419316299110,0cyclictest0-21swapper/321:00:193
419316299110,0cyclictest0-21swapper/320:05:133
4193162991010,0cyclictest0-21swapper/323:50:223
4193162991010,0cyclictest0-21swapper/323:05:233
4193162991010,0cyclictest0-21swapper/322:40:233
4193162991010,0cyclictest0-21swapper/320:10:113
419316299100,8cyclictest0-21swapper/319:45:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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