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2026-05-07 - 06:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Thu May 07, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231689699140,12cyclictest0-21swapper/319:55:113
231689699140,12cyclictest0-21swapper/300:10:113
231689699120,11cyclictest0-21swapper/322:50:123
231689699120,11cyclictest0-21swapper/320:50:163
231689699120,11cyclictest0-21swapper/319:20:003
2316896991111,0cyclictest0-21swapper/323:30:133
2316896991110,0cyclictest0-21swapper/322:20:103
2316896991110,0cyclictest0-21swapper/321:10:123
2316896991110,0cyclictest0-21swapper/300:15:123
231689699110,1cyclictest0-21swapper/319:35:113
231689699110,11cyclictest0-21swapper/321:05:183
231689699110,10cyclictest0-21swapper/323:55:013
231689699110,10cyclictest0-21swapper/323:10:163
231689699110,10cyclictest0-21swapper/321:55:013
231689699110,10cyclictest0-21swapper/321:29:563
231689699110,10cyclictest0-21swapper/320:15:403
231689699110,10cyclictest0-21swapper/300:35:203
231689699110,0cyclictest0-21swapper/320:49:523
231689699109,1cyclictest0-21swapper/320:25:123
231689699109,0cyclictest0-21swapper/322:40:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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