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2026-01-23 - 04:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Fri Jan 23, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
236203899130,11cyclictest0-21swapper/323:25:133
236203899130,11cyclictest0-21swapper/319:35:123
236203899130,11cyclictest0-21swapper/319:15:123
2362038991211,0cyclictest0-21swapper/321:35:123
2362038991210,0cyclictest0-21swapper/322:15:013
236203899120,11cyclictest0-21swapper/323:00:013
236203899120,11cyclictest0-21swapper/322:55:013
236203899120,11cyclictest0-21swapper/320:33:463
236203899119,1cyclictest0-21swapper/323:15:123
236203899119,1cyclictest0-21swapper/321:05:113
236203899119,1cyclictest0-21swapper/320:35:143
2362038991110,0cyclictest0-21swapper/321:25:153
2362038991110,0cyclictest0-21swapper/320:55:193
2362038991110,0cyclictest0-21swapper/319:20:113
236203899110,10cyclictest0-21swapper/323:05:013
236203899110,10cyclictest0-21swapper/322:40:173
236203899110,10cyclictest0-21swapper/321:55:183
236203899110,10cyclictest0-21swapper/319:45:013
236203899110,10cyclictest0-21swapper/300:40:013
236203899109,0cyclictest0-21swapper/323:20:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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