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2026-02-15 - 16:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Feb 15, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39012960,2sleep3574499cyclictest10:13:313
312782820,0sleep70-21swapper/710:53:247
536725726,18sleep20-21swapper/207:04:482
246362540,0sleep10-21swapper/112:04:221
94282530,1sleep19429-21bash09:58:321
314592510,0sleep6631rcuc/612:25:426
11392510,0sleep20-21swapper/208:52:492
556025025,9sleep40-21swapper/407:07:234
553425026,8sleep70-21swapper/707:07:027
320192500,0sleep70-21swapper/709:30:587
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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