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2026-08-09 - 22:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Aug 09, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
157192910,0sleep015718-21sshd11:25:300
280212700,1sleep428010-21sshd09:41:554
288522560,0sleep20-21swapper/211:55:112
225772540,0sleep20-21swapper/212:19:542
86702530,0sleep70-21swapper/710:38:447
951825249,1sleep40-21swapper/407:01:084
305562520,2sleep11174899cyclictest12:16:251
83762500,0sleep60-21swapper/610:38:436
255052490,3sleep2311rcuc/210:55:132
200592490,0sleep10-21swapper/109:08:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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