You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-24 - 00:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Feb 23, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53569912727,84cyclictest12745-21id09:19:281
5391998482,1cyclictest1116-21nfsd09:19:277
180762830,1sleep09-21ksoftirqd/010:51:200
5350997633,43cyclictest1114-21nfsd09:19:290
5379997430,43cyclictest0-21swapper/609:19:286
220552700,0sleep40-21swapper/410:55:174
513526136,9sleep70-21swapper/707:06:257
259342580,2sleep2536199cyclictest11:49:452
56712550,0sleep50-21swapper/509:43:185
537399520,51cyclictest10957-21kworker/4:409:19:284
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional