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2026-02-12 - 07:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Thu Feb 12, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
185619911462,52cyclictest0-21swapper/600:33:446
18564999998,1cyclictest15-21kswork00:33:447
1854999801,79cyclictest0-21swapper/400:33:454
26562730,0sleep40-21swapper/421:08:404
287002540,1sleep557-21ksoftirqd/522:30:105
1821325125,9sleep40-21swapper/419:05:094
177352510,0sleep4481ktimersoftd/422:44:194
137642510,0sleep40-21swapper/423:15:594
74862490,1sleep6492-21systemd-journal22:10:336
1812024926,8sleep50-21swapper/519:03:505
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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