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2026-02-09 - 16:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Feb 09, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1761321010,2sleep5670899cyclictest12:13:235
125252940,0sleep40-21swapper/409:23:514
125252940,0sleep40-21swapper/409:23:514
84332810,1sleep18432-21sshd11:30:421
215212680,1sleep121487-21cp11:50:451
306562580,0sleep40-21swapper/412:23:474
64672540,1sleep06430-21sshd10:56:210
156782540,2sleep7671899cyclictest09:24:027
156782540,2sleep7671899cyclictest09:24:027
42932530,2sleep2668699cyclictest11:30:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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