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2026-01-22 - 11:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Thu Jan 22, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
235162690,0sleep10-21swapper/123:25:511
163462590,2sleep0778399cyclictest23:51:450
22732540,1sleep2885-21polkitd23:03:262
82392510,1sleep48173-21sshd23:17:134
95802500,0sleep60-21swapper/600:19:466
257072500,2sleep0778399cyclictest22:53:390
200122480,0sleep60-21swapper/600:31:406
126172480,0sleep20-21swapper/222:41:232
757824725,8sleep10-21swapper/119:07:501
69222470,0sleep70-21swapper/721:57:237
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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