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2026-07-31 - 20:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Jul 31, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64522910,1sleep3571799cyclictest11:18:403
304562890,1sleep3571799cyclictest09:36:453
148952850,2sleep0569099cyclictest10:12:060
290942710,0sleep10-21swapper/110:49:071
82382660,0sleep50-21swapper/512:02:155
536225329,8sleep70-21swapper/707:03:557
48242510,1sleep10-21swapper/107:01:401
223042510,0sleep30-21swapper/312:33:533
189362510,0sleep60-21swapper/609:21:426
162752490,0sleep30-21swapper/310:17:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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