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2026-01-30 - 11:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Jan 30, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158509913617,73cyclictest13737-21bash22:31:103
80402890,0sleep00-21swapper/021:23:280
15874997737,26cyclictest0-21swapper/622:31:106
221912680,1sleep122169-21sshd22:58:361
88832670,0sleep40-21swapper/421:12:114
15372560,1sleep01536-21grep21:33:130
15844995116,17cyclictest0-21swapper/222:31:102
296692500,1sleep41585899cyclictest21:46:074
15858995049,1cyclictest15-21kswork22:31:114
1556225027,8sleep30-21swapper/319:06:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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