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2026-05-15 - 16:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri May 15, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2894699117116,0cyclictest0-21swapper/410:10:584
2894699116100,1cyclictest49-21ksoftirqd/410:58:584
168282960,2sleep12893399cyclictest11:30:241
28957998428,0cyclictest0-21swapper/510:58:585
2897199760,75cyclictest10763-21kworker/7:210:58:587
96722730,2sleep12893399cyclictest09:38:511
28940997065,4cyclictest4802-21cp10:10:572
2893399690,69cyclictest20499-21kworker/1:010:10:581
28964996628,37cyclictest0-21swapper/610:58:586
28964995755,1cyclictest0-21swapper/610:10:586
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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