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2026-02-17 - 05:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue Feb 17, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
193852970,0sleep70-21swapper/721:09:027
252092930,2sleep62689999cyclictest22:23:416
286412850,2sleep32687999cyclictest22:52:463
234462610,1sleep5784-21runrttasks23:01:535
200172590,0sleep10-21swapper/122:33:051
53302540,0sleep60-21swapper/621:53:546
326822530,1sleep732686-21df_abs22:52:587
129652520,0sleep00-21swapper/023:01:160
209192490,0sleep40-21swapper/421:56:484
121382490,0sleep70-21swapper/721:54:197
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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