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2026-01-23 - 03:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Jan 23, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
537221090,2sleep21650799cyclictest21:17:192
159332740,1sleep2784-21runrttasks23:52:412
291592540,5sleep70-21swapper/722:53:357
162312530,0sleep40-21swapper/422:47:084
238452520,1sleep323841-21sshd22:32:333
14312510,0sleep0111rcuc/023:25:320
68432490,0sleep06839-21sshd23:37:090
274482480,2sleep71652099cyclictest23:21:227
240552470,0sleep10-21swapper/121:58:271
222242470,2sleep71652099cyclictest23:04:087
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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