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2026-02-07 - 01:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Feb 06, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
394221030,2sleep03233199cyclictest10:45:380
292192940,2sleep63236699cyclictest09:54:516
289852750,2sleep73237099cyclictest11:53:217
273212670,0sleep30-21swapper/311:04:083
273212670,0sleep30-21swapper/311:04:083
23432570,1sleep22324-21sshd10:38:042
284832560,1sleep628478-21grepconf.sh10:02:356
4742550,0sleep40-21swapper/410:26:204
279742550,0sleep327972-21sshd11:26:503
302662540,0sleep10-21swapper/111:32:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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