You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-19 - 19:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Thu Feb 19, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26774991460,145cyclictest3771-21kworker/3:110:13:043
26782998651,1cyclictest691-21systemd-logind10:13:064
103382820,0sleep70-21swapper/710:41:187
325282800,2sleep62679699cyclictest12:15:206
26796997337,0cyclictest0-21swapper/610:13:056
26788995216,0cyclictest0-21swapper/510:13:065
234862510,0sleep60-21swapper/612:01:506
117902510,0sleep5551rcuc/511:05:275
30412500,0sleep50-21swapper/511:45:475
23252500,0sleep60-21swapper/612:34:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional