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2026-03-19 - 18:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Thu Mar 19, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
148469916116,82cyclictest11252-21grep11:16:434
148469915676,14cyclictest18751-21sshd12:20:134
148469912119,65cyclictest11541-21systemd11:16:444
190022760,0sleep70-21swapper/711:26:267
14860997449,0cyclictest0-21swapper/612:20:136
14860997421,33cyclictest11671-21systemd11:16:446
14860997231,40cyclictest0-21swapper/611:16:436
315572710,0sleep00-21swapper/009:50:410
146962710,0sleep00-21swapper/011:26:110
190012700,0sleep20-21swapper/210:32:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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