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2026-01-25 - 11:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Jan 25, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
449099107104,2cyclictest1116-21nfsd22:31:177
68472970,1sleep5723-21in:imjournal22:23:185
15322880,1sleep56343-21kworker/u16:323:40:325
321482860,1sleep732143-21sshd23:08:147
154402770,0sleep60-21swapper/621:53:166
109282740,0sleep51-21systemd00:14:435
4435996433,31cyclictest0-21swapper/022:31:170
4448996160,1cyclictest1-21systemd22:31:172
269172560,0sleep2784-21runrttasks21:19:322
269172560,0sleep2784-21runrttasks21:19:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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