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2026-02-14 - 21:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Feb 14, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
235679912554,51cyclictest5478-21systemd11:10:127
3012621090,1sleep130119-21grepconf.sh11:29:041
2352299106104,1cyclictest1116-21nfsd11:10:111
93352790,2sleep79307-21cp09:32:257
23559997445,28cyclictest5678-21sshd11:10:126
189422730,0sleep6631rcuc/609:23:196
325672700,0sleep60-21swapper/609:39:296
31252650,13sleep687950irq/25-em1-rx-011:37:186
23514996312,0cyclictest0-21swapper/011:10:120
138162560,0sleep10-21swapper/110:41:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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