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2026-02-18 - 18:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Feb 18, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243112730,0sleep70-21swapper/712:06:177
101162720,0sleep70-21swapper/710:49:447
262342660,0sleep00-21swapper/011:11:160
281772600,1sleep028152-21cp12:17:550
61282540,2sleep0800399cyclictest10:40:080
34022540,0sleep70-21swapper/710:41:517
129202530,0sleep40-21swapper/412:05:344
538625229,9sleep70-21swapper/707:02:507
781125126,9sleep20-21swapper/207:07:022
773825127,9sleep50-21swapper/507:06:005
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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