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2026-02-17 - 17:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue Feb 17, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
220722760,0sleep30-21swapper/310:11:473
266892750,0sleep4471rcuc/411:33:104
157442680,0sleep5551rcuc/511:06:445
1562025629,9sleep40-21swapper/407:06:354
81492530,0sleep00-21swapper/012:05:260
81492530,0sleep00-21swapper/012:05:260
1567625026,8sleep00-21swapper/007:07:190
25722480,0sleep50-21swapper/512:20:285
1544524825,9sleep50-21swapper/507:04:115
143332480,0sleep0101ktimersoftd/010:36:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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