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2025-06-29 - 00:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Jun 28, 2025 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325321020,0sleep10-21swapper/111:17:281
300772580,0sleep70-21swapper/711:23:037
139952510,0sleep20-21swapper/211:03:442
1932324924,8sleep40-21swapper/406:58:424
122482490,0sleep00-21swapper/012:22:060
1930724725,4sleep60-21swapper/606:58:286
295052460,0sleep00-21swapper/010:43:230
1931724621,9sleep70-21swapper/706:58:377
87322450,0sleep30-21swapper/311:44:533
56062450,0sleep50-21swapper/510:50:255
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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