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2026-01-26 - 11:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Jan 26, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13172980,0sleep00-21swapper/023:09:490
53002960,2sleep52954799cyclictest21:30:385
258142900,0sleep525813-21systemd-cgroups21:28:065
90992880,0sleep50-21swapper/522:18:445
104972520,0sleep4481ktimersoftd/421:17:244
301102510,0sleep530107-21sshd00:08:575
77682500,1sleep07767-21grepconf.sh21:32:500
323632490,0sleep70-21swapper/700:09:077
232432480,1sleep7686-21dbus-daemon23:40:007
101832480,0sleep20-21swapper/200:33:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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