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2026-03-09 - 04:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Mar 09, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
277032780,1sleep51-21systemd22:21:185
271742550,0sleep10-21swapper/122:43:011
140832520,1sleep114082-21grep21:33:091
140832520,1sleep114082-21grep21:33:091
301902500,1sleep4821399cyclictest22:41:284
225752500,2sleep0818899cyclictest22:51:570
291502490,0sleep50-21swapper/522:59:315
28932490,0sleep50-21swapper/521:14:235
84912480,1sleep08494-21kworker/u16:222:45:400
257082480,0sleep00-21swapper/021:48:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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