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2026-02-22 - 20:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Feb 22, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
250452740,0sleep40-21swapper/409:41:194
125862720,0sleep10-21swapper/112:14:131
236232530,0sleep70-21swapper/709:41:147
208302530,0sleep20-21swapper/210:32:512
124312510,0sleep20-21swapper/211:20:322
34752500,0sleep00-21swapper/012:04:270
2253825027,8sleep10-21swapper/107:07:261
323862490,0sleep70-21swapper/709:17:437
201842490,0sleep10-21swapper/111:00:371
89192470,0sleep00-21swapper/009:36:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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