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2026-02-24 - 13:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue Feb 24, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2980721170,3sleep41357199cyclictest12:05:394
121632930,1sleep30-21swapper/307:02:503
189072830,2sleep21355599cyclictest11:46:392
10902560,0sleep20-21swapper/211:27:252
195102530,0sleep10-21swapper/109:20:531
99522510,0sleep50-21swapper/509:32:585
281092500,1sleep428064-21sshd10:52:264
169712500,0sleep716965-21sshd12:36:097
195032490,0sleep00-21swapper/012:36:190
112252490,0sleep70-21swapper/712:24:487
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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