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2026-04-12 - 19:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Apr 12, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
653421010,0sleep70-21swapper/710:57:487
73332910,1sleep11-21systemd10:50:291
275352690,1sleep527536-21grep10:10:455
308612590,1sleep730813-21sshd10:40:427
91652550,1sleep39168-21fschecks_count10:56:083
40892550,0sleep30-21swapper/311:27:243
121262550,0sleep712102-21sshd12:23:507
9162520,0sleep7910-21sshd09:43:087
261772500,0sleep00-21swapper/009:18:340
224502480,0sleep50-21swapper/511:09:565
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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