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2026-01-18 - 07:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Jan 18, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
236121240,0sleep60-21swapper/622:57:576
261002730,0sleep5551rcuc/523:55:555
1735727228,18sleep70-21swapper/719:08:247
77512580,2sleep41754399cyclictest22:51:144
237612570,0sleep60-21swapper/600:12:296
177092530,1sleep217706-21systemd-cgroups00:07:212
137292510,1sleep613728-21systemd-cgroups21:53:026
68642500,0sleep56851-21sshd23:33:285
225702500,0sleep322567-21sshd21:16:313
1714225026,9sleep10-21swapper/119:05:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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