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2026-05-10 - 12:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun May 10, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4602960,0sleep60-21swapper/621:35:506
3722960,0sleep4471rcuc/423:00:144
148612780,1sleep42192499cyclictest21:44:374
150962760,0sleep10-21swapper/123:13:241
310582710,1sleep1758-21runrttasks21:09:341
310582710,1sleep1758-21runrttasks21:09:341
194712710,0sleep30-21swapper/323:41:133
15232700,0sleep00-21swapper/000:31:560
248512690,0sleep10-21swapper/121:41:221
143362540,0sleep10-21swapper/100:26:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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