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2026-04-20 - 01:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Apr 19, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
248682990,1sleep424862-21sshd11:36:504
62042810,2sleep73142599cyclictest09:26:467
237932750,0sleep00-21swapper/011:08:430
274092730,2sleep03139699cyclictest11:48:150
143292680,1sleep014331-21pmu-power08:26:010
147822530,0sleep20-21swapper/211:04:282
278472500,0sleep10-21swapper/110:44:411
51552490,0sleep20-21swapper/212:11:162
3121424937,8sleep30-21swapper/307:05:013
3121424937,8sleep30-21swapper/307:05:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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