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2026-02-25 - 14:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Feb 25, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
85569912099,16cyclictest41-21ksoftirqd/311:48:143
269072930,1sleep6641ktimersoftd/612:04:596
132162820,0sleep40-21swapper/410:32:064
8535998177,2cyclictest24329-21cp11:48:140
8577996910,28cyclictest1-21systemd11:48:146
98842590,1sleep4784-21runrttasks10:08:034
325032590,0sleep50-21swapper/509:43:455
325032590,0sleep50-21swapper/509:43:455
97332560,2sleep6857799cyclictest10:52:106
299172540,0sleep60-21swapper/612:36:316
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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