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2026-04-21 - 02:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue Apr 21, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1906721030,0sleep10-21swapper/122:30:311
26852740,0sleep00-21swapper/000:10:160
159402710,2sleep72136799cyclictest00:25:207
324262560,0sleep30-21swapper/322:47:303
272342540,0sleep10-21swapper/123:51:511
150762530,0sleep20-21swapper/222:32:082
35672500,0sleep50-21swapper/523:34:255
236952500,0sleep60-21swapper/623:21:056
59662490,0sleep45968-21kworker/u16:423:56:024
252452480,0sleep30-21swapper/322:00:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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