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2026-02-07 - 15:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Feb 07, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
301432850,2sleep72977899cyclictest12:30:197
177812690,0sleep70-21swapper/712:19:547
147532530,1sleep314752-21bash11:41:213
192992510,0sleep20-21swapper/212:08:352
138932510,1sleep413895-21grepconf.sh09:51:264
131062510,0sleep50-21swapper/509:14:505
2936025027,8sleep20-21swapper/207:05:402
4542490,8sleep188250irq/28-em2-rx-010:33:031
279662490,1sleep627965-21grep10:46:226
229862490,1sleep233-21ksoftirqd/210:59:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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