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2026-05-03 - 19:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun May 03, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
59939914547,75cyclictest0-21swapper/510:39:235
59939914127,54cyclictest0-21swapper/510:46:555
595099913,87cyclictest0-21swapper/010:46:550
6001997715,53cyclictest0-21swapper/610:39:236
6001997543,32cyclictest0-21swapper/610:46:556
126562710,0sleep30-21swapper/310:41:463
5950996219,0cyclictest0-21swapper/010:39:230
61012540,2sleep1595899cyclictest09:19:101
563825446,5sleep50-21swapper/507:07:115
115052530,2sleep6600199cyclictest10:39:486
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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