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2026-05-20 - 21:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed May 20, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
671621030,2sleep01629899cyclictest11:57:300
156212980,0sleep40-21swapper/412:24:014
145502900,2sleep70-21swapper/707:04:107
272382890,0sleep40-21swapper/412:22:494
54732810,2sleep61632199cyclictest10:26:296
54732810,2sleep61632199cyclictest10:26:296
111172720,0sleep10-21swapper/110:02:461
168842710,1sleep616816-21sshd09:24:066
41022700,0sleep30-21swapper/311:20:093
162072530,1sleep71632799cyclictest08:04:087
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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