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2026-02-02 - 22:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Feb 02, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
199779916726,86cyclictest20608-21sshd10:48:590
199779915431,45cyclictest1-21systemd09:35:420
19977991537,124cyclictest31125-21bash12:07:000
3244621110,2sleep41999999cyclictest09:20:524
50692990,1sleep21998699cyclictest10:03:272
20003999553,41cyclictest20205-21sshd10:48:595
181602860,1sleep773-21ksoftirqd/710:25:347
104502770,2sleep11997999cyclictest11:42:331
220282690,0sleep30-21swapper/311:39:153
2001299660,65cyclictest26882-21sshd09:35:417
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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