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2026-05-25 - 00:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun May 24, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
187402870,0sleep00-21swapper/011:42:560
237802770,1sleep723763-21bash10:09:567
124362760,1sleep5721-21dbus-daemon11:57:105
312692720,0sleep30-21swapper/311:05:103
1441725928,18sleep70-21swapper/707:08:037
99322510,0sleep20-21swapper/209:52:452
266622510,0sleep20-21swapper/211:37:532
283092500,2sleep61468399cyclictest09:40:566
74502480,1sleep17410-21sshd10:34:331
74502480,1sleep17410-21sshd10:34:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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