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2026-03-28 - 23:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Mar 28, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22503991420,141cyclictest28503-21kworker/0:409:24:290
2251799133118,1cyclictest73-21ksoftirqd/709:24:307
2250499107105,1cyclictest1116-21nfsd09:24:291
1574021060,0sleep00-21swapper/009:34:120
2251599840,83cyclictest930-21kworker/u16:409:24:305
287802810,1sleep6686-21dbus-daemon12:35:116
232412800,0sleep00-21swapper/009:31:000
22516996933,36cyclictest0-21swapper/609:24:306
311012550,0sleep40-21swapper/410:56:424
252062520,0sleep20-21swapper/209:43:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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