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2026-03-02 - 01:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Mar 02, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
154789916846,74cyclictest0-21swapper/021:37:380
1531121240,2sleep40-21swapper/419:07:204
1548399850,84cyclictest31958-21kworker/2:321:37:392
15487997647,29cyclictest0-21swapper/621:37:386
203322690,0sleep00-21swapper/021:33:380
117962660,0sleep40-21swapper/421:36:544
187192560,2sleep51548699cyclictest22:36:305
1500525442,8sleep50-21swapper/519:03:215
118652530,2sleep71548899cyclictest21:14:477
53042520,0sleep75277-21sshd22:13:267
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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