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2025-12-16 - 12:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue Dec 16, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
149302810,0sleep70-21swapper/723:20:377
219082510,4sleep7132599cyclictest21:30:097
96324736,8sleep50-21swapper/519:08:515
52982460,0sleep40-21swapper/421:14:444
316292440,1sleep331626-21systemd23:43:153
149422430,0sleep50-21swapper/521:41:125
96524230,9sleep70-21swapper/719:08:537
246392420,1sleep5686-21dbus-daemon00:27:225
185022420,0sleep60-21swapper/623:21:246
10402410,0sleep60-21swapper/600:16:256
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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