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2026-03-29 - 19:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Mar 29, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18719998644,41cyclictest17686-21systemd11:41:086
32562700,1sleep341-21ksoftirqd/309:32:043
174552670,0sleep1121rcu_preempt09:42:271
204442660,0sleep30-21swapper/312:03:493
18703995554,1cyclictest15-21kswork11:41:084
98602540,0sleep39852-21sshd11:53:483
215432540,0sleep50-21swapper/509:33:105
86202510,0sleep40-21swapper/411:12:164
236212490,0sleep50-21swapper/509:16:205
236212490,0sleep50-21swapper/509:16:205
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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