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2026-01-24 - 23:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Jan 24, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
212009913752,48cyclictest21862-21systemd11:40:161
212009912051,29cyclictest0-21swapper/109:17:251
521021030,2sleep62120599cyclictest10:55:086
21207999593,1cyclictest1115-21nfsd09:17:247
21205999150,0cyclictest0-21swapper/609:17:256
2120299770,76cyclictest7346-21kworker/u16:511:40:163
21205996919,23cyclictest21726-21bash11:40:156
80452640,1sleep28041-21systemd11:16:262
8382540,2sleep32120299cyclictest09:59:063
26532510,0sleep12461-21sshd09:38:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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