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2026-04-27 - 11:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Apr 27, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28769991070,106cyclictest2033-21kworker/7:322:44:487
60882910,0sleep26089-21sshd23:37:492
58182650,0sleep00-21swapper/023:20:170
28726996143,0cyclictest0-21swapper/022:44:490
2873899590,46cyclictest10912-21kworker/2:022:44:482
28764995822,35cyclictest17029-21sshd22:44:486
44002550,0sleep30-21swapper/323:39:423
180502540,0sleep60-21swapper/600:15:176
2835325125,9sleep40-21swapper/419:06:274
304922500,1sleep6721-21dbus-daemon21:36:516
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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