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2026-01-28 - 21:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Jan 28, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24712810,2sleep2546499cyclictest10:33:052
284412760,1sleep428437-21systemd10:38:364
14452640,1sleep41447-21bash11:42:034
201772520,0sleep30-21swapper/311:35:213
514925027,8sleep20-21swapper/207:06:372
316112490,0sleep6641ktimersoftd/612:35:236
171902490,1sleep233-21ksoftirqd/211:48:502
22852480,1sleep12288-21grepconf.sh12:14:441
155412480,1sleep715544-21bash09:28:317
145412480,0sleep70-21swapper/712:34:207
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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