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2026-05-21 - 22:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Thu May 21, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39122600,1sleep11-21systemd11:08:101
55462590,0sleep60-21swapper/611:13:446
2874525442,8sleep70-21swapper/707:08:257
191852510,1sleep11-21systemd10:14:121
2866225027,8sleep00-21swapper/007:07:130
2852325037,9sleep40-21swapper/407:05:174
2849224825,8sleep50-21swapper/507:04:545
127642480,0sleep30-21swapper/310:28:323
111292480,0sleep10-21swapper/112:32:521
111292480,0sleep10-21swapper/112:32:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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