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2026-01-31 - 00:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Jan 30, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1310499118118,0cyclictest0-21swapper/009:20:150
76782990,2sleep51310999cyclictest10:23:065
13105999595,0cyclictest25-21ksoftirqd/109:15:461
13105998873,1cyclictest25-21ksoftirqd/109:20:141
275402840,0sleep0111rcuc/009:34:160
1311199740,73cyclictest1543-21sshd09:15:467
178202730,0sleep40-21swapper/410:31:384
135052700,0sleep10-21swapper/111:35:271
70202680,0sleep00-21swapper/010:05:310
1310499680,67cyclictest16816-21kworker/0:109:15:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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