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2026-01-23 - 23:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Jan 23, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3147499160116,42cyclictest73-21ksoftirqd/712:25:087
314749911192,19cyclictest73-21ksoftirqd/712:21:517
31473997918,61cyclictest0-21swapper/612:25:516
160192780,1sleep73147499cyclictest10:27:077
108262760,1sleep03144299cyclictest11:35:320
31473997353,20cyclictest0-21swapper/612:21:546
25802710,0sleep30-21swapper/311:42:483
3146999580,58cyclictest6969-21kworker/4:112:24:224
3144299580,57cyclictest24206-21kworker/u16:112:22:060
31451995538,17cyclictest13550irq/24-ahci[00012:21:542
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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