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2026-04-26 - 21:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Apr 26, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
290982700,0sleep70-21swapper/712:07:587
295462560,2sleep51579699cyclictest11:30:085
6252530,0sleep70-21swapper/710:20:427
162972530,0sleep00-21swapper/011:39:000
255092510,0sleep20-21swapper/211:22:282
309352500,0sleep40-21swapper/412:27:024
207202500,1sleep1758-21runrttasks09:15:561
205242500,1sleep220500-21sshd12:13:142
1534125027,8sleep00-21swapper/007:06:000
324912490,0sleep00-21swapper/009:35:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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