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2026-01-10 - 02:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Jan 10, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2717199114113,1cyclictest1116-21nfsd22:21:023
27197999070,1cyclictest65-21ksoftirqd/622:21:036
192072830,1sleep3686-21dbus-daemon22:29:223
2719099700,70cyclictest0-21swapper/522:21:045
2715799650,64cyclictest4448-21kworker/1:222:21:021
173972580,2sleep12715799cyclictest23:06:531
134452560,2sleep62719799cyclictest22:26:456
273432510,1sleep449-21ksoftirqd/423:30:264
141962510,0sleep30-21swapper/323:15:443
252632500,2sleep42718299cyclictest22:11:214
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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