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2026-05-06 - 11:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed May 06, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13191991239,55cyclictest29298-21kworker/u16:422:06:351
13205999048,42cyclictest0-21swapper/622:06:346
17592790,1sleep6721-21dbus-daemon21:48:586
316212700,1sleep231616-21systemd23:53:242
289322690,1sleep61320599cyclictest22:34:316
82172530,0sleep40-21swapper/422:48:474
112032530,0sleep30-21swapper/300:24:493
13203995228,0cyclictest0-21swapper/422:06:344
89662510,0sleep10-21swapper/121:55:091
325362510,0sleep50-21swapper/523:26:365
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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