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2025-11-19 - 21:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Nov 19, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2630925625,8sleep00-21swapper/006:50:490
253752560,0sleep10-21swapper/109:49:301
2654325428,9sleep40-21swapper/406:53:574
2505624825,18sleep30-21swapper/306:49:483
135572470,0sleep30-21swapper/310:22:323
208872450,0sleep00-21swapper/011:02:330
309132440,0sleep50-21swapper/511:58:205
60632430,0sleep10-21swapper/110:45:121
269152430,0sleep30-21swapper/309:54:453
224762420,0sleep30-21swapper/310:42:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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