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2026-02-18 - 02:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Feb 18, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81532930,2sleep3878399cyclictest00:17:193
81532930,2sleep3878399cyclictest00:17:193
8785997239,32cyclictest22202-21systemd-cgroups22:38:414
154472680,0sleep00-21swapper/021:58:200
8794995113,37cyclictest22043-21grepconf.sh22:38:406
295422510,0sleep70-21swapper/722:46:407
252462510,8sleep557-21ksoftirqd/522:52:075
157382510,0sleep70-21swapper/723:14:207
97422500,0sleep10-21swapper/123:15:581
66352500,1sleep76631-21sshd21:48:187
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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