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2026-02-10 - 05:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue Feb 10, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21662550,1sleep12164-21sshd22:35:311
75262540,1sleep37527-21grepconf.sh23:45:573
65712540,1sleep5561ktimersoftd/522:47:045
4812530,1sleep6885-21polkitd23:41:446
111022520,2sleep32611099cyclictest23:38:203
80972510,0sleep20-21swapper/221:35:332
115282500,0sleep70-21swapper/721:13:127
226372490,0sleep1686-21dbus-daemon22:40:281
230762470,0sleep70-21swapper/723:43:057
224122460,0sleep30-21swapper/323:35:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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