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2026-05-13 - 14:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed May 13, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1587699131129,1cyclictest1842-21nfsd10:02:505
171402910,0sleep50-21swapper/509:39:555
15886998732,22cyclictest721-21dbus-daemon10:02:527
218732770,0sleep70-21swapper/710:12:257
170762770,2sleep61588299cyclictest10:56:056
181412750,1sleep418140-21kworker/u16:010:54:104
1586999630,62cyclictest20039-21kworker/4:110:02:514
278752590,1sleep027871-21grepconf.sh09:46:150
321122540,0sleep0721-21dbus-daemon10:26:270
321122540,0sleep0721-21dbus-daemon10:26:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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