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2026-02-08 - 03:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Feb 08, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
93299913052,39cyclictest885-21polkitd00:05:512
293172880,0sleep10-21swapper/122:33:151
30292850,0sleep10-21swapper/122:02:081
931599578,48cyclictest8639-21sshd00:05:500
152562560,0sleep40-21swapper/421:43:294
9366995552,2cyclictest1-21systemd00:05:517
241732540,1sleep124149-21cp22:09:131
139302520,2sleep3933699cyclictest23:07:373
935299500,16cyclictest0-21swapper/500:05:515
291052500,1sleep41-21systemd22:31:104
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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