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2026-02-15 - 08:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Feb 15, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
92712770,0sleep00-21swapper/000:30:280
211862740,0sleep00-21swapper/023:05:140
302262680,0sleep40-21swapper/423:28:334
134442620,0sleep60-21swapper/600:21:056
136825331,18sleep40-21swapper/419:03:024
90732520,0sleep20-21swapper/200:03:392
54982500,0sleep60-21swapper/600:35:556
296042490,0sleep10-21swapper/122:16:461
176272490,0sleep1241ktimersoftd/122:46:091
163172480,0sleep60-21swapper/623:20:266
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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