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2026-08-12 - 22:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Aug 12, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
279782840,0sleep30-21swapper/312:01:223
233552830,1sleep1460299cyclictest10:43:431
46472780,0sleep20-21swapper/209:17:422
109142760,0sleep2321ktimersoftd/212:11:302
294062680,0sleep70-21swapper/710:22:197
322342550,2sleep0459499cyclictest10:04:250
326242530,10sleep213550irq/24-ahci[00010:42:242
213392510,0sleep60-21swapper/609:28:196
43032500,0sleep4721-21dbus-daemon09:55:404
424325038,9sleep70-21swapper/707:02:567
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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