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2026-02-09 - 04:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Feb 09, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16413997776,1cyclictest41-21ksoftirqd/322:09:033
69672750,0sleep20-21swapper/223:17:472
16417996815,33cyclictest57-21ksoftirqd/522:09:035
16423996526,0cyclictest0-21swapper/622:09:036
41342550,1sleep54117-21sshd22:58:125
176132550,3sleep0686-21dbus-daemon21:25:160
183122500,0sleep60-21swapper/600:33:206
1613424925,9sleep70-21swapper/719:06:077
117542490,0sleep70-21swapper/723:38:427
299412480,1sleep41-21systemd23:34:074
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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