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2026-04-18 - 23:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Apr 18, 2026 12:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1614321000,0sleep30-21swapper/310:59:583
80692940,0sleep40-21swapper/412:21:134
21922780,1sleep7686-21dbus-daemon10:57:147
221892690,2sleep2587199cyclictest09:06:242
5877996653,8cyclictest65-21ksoftirqd/611:08:066
5883996032,0cyclictest0-21swapper/711:08:067
5865995756,1cyclictest25-21ksoftirqd/111:08:061
586499540,53cyclictest9397-21kworker/0:111:08:050
227732530,0sleep6641ktimersoftd/611:48:396
572825228,8sleep70-21swapper/707:05:317
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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