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2026-02-01 - 22:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Feb 01, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205222860,2sleep62148599cyclictest10:15:286
157132700,1sleep773-21ksoftirqd/712:36:507
105582610,16sleep687950irq/25-em1-rx-010:03:196
105582610,16sleep687950irq/25-em1-rx-010:03:196
2113225725,17sleep70-21swapper/707:06:157
224312520,1sleep622432-21grep11:36:506
135582510,0sleep1241ktimersoftd/110:42:061
273802500,0sleep40-21swapper/410:31:284
268782500,0sleep00-21swapper/011:29:230
234292500,0sleep40-21swapper/410:25:114
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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