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2026-01-13 - 03:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue Jan 13, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
960221040,0sleep30-21swapper/300:03:283
248952680,0sleep20-21swapper/223:50:372
55232490,0sleep65522-21systemd-cgroups23:25:346
1409724926,8sleep60-21swapper/619:05:166
70992480,0sleep50-21swapper/521:32:015
57292470,0sleep70-21swapper/700:36:157
224042460,0sleep00-21swapper/022:00:470
53882450,0sleep60-21swapper/621:48:116
307272450,1sleep430721-21sshd22:01:234
281902450,0sleep00-21swapper/000:16:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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