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2026-02-08 - 15:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Feb 08, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201222980,0sleep10-21swapper/110:23:131
235822860,0sleep423581-21sshd10:31:094
309962730,0sleep60-21swapper/611:55:046
185102550,0sleep70-21swapper/710:46:257
78232510,2sleep51506899cyclictest09:41:285
78232510,2sleep51506899cyclictest09:41:285
302772510,1sleep125-21ksoftirqd/111:49:071
1462425126,8sleep40-21swapper/407:04:254
240572500,1sleep424054-21bash12:00:394
194972500,0sleep50-21swapper/509:08:045
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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