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2025-11-30 - 01:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Nov 30, 2025 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
402225327,8sleep40-21swapper/418:51:344
414125127,8sleep30-21swapper/318:53:093
94402500,0sleep00-21swapper/022:44:240
94402500,0sleep00-21swapper/022:44:240
271612500,0sleep30-21swapper/322:47:073
271612500,0sleep30-21swapper/322:47:073
420824924,8sleep10-21swapper/118:54:031
41982490,0sleep70-21swapper/723:11:467
222782460,0sleep00-21swapper/021:20:150
10742460,0sleep00-21swapper/022:38:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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