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2026-05-18 - 18:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon May 18, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
709321010,0sleep70-21swapper/711:23:237
76902880,2sleep02784299cyclictest11:38:290
286132690,0sleep70-21swapper/709:39:197
147942610,0sleep60-21swapper/611:36:596
2752225827,18sleep30-21swapper/307:06:293
2755525430,8sleep70-21swapper/707:06:577
2742925428,9sleep40-21swapper/407:05:104
175652530,1sleep1231rcuc/110:23:581
296102520,0sleep50-21swapper/509:18:585
124022520,0sleep70-21swapper/712:01:197
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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