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2026-03-20 - 22:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Mar 20, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2513799144143,1cyclictest1116-21nfsd11:11:316
251059910218,41cyclictest686-21dbus-daemon11:11:312
198012960,2sleep72514599cyclictest10:02:147
152182930,2sleep72514599cyclictest12:06:457
149962860,2sleep22510599cyclictest09:50:562
149962860,2sleep22510599cyclictest09:50:562
25089997934,23cyclictest0-21swapper/011:11:310
2512299770,76cyclictest26760-21kworker/4:111:11:314
2514599570,56cyclictest4615-21kworker/7:011:11:327
59152560,0sleep10-21swapper/110:20:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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