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2026-02-11 - 05:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Feb 11, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46329914719,51cyclictest686-21dbus-daemon23:41:190
200602990,0sleep60-21swapper/623:44:456
289522850,1sleep0686-21dbus-daemon00:26:360
198312840,0sleep30-21swapper/321:33:073
190892800,2sleep0463299cyclictest23:52:080
465299750,74cyclictest20587-21kworker/6:023:41:186
275132730,1sleep627515-21fschecks_time20:43:136
113742590,0sleep70-21swapper/722:57:057
464199580,57cyclictest31806-21kworker/2:223:41:182
160222580,0sleep70-21swapper/700:16:267
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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