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2026-03-26 - 23:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Thu Mar 26, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
88672680,0sleep58866-21systemd-cgroups12:09:585
234922560,0sleep00-21swapper/009:49:450
65432530,0sleep70-21swapper/711:36:287
267822510,0sleep10-21swapper/110:08:281
1788924926,8sleep30-21swapper/307:04:293
1787224825,9sleep40-21swapper/407:04:144
190952460,0sleep719068-21sshd10:30:217
324382450,0sleep30-21swapper/309:53:573
311052450,0sleep60-21swapper/610:27:156
26052450,0sleep60-21swapper/609:09:316
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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