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2026-05-27 - 18:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed May 27, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
52152990,1sleep41707599cyclictest10:51:434
133042960,0sleep6631rcuc/609:23:356
21562930,0sleep50-21swapper/511:13:475
323392830,1sleep532341-21kworker/u16:209:39:205
1659025625,17sleep40-21swapper/407:05:054
180182550,0sleep70-21swapper/712:06:437
287652530,0sleep70-21swapper/710:23:357
236072520,0sleep2311rcuc/211:40:592
1685125026,8sleep70-21swapper/707:08:367
1676325027,8sleep60-21swapper/607:07:236
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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