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2026-04-15 - 22:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Apr 15, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2658321020,2sleep31765699cyclictest11:47:373
118632840,2sleep11764099cyclictest12:35:401
118632840,2sleep11764099cyclictest12:35:401
189462750,0sleep40-21swapper/409:56:214
16322750,0sleep10-21swapper/110:02:511
19612740,0sleep60-21swapper/610:46:056
37812720,0sleep00-21swapper/009:38:470
221972710,0sleep10-21swapper/111:04:101
30232680,1sleep7721ktimersoftd/709:51:437
303332610,0sleep60-21swapper/611:38:276
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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