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2026-06-08 - 04:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Jun 08, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31933991150,114cyclictest20333-21kworker/2:422:48:552
3193599110109,0cyclictest49-21ksoftirqd/422:48:564
43012840,1sleep4721-21dbus-daemon21:45:094
288842810,1sleep30-21swapper/321:56:053
253082780,0sleep30-21swapper/321:42:363
31937997737,40cyclictest0-21swapper/622:48:566
257482750,0sleep70-21swapper/722:28:137
257482750,0sleep70-21swapper/722:28:137
311152730,0sleep60-21swapper/623:44:536
217722690,2sleep23193399cyclictest23:00:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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