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2026-01-21 - 11:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Jan 21, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35372810,0sleep00-21swapper/023:13:260
35372810,0sleep00-21swapper/023:13:260
61482710,0sleep00-21swapper/000:01:560
286442640,0sleep40-21swapper/421:29:024
286442640,0sleep40-21swapper/421:29:024
994025228,9sleep10-21swapper/119:05:591
980024926,8sleep30-21swapper/319:04:083
234862490,0sleep623487-21sshd22:21:506
127302490,1sleep312731-21bash23:26:033
260562480,1sleep226014-21sshd21:26:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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