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2026-04-25 - 21:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Apr 25, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
125489911724,52cyclictest721-21dbus-daemon11:19:045
294432990,0sleep7711rcuc/710:53:127
197142820,1sleep019708-21sshd11:16:440
12556997232,0cyclictest0-21swapper/611:19:036
12521996563,2cyclictest1844-21nfsd11:19:032
1256499640,63cyclictest1325-21kworker/7:511:19:047
59822590,0sleep60-21swapper/609:48:406
59822590,0sleep60-21swapper/609:48:406
1185925626,15sleep70-21swapper/707:05:147
288242550,0sleep60-21swapper/609:40:396
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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