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2026-10-25 - 13:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Oct 25, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112832710,0sleep50-21swapper/511:36:005
255142650,0sleep10-21swapper/110:42:221
232032620,2sleep62231999cyclictest12:03:006
103062500,0sleep6721-21dbus-daemon10:26:336
103062500,0sleep6721-21dbus-daemon10:26:336
290012490,1sleep129002-21grepconf.sh11:58:311
249162490,0sleep60-21swapper/609:31:396
242322490,0sleep724228-21sshd11:36:587
2034524926,8sleep30-21swapper/307:00:483
2026624925,9sleep10-21swapper/106:59:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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