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2026-02-28 - 12:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Feb 28, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
981299860,85cyclictest31291-21kworker/3:422:36:143
9789998213,68cyclictest18596-21kworker/0:322:36:140
139842800,1sleep013985-21sshd22:24:520
9838997534,39cyclictest0-21swapper/622:36:146
129762740,0sleep60-21swapper/600:22:156
283852580,1sleep71-21systemd21:47:107
258102580,2sleep4982099cyclictest00:26:384
980499560,56cyclictest1436-21kworker/2:322:36:152
89632550,0sleep20-21swapper/223:04:502
133172550,0sleep50-21swapper/523:30:485
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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