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2026-02-05 - 23:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Thu Feb 05, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
239792830,0sleep30-21swapper/311:55:113
84562680,0sleep4471rcuc/411:18:044
189242570,1sleep449-21ksoftirqd/409:54:584
189242570,1sleep449-21ksoftirqd/409:54:584
240682520,0sleep50-21swapper/511:26:305
244762510,0sleep70-21swapper/712:37:447
244762510,0sleep70-21swapper/712:37:447
165642510,0sleep10-21swapper/112:19:361
1188225126,8sleep40-21swapper/407:05:554
214822500,0sleep60-21swapper/611:43:296
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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