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2026-01-17 - 07:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Jan 17, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
107642780,2sleep61892699cyclictest23:14:406
264662720,0sleep40-21swapper/421:28:504
135012530,0sleep20-21swapper/223:22:052
142942500,0sleep314297-21kworker/u16:000:33:263
230122490,0sleep20-21swapper/222:28:152
1862624926,9sleep70-21swapper/719:07:217
1842624926,8sleep30-21swapper/319:04:443
1861924824,8sleep00-21swapper/019:07:140
52812470,0sleep10-21swapper/122:22:051
313712470,0sleep40-21swapper/421:17:214
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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