You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-01 - 08:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Feb 01, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
289902750,1sleep411046-21kworker/4:121:52:254
250982710,0sleep10-21swapper/121:59:431
325792540,0sleep40-21swapper/400:14:494
260252510,0sleep126024-21systemd-cgroups22:30:101
139652510,0sleep20-21swapper/223:26:262
1971325046,1sleep70-21swapper/719:05:497
1971325046,1sleep70-21swapper/719:05:497
200832490,2sleep32015299cyclictest21:17:483
1969924825,8sleep20-21swapper/219:05:362
1969924825,8sleep20-21swapper/219:05:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional