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2026-02-16 - 04:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Feb 16, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
193542790,1sleep41638599cyclictest23:49:064
191202740,1sleep557-21ksoftirqd/500:21:355
219452670,0sleep20-21swapper/222:10:292
232102650,0sleep3391rcuc/322:19:513
87512640,0sleep30-21swapper/323:56:023
83532540,0sleep58354-21kworker/u16:123:09:595
79502540,0sleep67947-21sshd23:31:146
327672500,0sleep30-21swapper/322:50:353
36262480,0sleep70-21swapper/723:02:167
75662470,2sleep61640299cyclictest00:34:266
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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