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2026-03-01 - 00:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Feb 28, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2118699135131,1cyclictest49-21ksoftirqd/411:58:394
2117799124121,1cyclictest1115-21nfsd11:58:382
21192997746,1cyclictest1116-21nfsd11:58:395
296272760,0sleep60-21swapper/611:22:236
42082740,2sleep22117799cyclictest11:04:172
21196997242,30cyclictest0-21swapper/611:58:386
2117699690,69cyclictest16492-21kworker/1:111:58:391
93892640,0sleep50-21swapper/510:42:335
107302560,1sleep010720-21sshd11:59:570
46212540,0sleep50-21swapper/512:03:155
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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