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2026-04-01 - 02:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Apr 01, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112352780,0sleep20-21swapper/222:05:302
194282730,2sleep11862699cyclictest23:46:211
274392720,0sleep50-21swapper/523:15:095
322002670,0sleep70-21swapper/722:17:457
9532600,0sleep10-21swapper/121:37:021
9532600,0sleep10-21swapper/121:37:021
241952550,2sleep71864199cyclictest22:28:267
40662520,2sleep01862099cyclictest23:04:310
46052510,0sleep60-21swapper/621:13:126
204622500,0sleep220450-21sshd23:12:502
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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