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2026-05-05 - 22:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue May 05, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11689915050,100cyclictest0-21swapper/509:33:425
115299101100,1cyclictest1841-21nfsd09:33:411
1162999877,21cyclictest49-21ksoftirqd/411:04:194
1162999351,14cyclictest49-21ksoftirqd/410:11:334
1162999351,14cyclictest49-21ksoftirqd/410:11:334
1156998482,1cyclictest1843-21nfsd10:11:333
1156998482,1cyclictest1843-21nfsd10:11:333
117999700,69cyclictest5904-21kworker/7:311:04:207
149852550,0sleep10-21swapper/111:56:521
115299550,54cyclictest26558-21kworker/1:311:04:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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