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2026-02-13 - 19:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Feb 13, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
214182740,1sleep621395-21bash10:27:286
294882720,0sleep70-21swapper/710:04:467
208512710,0sleep30-21swapper/311:52:463
307502580,0sleep20-21swapper/211:24:342
126142530,2sleep72570299cyclictest12:24:147
49712520,0sleep5561ktimersoftd/510:58:425
30332510,0sleep10-21swapper/110:11:131
2527725027,8sleep00-21swapper/007:05:260
36482480,0sleep00-21swapper/009:10:250
31542480,1sleep21-21systemd12:34:582
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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