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2026-04-21 - 18:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue Apr 21, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
54862840,0sleep7711rcuc/710:35:027
258472720,0sleep70-21swapper/711:30:207
22995997021,26cyclictest857-21polkitd11:17:555
289502670,0sleep70-21swapper/710:08:197
289502670,0sleep70-21swapper/710:08:197
2282526049,8sleep70-21swapper/707:09:477
2036426055,2sleep60-21swapper/607:05:056
202752590,0sleep60-21swapper/609:23:096
70312560,1sleep17030-21systemd-cgroups12:16:031
160082550,0sleep10-21swapper/111:52:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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