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2026-06-06 - 01:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Jun 05, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
309572950,0sleep10-21swapper/112:20:021
64622750,1sleep09-21ksoftirqd/010:30:280
279782750,0sleep427957-21sshd09:38:024
91942730,0sleep125-21ksoftirqd/111:26:361
91942730,0sleep125-21ksoftirqd/111:26:361
102272660,0sleep70-21swapper/709:38:457
274182590,0sleep00-21swapper/011:48:130
241062570,1sleep0721-21dbus-daemon11:19:540
241062570,1sleep0721-21dbus-daemon11:19:540
233025645,8sleep30-21swapper/307:07:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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