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2026-09-24 - 21:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Thu Sep 24, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300092870,2sleep5106299cyclictest10:43:055
278662690,0sleep30-21swapper/309:47:533
48312650,0sleep20-21swapper/212:19:532
99612550,1sleep39945-21sshd11:49:353
59425226,9sleep40-21swapper/407:01:464
93132510,1sleep233-21ksoftirqd/209:31:262
76225026,8sleep70-21swapper/707:03:347
55025026,8sleep00-21swapper/007:01:100
191062500,0sleep40-21swapper/409:47:224
79182480,2sleep4721-21dbus-daemon09:10:374
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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