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2026-05-26 - 02:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue May 26, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2384321040,0sleep70-21swapper/722:28:067
2384321040,0sleep70-21swapper/722:28:067
127252770,2sleep62412899cyclictest00:16:186
202712730,1sleep1241ktimersoftd/100:29:351
262952720,1sleep326290-21sshd23:05:033
195832690,0sleep00-21swapper/021:32:410
195832690,0sleep00-21swapper/021:32:410
213122620,0sleep40-21swapper/400:16:484
98332530,0sleep40-21swapper/421:57:524
274432520,2sleep02408599cyclictest21:38:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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