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2025-12-13 - 11:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Dec 13, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
66292780,0sleep50-21swapper/521:33:085
205162740,0sleep50-21swapper/522:01:505
337725643,9sleep70-21swapper/719:05:457
577225139,8sleep30-21swapper/319:09:503
558624725,8sleep00-21swapper/019:07:150
323082470,0sleep30-21swapper/323:07:473
332624629,13sleep50-21swapper/519:05:035
78932450,0sleep71-21systemd23:46:517
176622430,0sleep60-21swapper/623:26:566
576624231,8sleep60-21swapper/619:09:456
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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