You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-02 - 15:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Mar 02, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
148902870,2sleep02156999cyclictest11:14:490
313762830,2sleep22158699cyclictest10:05:312
29092820,11sleep687950irq/25-em1-rx-009:32:276
304982790,0sleep030496-21sshd11:08:160
326692750,0sleep40-21swapper/411:23:184
252402720,2sleep62161499cyclictest12:31:446
5852680,2sleep32159399cyclictest09:15:423
104692640,0sleep00-21swapper/011:55:330
2123425828,17sleep50-21swapper/507:04:535
26942500,0sleep60-21swapper/612:09:576
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional