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2026-09-18 - 17:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Sep 18, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26482991180,117cyclictest12367-21kworker/6:211:34:336
264369910484,19cyclictest9-21ksoftirqd/011:34:340
140562940,0sleep10-21swapper/110:21:071
134012750,0sleep30-21swapper/312:01:053
216382710,1sleep22645299cyclictest11:32:522
101722700,0sleep20-21swapper/209:44:402
41802620,0sleep60-21swapper/610:26:166
8382520,0sleep30-21swapper/309:42:163
154042510,0sleep40-21swapper/411:28:304
16502500,1sleep2721-21dbus-daemon11:44:542
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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