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2026-07-04 - 14:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Jul 04, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
188662990,2sleep03235599cyclictest09:46:540
207842890,6sleep33237999cyclictest09:31:433
193022850,0sleep0111rcuc/010:08:080
29042730,0sleep60-21swapper/609:57:416
29042730,0sleep60-21swapper/609:57:416
3212225027,9sleep50-21swapper/507:05:565
202522500,1sleep520245-21sshd12:13:325
108782500,0sleep70-21swapper/712:28:247
3211924926,8sleep20-21swapper/207:05:532
291892470,0sleep029187-21sshd09:22:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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