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2026-03-03 - 17:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue Mar 03, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
188832530,2sleep71287499cyclictest07:17:257
165222520,0sleep50-21swapper/511:00:425
13282500,1sleep11319-21bash10:18:581
76692490,1sleep17670-21kworker/u16:011:46:441
88742480,0sleep70-21swapper/709:47:567
268972480,0sleep00-21swapper/009:58:140
183622480,0sleep10-21swapper/109:31:561
1253124825,8sleep60-21swapper/607:05:166
226502470,0sleep20-21swapper/212:13:362
84602450,2sleep51285899cyclictest12:16:355
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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