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2025-08-26 - 21:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Tue Aug 26, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
72352820,2sleep02740499cyclictest11:48:100
324272710,1sleep51-21systemd09:13:095
2718725026,8sleep70-21swapper/706:56:367
2703924925,9sleep50-21swapper/506:54:335
32732460,0sleep30-21swapper/311:02:073
214532450,0sleep52743599cyclictest09:09:175
97092440,2sleep52743599cyclictest11:45:345
2697724323,8sleep20-21swapper/206:53:422
252002430,0sleep20-21swapper/212:23:032
251232430,0sleep10-21swapper/111:52:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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