You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-29 - 09:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Thu Jan 29, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
108062860,0sleep40-21swapper/423:44:234
88252750,0sleep60-21swapper/621:48:526
219802720,6sleep213550irq/24-ahci[00021:16:042
155892530,1sleep228702-1kworker/2:1H23:25:472
91152520,2sleep02107799cyclictest23:51:560
91152520,2sleep02107799cyclictest23:51:560
2077525125,9sleep40-21swapper/419:06:034
105982480,0sleep50-21swapper/522:43:455
284612470,0sleep70-21swapper/722:56:127
60902460,0sleep60-21swapper/600:18:216
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional