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2026-01-14 - 04:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Jan 14, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23672820,0sleep099-21kswapd023:35:200
23672820,0sleep099-21kswapd023:35:200
19302570,3sleep02747699cyclictest21:31:300
202702560,0sleep40-21swapper/421:44:314
2706225126,8sleep40-21swapper/419:04:564
201382510,0sleep20-21swapper/220:48:552
201382510,0sleep20-21swapper/220:48:552
53492500,0sleep10-21swapper/123:28:321
258242500,0sleep7721ktimersoftd/722:25:277
2707624824,8sleep00-21swapper/019:05:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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