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2025-12-15 - 09:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Dec 15, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
161092450,0sleep10-21swapper/122:54:391
282872440,0sleep00-21swapper/000:27:350
2054524432,9sleep40-21swapper/419:08:374
176962420,0sleep10-21swapper/122:18:431
294302410,0sleep10-21swapper/123:51:411
2053524124,13sleep30-21swapper/319:08:283
2051924130,8sleep20-21swapper/219:08:192
2054724027,9sleep60-21swapper/619:08:396
2052624028,8sleep70-21swapper/719:08:247
2063923927,8sleep00-21swapper/019:09:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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