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2026-02-27 - 02:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Fri Feb 27, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
131862690,0sleep60-21swapper/600:03:596
277672660,0sleep10-21swapper/122:59:311
178432610,0sleep20-21swapper/223:38:482
13642560,2sleep2714099cyclictest00:19:412
226942520,0sleep60-21swapper/621:32:146
202902520,0sleep10-21swapper/121:19:201
264832510,0sleep60-21swapper/623:50:146
248732510,2sleep1713299cyclictest22:50:181
57492500,0sleep25746-21sshd23:30:562
37502500,0sleep10-21swapper/121:16:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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