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2026-07-22 - 20:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Wed Jul 22, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
172139911657,41cyclictest721-21dbus-daemon09:30:571
16650210196,2sleep40-21swapper/407:02:284
17251999156,0cyclictest0-21swapper/609:30:576
63452870,1sleep16340-21systemd-cgroups10:11:311
23922800,0sleep60-21swapper/611:25:456
17205996821,0cyclictest0-21swapper/009:30:570
198972580,0sleep519860-21sshd10:23:045
314502560,0sleep50-21swapper/509:32:595
204322550,0sleep10-21swapper/110:54:001
252042540,0sleep10-21swapper/112:35:561
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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