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2026-01-27 - 00:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Mon Jan 26, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5763991460,145cyclictest11380-21kworker/5:109:33:015
57559911634,81cyclictest686-21dbus-daemon09:33:024
37172720,1sleep33716-21sshd09:47:563
37172720,1sleep33716-21sshd09:47:563
5770996415,48cyclictest0-21swapper/609:33:026
98582550,1sleep69797-21sshd11:54:306
288452530,0sleep40-21swapper/409:33:404
37742510,1sleep43778-21bash11:56:044
272192490,1sleep027218-21grepconf.sh11:45:510
152912490,0sleep40-21swapper/411:29:134
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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