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2026-03-04 - 13:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot0.osadl.org (updated Wed Mar 04, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
294902950,0sleep60-21swapper/621:30:166
115042940,0sleep00-21swapper/022:17:270
209842810,0sleep50-21swapper/523:13:395
67772790,0sleep40-21swapper/421:41:594
67772790,0sleep40-21swapper/421:41:594
96592760,0sleep60-21swapper/623:00:026
317982700,0sleep1231rcuc/122:31:381
20732600,0sleep60-21swapper/621:58:196
2406325954,2sleep70-21swapper/719:05:247
61662530,0sleep56168-21latency_hist00:27:155
61662530,0sleep56168-21latency_hist00:27:155
122272510,0sleep712224-21sshd21:34:497
35702500,2sleep32432499cyclictest21:23:083
256812500,0sleep125677-21sshd21:44:531
37372490,0sleep40-21swapper/423:08:574
278342490,0sleep00-21swapper/023:34:320
264062490,1sleep326402-21systemd22:27:313
137432490,1sleep0111rcuc/021:31:140
40902480,0sleep30-21swapper/321:28:453
317552480,0sleep40-21swapper/423:27:234
42612470,0sleep70-21swapper/722:15:107
219342470,5sleep40-21swapper/421:24:134
140282470,0sleep60-21swapper/621:21:596
76172460,1sleep09-21ksoftirqd/022:41:220
68372460,0sleep76813-21sshd23:48:087
6252460,0sleep233-21ksoftirqd/222:22:262
39242450,2sleep62433999cyclictest22:50:256
38112450,0sleep00-21swapper/021:12:000
72242440,0sleep40-21swapper/422:37:334
167602440,2sleep52433799cyclictest00:35:165
132232440,0sleep70-21swapper/723:37:277
2386224331,8sleep50-21swapper/519:02:425
4362420,0sleep50-21swapper/523:44:065
279912420,1sleep127990-21sshd22:44:191
153052420,1sleep715303-21sshd00:03:307
76012410,0sleep70-21swapper/722:19:027
2416924116,9sleep60-21swapper/619:06:516
2394324128,9sleep30-21swapper/319:03:443
2389324130,8sleep20-21swapper/219:03:032
229442410,0sleep50-21swapper/523:47:185
186352410,0sleep60-21swapper/622:27:106
121732410,0sleep70-21swapper/700:20:047
121732410,0sleep70-21swapper/700:20:047
66672400,0sleep40-21swapper/422:04:104
2417324027,9sleep10-21swapper/119:06:541
2395724027,9sleep40-21swapper/419:03:534
184382400,0sleep40-21swapper/423:45:094
261182390,1sleep026119-21bash22:12:390
2396223927,8sleep00-21swapper/019:03:570
142152390,2sleep52433799cyclictest21:42:245
73142380,0sleep40-21swapper/400:10:324
64502380,0sleep00-21swapper/023:50:020
108332380,2sleep62433999cyclictest00:16:196
314592370,0sleep40-21swapper/423:16:104
104262370,0sleep70-21swapper/722:32:167
104262370,0sleep70-21swapper/722:32:167
5462360,2sleep52433799cyclictest22:09:235
106942270,1sleep410685-21sshd00:12:324
316182260,12sleep687950irq/25-em1-rx-021:45:146
302162220,0sleep50-21swapper/522:25:575
2431599228,1cyclictest25-21ksoftirqd/122:27:141
24315992210,1cyclictest121rcu_preempt23:00:391
2431599217,1cyclictest25-21ksoftirqd/123:28:191
2431599214,3cyclictest25-21ksoftirqd/121:47:281
24315992117,4cyclictest25-21ksoftirqd/121:25:371
320212200,0sleep70-21swapper/723:12:287
2431599209,1cyclictest25-21ksoftirqd/123:55:561
2431599203,3cyclictest25-21ksoftirqd/100:09:431
24315992018,1cyclictest25-21ksoftirqd/123:07:241
2431599198,1cyclictest121rcu_preempt00:30:591
2431599193,2cyclictest25-21ksoftirqd/121:33:061
24315991916,1cyclictest25-21ksoftirqd/123:24:091
24315991916,1cyclictest25-21ksoftirqd/123:24:091
24315991916,1cyclictest25-21ksoftirqd/123:19:161
24315991914,1cyclictest25-21ksoftirqd/100:19:071
24315991914,1cyclictest25-21ksoftirqd/100:19:071
2431599190,2cyclictest131rcu_sched22:13:581
24347991813,2cyclictest18752-21systemd22:58:407
24324991816,1cyclictest41-21ksoftirqd/323:04:573
2431599188,3cyclictest25-21ksoftirqd/122:53:431
24315991816,1cyclictest25-21ksoftirqd/122:51:101
24315991816,1cyclictest25-21ksoftirqd/122:42:051
24315991816,1cyclictest25-21ksoftirqd/122:11:101
24315991816,1cyclictest25-21ksoftirqd/121:07:251
24315991816,1cyclictest25-21ksoftirqd/100:04:441
24315991815,3cyclictest25-21ksoftirqd/123:42:261
24315991814,3cyclictest25-21ksoftirqd/122:02:321
24315991814,1cyclictest25-21ksoftirqd/121:39:291
24315991814,1cyclictest25-21ksoftirqd/121:39:291
24315991814,1cyclictest25-21ksoftirqd/121:27:541
2431599180,1cyclictest131rcu_sched23:50:341
2431599180,1cyclictest131rcu_sched23:02:521
24324991716,1cyclictest41-21ksoftirqd/321:08:403
24324991715,1cyclictest41-21ksoftirqd/322:25:583
24324991712,4cyclictest41-21ksoftirqd/322:50:533
2431599176,3cyclictest25-21ksoftirqd/122:34:111
2431599176,3cyclictest25-21ksoftirqd/122:34:111
2431599176,1cyclictest25-21ksoftirqd/100:25:281
2431599176,1cyclictest25-21ksoftirqd/100:25:281
24315991716,1cyclictest25-21ksoftirqd/123:57:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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