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2026-01-27 - 09:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot0.osadl.org (updated Tue Jan 27, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
204392740,0sleep60-21swapper/622:53:426
155342720,0sleep4471rcuc/400:04:204
104222570,1sleep11-21systemd21:28:551
65242520,1sleep26456-21sshd22:09:252
2575025127,8sleep00-21swapper/019:04:170
279392500,0sleep5686-21dbus-daemon23:22:085
282882470,0sleep70-21swapper/700:14:407
245612470,1sleep724542-21sshd23:59:027
124172470,1sleep233-21ksoftirqd/221:38:492
154472460,0sleep20-21swapper/222:31:432
47792450,0sleep3391rcuc/323:34:073
240842450,0sleep2686-21dbus-daemon21:35:372
162032450,0sleep11-21systemd00:10:091
308752440,0sleep60-21swapper/622:03:126
262202440,0sleep326219-21systemd-cgroups23:43:123
209132440,0sleep10-21swapper/122:49:441
138522440,1sleep5784-21runrttasks00:21:355
188662430,0sleep70-21swapper/700:31:467
124082430,0sleep40-21swapper/400:27:264
119332430,0sleep20-21swapper/200:06:022
311292420,0sleep30-21swapper/322:56:193
2591324231,8sleep30-21swapper/319:06:283
239192420,0sleep40-21swapper/400:10:364
87302410,0sleep40-21swapper/423:56:114
59762410,0sleep10-21swapper/123:22:441
4052410,0sleep10-21swapper/123:45:271
264282410,2sleep52623099cyclictest22:34:275
173492410,2sleep72623999cyclictest23:03:447
143172410,0sleep50-21swapper/523:34:415
114022410,0sleep411384-21sshd00:35:034
275382400,0sleep10-21swapper/123:31:411
275382400,0sleep10-21swapper/123:31:411
2602424029,8sleep70-21swapper/719:08:017
2591524028,8sleep50-21swapper/519:06:305
2572924028,9sleep60-21swapper/619:03:596
184312400,0sleep60-21swapper/622:29:476
171152400,0sleep30-21swapper/323:19:263
109412400,0sleep30-21swapper/321:27:133
51502390,0sleep20-21swapper/221:46:182
307112390,0sleep30-21swapper/323:27:593
2581923927,8sleep20-21swapper/219:05:152
137522390,0sleep50-21swapper/523:52:355
260132380,0sleep60-21swapper/600:14:316
2581223827,8sleep40-21swapper/419:05:094
2572423826,8sleep10-21swapper/119:03:541
317712370,0sleep50-21swapper/523:43:305
281982370,2sleep12620499cyclictest22:40:391
262882370,0sleep30-21swapper/323:47:053
26209992611,2cyclictest33-21ksoftirqd/223:16:282
2620999258,3cyclictest33-21ksoftirqd/223:38:322
2620999238,3cyclictest33-21ksoftirqd/222:16:442
78202220,0sleep70-21swapper/723:18:507
2620999228,2cyclictest33-21ksoftirqd/222:20:022
26209992218,1cyclictest33-21ksoftirqd/221:20:182
26209992216,2cyclictest33-21ksoftirqd/222:50:382
26209992212,3cyclictest33-21ksoftirqd/221:11:372
26209992212,2cyclictest33-21ksoftirqd/200:24:102
26209992211,2cyclictest33-21ksoftirqd/223:01:242
23322220,0sleep00-21swapper/000:38:200
2620999218,3cyclictest33-21ksoftirqd/223:25:512
2620999218,3cyclictest33-21ksoftirqd/200:00:382
2620999218,2cyclictest33-21ksoftirqd/222:38:402
2620999218,1cyclictest33-21ksoftirqd/223:20:422
2620999217,2cyclictest33-21ksoftirqd/222:47:082
2620999216,3cyclictest33-21ksoftirqd/223:31:002
2620999216,3cyclictest33-21ksoftirqd/223:31:002
2620999215,3cyclictest33-21ksoftirqd/223:33:532
26209992112,1cyclictest33-21ksoftirqd/223:11:302
26209992111,3cyclictest33-21ksoftirqd/221:24:052
26212992017,1cyclictest41-21ksoftirqd/323:57:533
2620999205,1cyclictest33-21ksoftirqd/222:03:332
26209992016,1cyclictest33-21ksoftirqd/200:21:552
26209992010,2cyclictest33-21ksoftirqd/200:18:282
2620999200,3cyclictest121rcu_preempt23:49:042
26212991917,1cyclictest41-21ksoftirqd/300:22:383
2620999197,3cyclictest33-21ksoftirqd/221:48:392
2620999194,2cyclictest33-21ksoftirqd/221:29:372
2620999194,1cyclictest33-21ksoftirqd/223:56:472
26209991915,1cyclictest33-21ksoftirqd/221:58:542
26209991910,1cyclictest33-21ksoftirqd/221:54:342
292352180,1sleep0101ktimersoftd/000:22:340
26239991813,3cyclictest73-21ksoftirqd/721:30:047
26212991816,1cyclictest41-21ksoftirqd/300:32:273
26212991815,3cyclictest41-21ksoftirqd/323:03:573
26212991814,4cyclictest41-21ksoftirqd/322:16:443
26212991814,1cyclictest41-21ksoftirqd/321:16:013
2620999189,1cyclictest33-21ksoftirqd/222:24:082
2620999189,1cyclictest33-21ksoftirqd/222:24:082
2620999187,3cyclictest33-21ksoftirqd/222:55:222
2620999186,2cyclictest33-21ksoftirqd/221:14:122
26209991813,3cyclictest33-21ksoftirqd/200:32:502
26209991810,1cyclictest33-21ksoftirqd/200:10:242
2620999181,1cyclictest33-21ksoftirqd/222:36:362
2620999181,1cyclictest121rcu_preempt00:36:022
26196991813,1cyclictest32735-21systemd00:03:330
231892180,2sleep72623999cyclictest23:55:027
217412180,0sleep7686-21dbus-daemon23:35:077
89922170,0sleep00-21swapper/023:38:210
26239991715,1cyclictest73-21ksoftirqd/723:27:487
26212991716,1cyclictest41-21ksoftirqd/321:19:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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