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2026-02-07 - 04:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot0.osadl.org (updated Sat Feb 07, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1430021050,0sleep30-21swapper/323:14:473
118622930,1sleep610209-21kworker/6:022:47:596
72942790,1sleep4784-21runrttasks19:03:184
209662730,0sleep00-21swapper/023:59:210
250302720,0sleep50-21swapper/500:20:415
58442660,0sleep40-21swapper/400:21:284
38582560,0sleep0101ktimersoftd/022:03:240
147672520,0sleep50-21swapper/523:49:335
913925026,8sleep50-21swapper/519:03:445
325862500,0sleep632584-21systemd-cgroups23:54:236
935024925,8sleep20-21swapper/219:06:382
915724925,9sleep10-21swapper/119:03:561
252372490,1sleep557-21ksoftirqd/523:17:305
50332480,0sleep15032-21systemd-cgroups22:32:001
324422480,0sleep732441-21systemd-cgroups23:12:037
324422480,0sleep732441-21systemd-cgroups23:12:037
323172480,0sleep30-21swapper/322:01:193
303672470,0sleep5551rcuc/520:38:245
285582470,0sleep70-21swapper/723:42:557
130652470,0sleep50-21swapper/522:24:435
107622470,0sleep20-21swapper/222:47:552
57372460,0sleep10-21swapper/100:36:391
292512460,0sleep60-21swapper/622:08:436
106202460,0sleep60-21swapper/600:08:256
112732450,0sleep3391rcuc/321:56:223
108062450,1sleep310774-21sshd21:20:103
280572440,1sleep125-21ksoftirqd/122:37:291
8202430,0sleep50-21swapper/522:10:585
39932430,0sleep00-21swapper/022:38:000
320912430,0sleep70-21swapper/700:00:017
296392430,0sleep30-21swapper/323:06:143
274492430,2sleep4960199cyclictest22:02:564
250652430,0sleep7711rcuc/721:47:457
93412420,0sleep10-21swapper/123:26:151
53682420,0sleep60-21swapper/621:29:106
203352420,0sleep40-21swapper/423:01:594
129102420,0sleep20-21swapper/200:25:352
936024130,8sleep30-21swapper/319:06:473
934824128,9sleep00-21swapper/019:06:360
4582410,0sleep40-21swapper/422:23:544
300972410,0sleep10-21swapper/122:27:441
247462410,0sleep10-21swapper/121:22:561
193472410,0sleep00-21swapper/023:57:290
942224029,8sleep70-21swapper/719:07:397
215342400,0sleep30-21swapper/300:35:373
21442400,0sleep60-21swapper/622:31:496
926923926,9sleep60-21swapper/619:05:296
61302390,0sleep21-21systemd21:44:362
110682370,0sleep70-21swapper/723:45:357
237212360,0sleep60-21swapper/600:01:366
177502270,12sleep687950irq/25-em1-rx-023:03:376
9586992614,3cyclictest25-21ksoftirqd/123:58:151
960899259,5cyclictest686-21dbus-daemon21:17:385
960199229,2cyclictest49-21ksoftirqd/423:39:274
958699229,2cyclictest25-21ksoftirqd/100:17:431
9586992214,3cyclictest25-21ksoftirqd/121:58:301
960199217,3cyclictest49-21ksoftirqd/423:03:234
960199216,4cyclictest49-21ksoftirqd/423:12:594
960199216,4cyclictest49-21ksoftirqd/423:12:594
960199216,2cyclictest49-21ksoftirqd/422:05:144
9601992111,1cyclictest49-21ksoftirqd/400:33:414
9591992113,5cyclictest33-21ksoftirqd/221:58:182
958699216,1cyclictest25-21ksoftirqd/122:38:261
958699215,1cyclictest25-21ksoftirqd/121:57:201
960199207,3cyclictest49-21ksoftirqd/421:27:504
960199204,1cyclictest49-21ksoftirqd/423:35:514
960199203,1cyclictest49-21ksoftirqd/423:31:524
958699209,3cyclictest25-21ksoftirqd/121:30:481
958699202,4cyclictest25-21ksoftirqd/121:44:581
958699201,1cyclictest19581-21sshd21:33:501
958699200,2cyclictest25-21ksoftirqd/122:16:391
960199197,3cyclictest49-21ksoftirqd/421:54:314
960199196,3cyclictest49-21ksoftirqd/400:28:404
960199196,1cyclictest49-21ksoftirqd/422:30:294
960199194,4cyclictest49-21ksoftirqd/422:57:214
960199194,2cyclictest49-21ksoftirqd/400:02:174
9601991916,3cyclictest49-21ksoftirqd/422:50:474
9601991916,2cyclictest49-21ksoftirqd/400:09:044
9601991915,3cyclictest49-21ksoftirqd/423:15:004
9601991911,4cyclictest49-21ksoftirqd/421:19:084
9601991910,1cyclictest49-21ksoftirqd/422:22:174
960199191,2cyclictest49-21ksoftirqd/421:30:094
9595991918,1cyclictest41-21ksoftirqd/300:06:023
9595991918,1cyclictest41-21ksoftirqd/300:06:023
9591991912,4cyclictest33-21ksoftirqd/221:28:112
958699199,3cyclictest25-21ksoftirqd/123:05:151
958699199,3cyclictest25-21ksoftirqd/122:50:371
958699198,2cyclictest25-21ksoftirqd/123:55:461
958699197,1cyclictest25-21ksoftirqd/100:07:191
958699197,1cyclictest25-21ksoftirqd/100:07:191
958699196,4cyclictest25-21ksoftirqd/100:28:341
9586991916,1cyclictest25-21ksoftirqd/121:09:161
9586991911,3cyclictest25-21ksoftirqd/121:40:531
9586991910,2cyclictest25-21ksoftirqd/122:07:531
958699190,4cyclictest25-21ksoftirqd/123:28:171
958699190,2cyclictest0-21swapper/123:40:061
960199185,1cyclictest131rcu_sched22:14:224
960199184,3cyclictest49-21ksoftirqd/422:46:434
960199184,1cyclictest49-21ksoftirqd/400:24:104
960199183,3cyclictest49-21ksoftirqd/421:08:504
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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