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2026-01-23 - 17:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot0.osadl.org (updated Fri Jan 23, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3147499160116,42cyclictest73-21ksoftirqd/712:25:087
314749911192,19cyclictest73-21ksoftirqd/712:21:517
31473997918,61cyclictest0-21swapper/612:25:516
160192780,1sleep73147499cyclictest10:27:077
108262760,1sleep03144299cyclictest11:35:320
31473997353,20cyclictest0-21swapper/612:21:546
25802710,0sleep30-21swapper/311:42:483
3146999580,58cyclictest6969-21kworker/4:112:24:224
3144299580,57cyclictest24206-21kworker/u16:112:22:060
31451995538,17cyclictest13550irq/24-ahci[00012:21:542
313472520,0sleep10-21swapper/111:55:431
313472520,0sleep10-21swapper/111:55:431
3115025227,9sleep70-21swapper/707:06:407
3113025026,9sleep50-21swapper/507:06:225
53082490,1sleep557-21ksoftirqd/511:01:015
275262490,3sleep10-21swapper/110:10:521
3147299470,47cyclictest0-21swapper/512:25:515
200682470,1sleep3401ktimersoftd/312:18:283
256282460,0sleep30-21swapper/311:47:203
260822450,0sleep00-21swapper/009:55:530
165022450,0sleep70-21swapper/712:15:287
31461994444,0cyclictest10872-21kworker/3:212:22:053
73892430,0sleep7711rcuc/710:18:597
4582430,0sleep4455-21systemd-cgroups11:45:134
31461994312,30cyclictest12332-21kworker/3:312:24:113
296612430,0sleep60-21swapper/611:53:006
162162430,0sleep50-21swapper/511:54:275
162162430,0sleep50-21swapper/511:54:275
44322420,1sleep53147299cyclictest09:56:305
3117624229,9sleep40-21swapper/407:07:014
31142420,0sleep40-21swapper/411:11:174
3114424130,8sleep10-21swapper/107:06:341
186082410,0sleep00-21swapper/010:41:180
168512410,1sleep665-21ksoftirqd/609:28:526
318962400,0sleep09-21ksoftirqd/011:04:010
31448994038,1cyclictest1-21systemd12:22:481
3106024027,9sleep30-21swapper/307:05:243
177232400,0sleep10-21swapper/112:35:161
67072390,0sleep40-21swapper/407:18:544
3144299390,39cyclictest28610-21kworker/u16:212:27:110
3097823927,9sleep60-21swapper/607:04:156
185722390,0sleep40-21swapper/407:38:554
3145199389,22cyclictest0-21swapper/212:24:092
314352380,0sleep70-21swapper/710:11:067
3115423827,8sleep20-21swapper/207:06:432
3095923826,8sleep00-21swapper/007:04:010
3144899370,37cyclictest20741-21kworker/1:012:26:061
62042340,2sleep43146999cyclictest09:52:454
244132340,0sleep60-21swapper/610:01:206
31472993030,0cyclictest0-21swapper/512:21:505
3146999290,28cyclictest26845-21kworker/4:312:21:524
217502220,1sleep721740-21sshd10:18:027
31461991916,3cyclictest41-21ksoftirqd/310:43:033
99932180,0sleep20-21swapper/210:43:522
31474991816,1cyclictest73-21ksoftirqd/709:40:197
31461991814,1cyclictest41-21ksoftirqd/310:03:363
3146199181,1cyclictest131rcu_sched12:08:413
189152180,0sleep40-21swapper/411:25:434
31474991715,1cyclictest73-21ksoftirqd/712:31:177
31474991715,1cyclictest73-21ksoftirqd/709:37:317
31474991715,1cyclictest73-21ksoftirqd/709:16:257
31474991713,1cyclictest73-21ksoftirqd/710:43:277
31474991712,3cyclictest73-21ksoftirqd/710:07:357
3147499170,16cyclictest12424-21kworker/7:109:25:517
31473991712,4cyclictest24993-21systemd09:53:516
31461991716,1cyclictest41-21ksoftirqd/309:53:013
31461991715,1cyclictest41-21ksoftirqd/310:13:013
31461991715,1cyclictest41-21ksoftirqd/309:47:233
31461991715,1cyclictest41-21ksoftirqd/309:22:393
31461991714,1cyclictest41-21ksoftirqd/311:35:243
31461991714,1cyclictest41-21ksoftirqd/309:31:323
31461991714,1cyclictest41-21ksoftirqd/309:17:463
31461991713,3cyclictest41-21ksoftirqd/311:19:353
3146199170,16cyclictest3344-21kworker/3:110:04:123
31474991614,1cyclictest73-21ksoftirqd/711:44:167
31474991614,1cyclictest73-21ksoftirqd/711:26:327
31474991614,1cyclictest73-21ksoftirqd/709:44:047
31474991614,1cyclictest73-21ksoftirqd/709:21:157
3147499160,1cyclictest131rcu_sched09:51:247
31461991615,1cyclictest41-21ksoftirqd/312:04:133
31461991615,1cyclictest41-21ksoftirqd/312:04:133
31461991615,1cyclictest41-21ksoftirqd/309:36:063
31461991615,1cyclictest41-21ksoftirqd/309:12:173
31461991615,1cyclictest41-21ksoftirqd/309:12:173
31461991614,2cyclictest41-21ksoftirqd/310:14:403
31461991614,1cyclictest41-21ksoftirqd/311:52:483
31461991614,1cyclictest41-21ksoftirqd/311:10:213
31461991614,1cyclictest1-21systemd11:58:463
31461991614,1cyclictest1-21systemd11:58:463
31461991613,1cyclictest41-21ksoftirqd/312:37:333
31461991612,1cyclictest41-21ksoftirqd/310:57:313
249252160,0sleep20-21swapper/210:08:522
31474991514,1cyclictest73-21ksoftirqd/712:01:247
31474991514,1cyclictest73-21ksoftirqd/712:01:247
31474991514,1cyclictest73-21ksoftirqd/711:07:217
31474991514,1cyclictest73-21ksoftirqd/709:33:167
31474991513,1cyclictest73-21ksoftirqd/710:50:237
31474991513,1cyclictest73-21ksoftirqd/709:53:567
31474991512,1cyclictest73-21ksoftirqd/711:30:557
31474991512,1cyclictest73-21ksoftirqd/711:10:597
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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