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2026-04-30 - 16:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Thu Apr 30, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201572750,0sleep40-21swapper/409:16:124
192702730,0sleep20-21swapper/209:58:392
11509997012,58cyclictest0-21swapper/512:07:465
279082690,0sleep50-21swapper/509:38:475
1149599610,60cyclictest25399-21kworker/3:112:07:453
221922590,0sleep50-21swapper/511:12:185
108832550,3sleep2321ktimersoftd/212:32:332
171672530,0sleep50-21swapper/509:32:395
11518995251,1cyclictest65-21ksoftirqd/612:07:466
269982510,0sleep00-21swapper/011:55:460
1106925026,9sleep50-21swapper/507:05:465
87892490,0sleep70-21swapper/710:56:267
87892490,0sleep70-21swapper/710:56:267
1123624925,9sleep20-21swapper/207:08:072
72952470,1sleep77294-21bash10:09:097
40112470,1sleep5561ktimersoftd/512:37:485
15882470,2sleep11147999cyclictest11:05:251
213202460,0sleep60-21swapper/612:27:326
16402460,0sleep20-21swapper/212:11:262
120162460,0sleep20-21swapper/212:06:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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