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2024-04-20 - 04:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Sat Apr 20, 2024 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
129662790,3sleep61060699cyclictest21:13:026
1008825826,18sleep70-21swapper/719:04:207
125772550,0sleep20-21swapper/222:18:572
302612520,1sleep630234-21sshd22:47:206
162422500,0sleep00-21swapper/023:18:460
243292490,0sleep09-21ksoftirqd/022:46:420
223502480,0sleep50-21swapper/521:49:295
139332480,0sleep30-21swapper/321:32:213
173572470,0sleep51060399cyclictest21:29:195
272422460,0sleep30-21swapper/322:10:173
158312460,0sleep00-21swapper/000:14:200
118772460,0sleep60-21swapper/600:24:196
86872450,1sleep7699-21avahi-daemon21:15:437
285282450,0sleep00-21swapper/023:03:560
285282450,0sleep00-21swapper/023:03:560
1018624525,4sleep50-21swapper/519:05:305
273902440,0sleep00-21swapper/022:57:080
263352440,0sleep50-21swapper/523:35:415
215242440,0sleep10-21swapper/123:41:451
145242440,0sleep70-21swapper/722:52:267
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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