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2026-07-29 - 18:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Wed Jul 29, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158242940,1sleep315815-21sshd09:22:403
252632870,2sleep11980199cyclictest12:24:351
113312780,2sleep51981799cyclictest11:34:495
113312780,2sleep51981799cyclictest11:34:495
121362760,7sleep09-21ksoftirqd/012:00:150
37892740,1sleep73786-21sshd10:49:027
172092700,0sleep50-21swapper/511:46:035
38502570,0sleep10-21swapper/112:06:571
190462550,0sleep40-21swapper/412:20:384
168492550,0sleep60-21swapper/612:15:036
157792540,0sleep10-21swapper/110:24:211
101222500,0sleep00-21swapper/009:36:470
279362480,0sleep127899-21sshd10:01:231
1962724825,8sleep50-21swapper/507:05:265
1957424825,9sleep00-21swapper/007:04:410
158622480,2sleep0111rcuc/011:47:420
120412480,0sleep30-21swapper/310:49:303
265712470,0sleep70-21swapper/711:26:347
265712470,0sleep70-21swapper/711:26:347
20692470,0sleep20-21swapper/212:17:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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