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2025-05-03 - 01:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Fri May 02, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
261792730,0sleep50-21swapper/509:31:435
179802660,1sleep717975-21sshd09:43:147
59822540,1sleep341-21ksoftirqd/310:41:563
61892530,0sleep10-21swapper/111:44:331
50842520,0sleep00-21swapper/010:07:260
1789625126,9sleep70-21swapper/706:57:237
15472480,0sleep60-21swapper/612:19:306
42982470,0sleep70-21swapper/707:31:577
42982470,0sleep70-21swapper/707:31:577
104772470,0sleep00-21swapper/010:45:300
60912440,0sleep56066-21sshd11:57:035
262512440,2sleep31847299cyclictest12:13:513
203102440,1sleep220308-21bash10:21:372
225172430,0sleep10-21swapper/109:24:501
51532420,0sleep70-21swapper/712:24:527
293602420,0sleep60-21swapper/612:16:426
259902420,0sleep30-21swapper/310:18:583
240532420,0sleep20-21swapper/211:23:362
229072420,0sleep40-21swapper/409:43:434
60002410,0sleep0763-21runrttasks11:39:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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