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2025-08-21 - 22:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Thu Aug 21, 2025 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29738991690,168cyclictest5369-21kworker/7:110:18:497
29714991110,111cyclictest23451-21kworker/4:310:18:494
14252960,0sleep1231rcuc/110:59:321
266982700,0sleep10-21swapper/110:20:161
2934525328,8sleep40-21swapper/406:55:194
81972520,0sleep70-21swapper/710:54:017
2921225026,8sleep60-21swapper/606:53:296
158402480,0sleep70-21swapper/709:43:467
106802460,0sleep30-21swapper/310:12:413
63892450,0sleep40-21swapper/411:35:074
304332450,0sleep3763-21runrttasks10:56:143
231782450,0sleep30-21swapper/309:16:033
228732450,0sleep60-21swapper/609:12:536
200512450,0sleep5763-21runrttasks11:43:495
190882450,0sleep60-21swapper/611:10:186
139792440,0sleep40-21swapper/409:02:504
213712430,0sleep60-21swapper/612:24:276
180352430,0sleep20-21swapper/211:13:032
120382430,0sleep00-21swapper/012:03:300
72662420,0sleep60-21swapper/610:37:356
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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