You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-26 - 16:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 25 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot5.osadl.org.osadl.org (updated Thu Feb 26, 2026 12:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
151154470,0ktimers/0114571sleep07:07:360
123619949433,0cyclictest28999-21chrt12:38:410
1514810,0ktimers/088811sleep10:09:520
1514730,0ktimers/0192461sleep11:25:430
1514650,0ktimers/0277331sleep12:28:410
123619946531,0cyclictest6432-21munin-node09:52:300
123619946329,0cyclictest26331-21apt-get12:18:180
1514610,0ktimers/047161sleep09:40:470
1514540,0ktimers/054071sleep09:46:380
1514540,0ktimers/039911sleep09:34:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional