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2026-01-25 - 00:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 25 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot5.osadl.org.osadl.org (updated Sat Jan 24, 2026 12:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
151152610,0ktimers/018431sleep07:08:190
525504760,0irq/11-sym53c8x130250irq/15-NE200010:10:570
1514610,0ktimers/060261sleep07:36:020
525504520,0irq/11-sym53c8x130250irq/15-NE200012:12:280
1302504440,0irq/15-NE200052550irq/11-sym53c8xx08:12:220
1514310,0ktimers/078381sleep11:06:010
525504300,0irq/11-sym53c8x130250irq/15-NE200010:11:120
1514150,0ktimers/0102471sleep11:23:180
525504130,0irq/11-sym53c8x130250irq/15-NE200012:16:480
1514040,0ktimers/07741sleep10:17:080
1514010,0ktimers/0149391sleep11:57:230
1513980,0ktimers/057441sleep07:33:050
525503910,0irq/11-sym53c8x130250irq/15-NE200011:30:470
1513670,0ktimers/0200661sleep12:32:310
1302503660,0irq/15-NE200052550irq/11-sym53c8xx08:07:330
1513650,0ktimers/046721sleep07:26:490
1302503570,0irq/15-NE200015875-21kworker/u4:2+xprtiod12:26:100
1302503560,0irq/15-NE200032761-21kworker/u4:2+xprtiod10:22:300
1302503520,0irq/15-NE200052550irq/11-sym53c8xx11:32:140
1513470,0ktimers/078941sleep11:06:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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