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2026-02-26 - 09:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack4slot1.osadl.org (updated Wed Feb 25, 2026 20:06:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
251399196190,4cyclictest5301-21find19:56:350
251399196190,4cyclictest5301-21find19:56:350
2063921330,3chrt0-21swapper/219:32:492
2063921330,3chrt0-21swapper/219:32:492
656421310,2chrt0-21swapper/319:37:453
656421310,2chrt0-21swapper/319:37:453
656421310,2chrt0-21swapper/319:37:453
1525021220,3sleep20-21swapper/219:16:302
1525021220,3sleep20-21swapper/219:16:302
374921210,4sleep23744-21tr19:15:252
374921210,4sleep23744-21tr19:15:252
185221190,3sleep30-21swapper/319:56:163
185221190,3sleep30-21swapper/319:56:163
2325421180,2sleep3321rcuc/319:36:163
2325421180,2sleep3321rcuc/319:36:163
3165121170,3chrt0-21swapper/319:27:353
3165121170,3chrt0-21swapper/319:27:353
2157121150,3chrt21570-21benchlatencyplo19:29:472
2157121150,3chrt21570-21benchlatencyplo19:29:472
544121140,4sleep15424-21sort19:56:351
544121140,4sleep15424-21sort19:56:351
3224421130,2chrt0-21swapper/319:15:023
3224421130,2chrt0-21swapper/319:15:023
797821120,3sleep17976-21ts2lt19:47:201
797821120,3sleep17976-21ts2lt19:47:201
1940021070,2sleep1211ksoftirqd/119:35:541
1940021070,2sleep1211ksoftirqd/119:35:541
1269921030,11sleep333-21ksoftirqd/319:51:013
1269921030,11sleep333-21ksoftirqd/319:51:013
3268621020,3chrt0-21swapper/119:27:411
3268621020,3chrt0-21swapper/119:27:411
2849021020,3sleep228488-21cut19:55:432
2849021020,3sleep228488-21cut19:55:432
2980321010,3sleep10-21swapper/119:14:481
2980321010,3sleep10-21swapper/119:14:481
43992980,2sleep00-21swapper/019:46:590
43992980,2sleep00-21swapper/019:46:590
99822970,3chrt0-21swapper/319:44:253
99822970,3chrt0-21swapper/319:44:253
326602970,4sleep232657-21tr19:43:272
326602970,4sleep232657-21tr19:43:272
183542970,2chrt0-21swapper/319:16:473
183542970,2chrt0-21swapper/319:16:473
202652930,4sleep220259-21benchlatencyplo19:23:182
135122820,2sleep05423-21benchlatencyplo19:44:470
135122820,2sleep05423-21benchlatencyplo19:44:470
29562810,3sleep121-21ksoftirqd/119:21:361
40732760,2sleep30-21swapper/319:21:423
309442750,3sleep130942-21ts2lt19:18:021
309442750,3sleep130942-21ts2lt19:18:021
288032700,1sleep228964-21benchlatencyplo19:39:582
288032700,1sleep228964-21benchlatencyplo19:39:582
288032700,1sleep228964-21benchlatencyplo19:39:582
123282690,7sleep121-21ksoftirqd/119:44:391
123282690,7sleep121-21ksoftirqd/119:44:391
188772610,1chrt12-21ksoftirqd/019:51:350
188772610,1chrt12-21ksoftirqd/019:51:350
88122590,3sleep20-21swapper/219:47:262
88122590,3sleep20-21swapper/219:47:262
279582560,3sleep121-21ksoftirqd/119:39:521
279582560,3sleep121-21ksoftirqd/119:39:521
279582560,3sleep121-21ksoftirqd/119:39:521
12082537,31sleep01313-21benchlatencyplo19:11:580
12082537,31sleep01313-21benchlatencyplo19:11:580
38132510,2sleep03967-21benchlatencyplo19:18:340
38132510,2sleep03967-21benchlatencyplo19:18:340
86372490,2sleep08795-21benchlatencyplo19:25:230
249622480,2sleep125139-21benchlatencyplo19:55:231
249622480,2sleep125139-21benchlatencyplo19:55:231
311612460,3sleep00-21swapper/019:33:510
311612460,3sleep00-21swapper/019:33:510
223472460,2sleep022345-21benchlatencyplo19:26:390
223472460,2sleep022345-21benchlatencyplo19:26:390
252699390,4cyclictest2438-21benchlatencyplo19:56:192
252699390,4cyclictest2438-21benchlatencyplo19:56:192
275322340,2sleep027700-21ts2lt19:36:380
275322340,2sleep027700-21ts2lt19:36:380
275322340,2sleep027700-21ts2lt19:36:380
252699341,3cyclictest0-21swapper/220:01:312
252699341,3cyclictest0-21swapper/220:01:312
252199227,4cyclictest0-21swapper/120:02:361
252199227,4cyclictest0-21swapper/120:02:361
2531992014,4cyclictest321rcuc/320:03:493
2531992014,4cyclictest321rcuc/320:03:493
2531991914,3cyclictest321rcuc/319:59:183
2531991914,3cyclictest321rcuc/319:59:183
251399171,3cyclictest131rcu_preempt20:05:500
251399171,3cyclictest131rcu_preempt20:05:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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