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2026-03-03 - 15:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot1.osadl.org (updated Tue Mar 03, 2026 07:26:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
169662930,2chrt33-21ksoftirqd/307:11:383
169662930,2chrt33-21ksoftirqd/307:11:383
173262490,3sleep016040-21ls07:11:440
173262490,3sleep016040-21ls07:11:440
170822430,2sleep116040-21ls07:11:411
170822430,2sleep116040-21ls07:11:411
17576992419,3cyclictest213972sleep207:21:392
1757599241,6cyclictest73-21kswapd007:16:371
1757599241,6cyclictest73-21kswapd007:16:371
1757499231,4cyclictest131rcu_preempt07:16:370
1757499231,4cyclictest131rcu_preempt07:16:370
1757699218,4cyclictest131rcu_preempt07:16:382
1757699218,4cyclictest131rcu_preempt07:16:382
1757499202,2cyclictest131rcu_preempt07:21:390
1757699181,14cyclictest17965-21idleruntime-cro07:16:152
1757699181,14cyclictest17965-21idleruntime-cro07:16:152
17575991812,4cyclictest0-21swapper/107:21:341
1757799122,7cyclictest0-21swapper/307:16:263
1757799122,7cyclictest0-21swapper/307:16:263
1757799121,10cyclictest0-21swapper/307:21:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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