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2026-03-01 - 07:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot1.osadl.org (updated Sat Feb 28, 2026 19:46:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35882550,3sleep00-21swapper/019:16:390
35882550,3sleep00-21swapper/019:16:390
34412350,3sleep30-21swapper/319:16:383
34412350,3sleep30-21swapper/319:16:383
16622311,24sleep30-21swapper/319:11:413
16622311,24sleep30-21swapper/319:11:413
16202316,15sleep00-21swapper/019:11:220
16202316,15sleep00-21swapper/019:11:220
16682265,14sleep20-21swapper/219:11:442
16682265,14sleep20-21swapper/219:11:442
171699228,11cyclictest2450-21fschecks_count19:16:262
171699228,11cyclictest2450-21fschecks_count19:16:262
171499201,14cyclictest6103-21ls19:31:280
171499201,14cyclictest6103-21ls19:31:280
16602204,10sleep11425-21ls19:11:391
16602204,10sleep11425-21ls19:11:391
171699198,9cyclictest5485-21cat19:31:172
171699198,9cyclictest5485-21cat19:31:172
171699191,10cyclictest695-21runrttasks19:33:022
171699191,10cyclictest695-21runrttasks19:33:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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