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2026-02-08 - 22:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot1.osadl.org (updated Sun Feb 08, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1484821170,4chrt0-21swapper/012:32:410
1484821170,4chrt0-21swapper/012:32:410
1072421170,3sleep30-21swapper/310:52:293
1072421170,3sleep30-21swapper/310:52:293
200521140,3sleep00-21swapper/012:20:480
200521140,3sleep00-21swapper/012:20:480
601621090,2sleep30-21swapper/310:16:083
601621090,2sleep30-21swapper/310:16:083
630221080,3sleep00-21swapper/007:46:110
630221080,3sleep00-21swapper/007:46:110
2283621020,4sleep30-21swapper/311:05:313
2283621020,4sleep30-21swapper/311:05:313
210532950,3chrt0-21swapper/012:06:450
210532950,3chrt0-21swapper/012:06:450
197552950,2sleep227-21ksoftirqd/209:25:592
189822930,3chrt0-21swapper/309:25:083
322002880,3sleep0151rcuc/009:37:110
322002880,3sleep0151rcuc/009:37:110
36602810,3chrt0-21swapper/309:41:123
36602810,3chrt0-21swapper/309:41:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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