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2026-02-24 - 15:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot1.osadl.org (updated Tue Feb 24, 2026 12:45:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2745623420,2sleep2131rcu_preempt07:11:332
1017221280,3sleep10-21swapper/111:51:561
2895121070,3sleep10-21swapper/107:16:181
2895121070,3sleep10-21swapper/107:16:181
1368321060,2sleep00-21swapper/011:56:170
1368321060,2sleep00-21swapper/011:56:170
1368321060,2sleep00-21swapper/011:56:170
1083121060,3chrt0-21swapper/209:13:502
1083121060,3chrt0-21swapper/209:13:502
277002720,2sleep30-21swapper/310:01:333
60602670,2sleep10-21swapper/109:06:211
60602670,2sleep10-21swapper/109:06:211
104072640,3sleep10-21swapper/109:13:161
104072640,3sleep10-21swapper/109:13:161
178282630,3sleep10-21swapper/112:31:271
92602600,2sleep30-21swapper/309:44:253
92602600,2sleep30-21swapper/309:44:253
325522590,2sleep132557-21latency_hist07:26:071
325522590,2sleep132557-21latency_hist07:26:071
243872570,3sleep10-21swapper/110:31:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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