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2026-02-26 - 03:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot1.osadl.org (updated Wed Feb 25, 2026 20:06:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
251399196190,4cyclictest5301-21find19:56:350
251399196190,4cyclictest5301-21find19:56:350
2063921330,3chrt0-21swapper/219:32:492
2063921330,3chrt0-21swapper/219:32:492
656421310,2chrt0-21swapper/319:37:453
656421310,2chrt0-21swapper/319:37:453
656421310,2chrt0-21swapper/319:37:453
1525021220,3sleep20-21swapper/219:16:302
1525021220,3sleep20-21swapper/219:16:302
374921210,4sleep23744-21tr19:15:252
374921210,4sleep23744-21tr19:15:252
185221190,3sleep30-21swapper/319:56:163
185221190,3sleep30-21swapper/319:56:163
2325421180,2sleep3321rcuc/319:36:163
2325421180,2sleep3321rcuc/319:36:163
3165121170,3chrt0-21swapper/319:27:353
3165121170,3chrt0-21swapper/319:27:353
2157121150,3chrt21570-21benchlatencyplo19:29:472
2157121150,3chrt21570-21benchlatencyplo19:29:472
544121140,4sleep15424-21sort19:56:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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