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2026-02-21 - 14:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot1.osadl.org (updated Sat Feb 21, 2026 12:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3017921250,2sleep10-21swapper/109:46:291
3017921250,2sleep10-21swapper/109:46:291
449921240,2sleep2261rcuc/212:01:222
449921240,2sleep2261rcuc/212:01:222
804421090,6sleep28046-21ssh09:56:262
804421090,6sleep28046-21ssh09:56:262
1376621010,3sleep30-21swapper/310:35:023
1376621010,3sleep30-21swapper/310:35:023
2175921000,2sleep30-21swapper/307:31:283
105042980,2sleep20-21swapper/211:36:102
105042980,2sleep20-21swapper/211:36:102
287712960,3sleep10-21swapper/109:46:051
287712960,3sleep10-21swapper/109:46:051
270692940,3sleep214499-21cyclictest09:43:442
270692940,3sleep214499-21cyclictest09:43:442
301662910,2chrt30164-21rm09:46:280
301662910,2chrt30164-21rm09:46:280
113902900,4sleep30-21swapper/312:40:383
113902900,4sleep30-21swapper/312:40:383
113902900,4sleep30-21swapper/312:40:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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