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2026-03-09 - 04:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot2.osadl.org (updated Mon Mar 09, 2026 00:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
126312202185,12sleep10-21swapper/119:08:201
124542191174,12sleep00-21swapper/019:06:020
125612189172,12sleep30-21swapper/319:07:253
124882171152,14sleep20-21swapper/219:06:282
254582460,0sleep10-21swapper/122:52:231
93782440,0sleep10-21swapper/121:56:501
62852440,0sleep00-21swapper/022:10:580
45032430,0sleep00-21swapper/000:01:310
291312140,0sleep20-21swapper/221:35:122
129619993,3cyclictest7385-21ssh21:25:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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