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2025-12-09 - 08:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot2.osadl.org (updated Tue Dec 09, 2025 00:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
176132200183,12sleep10-21swapper/119:07:151
178032186169,12sleep00-21swapper/019:09:440
174892183166,12sleep30-21swapper/319:05:413
177532123107,12sleep20-21swapper/219:09:052
99762460,1sleep09979-21ntp_kernel_pll_19:55:170
128522450,0sleep20-21swapper/222:14:242
322312130,0sleep30-21swapper/322:55:483
96062120,0sleep20-21swapper/200:39:402
191652110,0sleep20-21swapper/200:27:432
1801699103,2cyclictest12859-21hddtemp_smartct21:25:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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