You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-06 - 12:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot2.osadl.org (updated Fri Feb 06, 2026 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
236572197182,10sleep10-21swapper/119:09:201
234952194177,12sleep30-21swapper/319:07:133
236142185168,12sleep00-21swapper/019:08:470
235242182164,13sleep20-21swapper/219:07:372
115022480,0sleep10-21swapper/119:45:221
293402460,0sleep10-21swapper/123:36:221
8392450,0sleep10-21swapper/121:31:361
159862440,0sleep30-21swapper/322:59:053
118372440,0sleep30-21swapper/321:21:083
157592170,0sleep10-21swapper/121:23:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional