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2026-05-05 - 06:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot2.osadl.org (updated Tue May 05, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
199582202187,11sleep10-21swapper/119:09:521
199582202187,11sleep10-21swapper/119:09:521
197162186169,12sleep30-21swapper/319:06:443
197162186169,12sleep30-21swapper/319:06:443
199572179161,13sleep00-21swapper/019:09:510
199572179161,13sleep00-21swapper/019:09:510
19897211093,13sleep20-21swapper/219:09:052
19897211093,13sleep20-21swapper/219:09:052
184972500,0sleep30-21swapper/300:20:403
273532490,0sleep30-21swapper/322:18:323
159762470,0sleep20-21swapper/222:28:522
19242460,0sleep30-21swapper/321:18:523
300542420,0sleep330056-21unixbench_singl20:30:193
158092420,0sleep10-21swapper/121:56:461
167192410,0sleep20-21swapper/221:57:182
201849990,8cyclictest15609-21diskmemload00:00:123
14195290,0sleep10-21swapper/120:00:151
201719981,1cyclictest3-21ksoftirqd/000:31:050
18525280,0sleep00-21swapper/021:58:250
16924280,0sleep00-21swapper/000:20:130
201719975,2cyclictest41ktimersoftd/023:10:130
201719972,2cyclictest3-21ksoftirqd/022:23:280
201719972,1cyclictest3-21ksoftirqd/020:20:000
201719970,6cyclictest0-21swapper/023:25:130
201719970,1cyclictest3-21ksoftirqd/021:10:010
201719970,1cyclictest3-21ksoftirqd/019:50:180
201719970,0cyclictest81rcu_preempt23:35:000
201849960,5cyclictest14899-21apt-get23:00:133
201789960,5cyclictest0-21swapper/222:30:112
201759961,3cyclictest0-21swapper/123:25:121
201719964,0cyclictest3-21ksoftirqd/000:13:020
201719963,2cyclictest3-21ksoftirqd/021:16:480
201719963,0cyclictest3-21ksoftirqd/000:25:310
201719963,0cyclictest3-21ksoftirqd/000:18:560
201719962,2cyclictest3-21ksoftirqd/023:32:390
201719962,2cyclictest3-21ksoftirqd/023:24:270
201719962,2cyclictest3-21ksoftirqd/022:42:200
201719962,2cyclictest3-21ksoftirqd/022:38:020
201719962,2cyclictest3-21ksoftirqd/022:15:310
201719962,2cyclictest3-21ksoftirqd/021:50:160
201719962,2cyclictest3-21ksoftirqd/000:36:420
201719962,0cyclictest3-21ksoftirqd/022:02:330
201719961,1cyclictest3-21ksoftirqd/023:15:010
201719961,1cyclictest3-21ksoftirqd/020:54:590
201719961,1cyclictest3-21ksoftirqd/020:10:000
201719961,1cyclictest3-21ksoftirqd/000:00:140
201719961,1cyclictest0-21swapper/021:30:230
201719961,0cyclictest0-21swapper/021:27:120
201719960,5cyclictest30707-21hddtemp_smartct23:55:130
201719960,2cyclictest3-21ksoftirqd/023:43:320
201719960,2cyclictest3-21ksoftirqd/000:05:170
201719960,1cyclictest3-21ksoftirqd/022:50:160
201719960,1cyclictest0-21swapper/022:13:400
27109250,0sleep10-21swapper/123:37:261
201849955,0cyclictest0-21swapper/322:55:203
201849950,5cyclictest0-21swapper/322:53:093
201849950,4cyclictest11093-21tr21:00:123
201849950,4cyclictest0-21swapper/319:35:123
201789950,5cyclictest0-21swapper/200:10:592
201789950,4cyclictest57150irq/125-eth023:20:112
201789950,0cyclictest0-21swapper/221:25:512
201759952,2cyclictest0-21swapper/122:40:101
201759951,3cyclictest0-21swapper/120:15:111
201759951,3cyclictest0-21swapper/119:40:111
201759951,3cyclictest0-21swapper/119:25:121
201759951,2cyclictest0-21swapper/123:45:111
201759951,2cyclictest0-21swapper/123:15:121
201759951,2cyclictest0-21swapper/122:30:101
201759951,2cyclictest0-21swapper/119:20:121
201759950,5cyclictest0-21swapper/100:37:471
201759950,2cyclictest0-21swapper/122:20:131
201719954,0cyclictest3-21ksoftirqd/020:45:140
201719954,0cyclictest3-21ksoftirqd/019:20:200
201719952,2cyclictest3-21ksoftirqd/022:25:370
201719952,2cyclictest3-21ksoftirqd/021:43:310
201719952,1cyclictest3-21ksoftirqd/022:30:130
201719952,1cyclictest3-21ksoftirqd/022:06:020
201719952,1cyclictest3-21ksoftirqd/019:40:140
201719952,0cyclictest3-21ksoftirqd/019:30:140
201719951,2cyclictest3-21ksoftirqd/023:05:080
201719951,2cyclictest3-21ksoftirqd/022:55:380
201719951,2cyclictest3-21ksoftirqd/021:45:170
201719951,2cyclictest3-21ksoftirqd/021:20:180
201719951,2cyclictest3-21ksoftirqd/021:05:150
201719951,2cyclictest3-21ksoftirqd/020:00:200
201719951,1cyclictest81rcu_preempt22:45:200
201719951,1cyclictest3-21ksoftirqd/021:35:140
201719951,1cyclictest11505-21fschecks_count21:00:130
201719951,0cyclictest81rcu_preempt19:10:130
201719950,5cyclictest0-21swapper/023:50:110
201719950,4cyclictest3-21ksoftirqd/020:35:130
201719950,1cyclictest3-21ksoftirqd/023:45:120
201719950,1cyclictest3-21ksoftirqd/023:00:170
201719950,1cyclictest3-21ksoftirqd/020:25:110
201719950,1cyclictest0-21swapper/020:10:110
201719950,0cyclictest0-21swapper/019:15:010
201849944,0cyclictest0-21swapper/321:26:173
201849941,2cyclictest0-21swapper/323:40:103
201849940,4cyclictest5073-21grep20:45:203
201849940,4cyclictest15609-21diskmemload23:50:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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