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2026-09-02 - 18:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot2.osadl.org (updated Wed Sep 02, 2026 12:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
306792200183,12sleep10-21swapper/107:05:591
306612198181,12sleep30-21swapper/307:05:443
285282181162,13sleep00-21swapper/007:05:020
309832156142,10sleep20-21swapper/207:09:542
187552440,0sleep10-21swapper/112:05:131
75882430,0sleep20-21swapper/211:26:062
154272150,0sleep30-21swapper/311:46:403
3116699102,3cyclictest22307-21perf09:00:000
311669995,2cyclictest3-21ksoftirqd/009:45:190
311669993,1cyclictest3-21ksoftirqd/011:10:210
311669982,3cyclictest27453-21perf09:10:010
311669980,2cyclictest3-21ksoftirqd/011:15:130
311799970,2cyclictest0-21swapper/311:57:523
311669975,0cyclictest3-21ksoftirqd/011:50:130
311669975,0cyclictest3-21ksoftirqd/011:30:140
311669975,0cyclictest3-21ksoftirqd/011:00:150
311669975,0cyclictest3-21ksoftirqd/010:45:000
311669975,0cyclictest3-21ksoftirqd/008:30:000
311669973,1cyclictest3-21ksoftirqd/010:15:150
311669971,1cyclictest3-21ksoftirqd/012:10:010
311669971,1cyclictest3-21ksoftirqd/009:25:190
311669971,1cyclictest3-21ksoftirqd/008:35:200
311669970,1cyclictest3-21ksoftirqd/011:55:140
311669970,1cyclictest3-21ksoftirqd/010:55:160
311669970,1cyclictest0-21swapper/012:15:140
311669966,0cyclictest3-21ksoftirqd/008:50:010
311669965,0cyclictest3-21ksoftirqd/011:05:190
311669965,0cyclictest3-21ksoftirqd/010:25:200
311669965,0cyclictest3-21ksoftirqd/009:50:200
311669965,0cyclictest3-21ksoftirqd/009:40:010
311669965,0cyclictest3-21ksoftirqd/009:20:150
311669965,0cyclictest3-21ksoftirqd/008:40:170
311669965,0cyclictest3-21ksoftirqd/007:30:140
311669964,0cyclictest3-21ksoftirqd/012:00:120
311669964,0cyclictest3-21ksoftirqd/010:10:120
311669964,0cyclictest3-21ksoftirqd/010:05:140
311669964,0cyclictest3-21ksoftirqd/010:00:180
311669964,0cyclictest3-21ksoftirqd/009:30:130
311669964,0cyclictest3-21ksoftirqd/009:15:110
311669964,0cyclictest3-21ksoftirqd/008:45:130
311669964,0cyclictest3-21ksoftirqd/008:20:140
311669963,2cyclictest3-21ksoftirqd/011:45:170
311669963,1cyclictest3-21ksoftirqd/010:20:110
311669963,0cyclictest3-21ksoftirqd/007:35:160
311669962,0cyclictest81rcu_preempt10:30:130
311669962,0cyclictest81rcu_preempt09:55:120
311669962,0cyclictest81rcu_preempt09:10:140
311669961,1cyclictest3-21ksoftirqd/011:20:160
311669961,1cyclictest3-21ksoftirqd/007:10:010
311669960,2cyclictest3-21ksoftirqd/012:10:160
311669960,1cyclictest3-21ksoftirqd/012:30:090
311669960,1cyclictest3-21ksoftirqd/012:25:110
311669960,1cyclictest3-21ksoftirqd/012:25:000
311669960,1cyclictest3-21ksoftirqd/011:39:120
311669960,1cyclictest3-21ksoftirqd/010:52:100
311669960,0cyclictest0-21swapper/007:15:020
311799951,3cyclictest0-21swapper/308:30:113
311799951,2cyclictest0-21swapper/311:10:123
311799950,5cyclictest0-21swapper/311:01:173
311799950,5cyclictest0-21swapper/310:21:513
311799950,5cyclictest0-21swapper/309:25:153
311799950,5cyclictest0-21swapper/308:26:463
311799950,5cyclictest0-21swapper/307:38:593
311799950,4cyclictest8294-21df10:05:133
311799950,1cyclictest0-21swapper/312:09:163
311799950,1cyclictest0-21swapper/311:06:083
311799950,0cyclictest0-21swapper/312:17:213
311799950,0cyclictest0-21swapper/309:52:363
311799950,0cyclictest0-21swapper/309:47:473
311759955,0cyclictest0-21swapper/210:32:262
311759955,0cyclictest0-21swapper/210:06:142
311759950,5cyclictest0-21swapper/212:32:552
311759950,5cyclictest0-21swapper/210:53:322
311759950,5cyclictest0-21swapper/210:28:132
311759950,4cyclictest18215-21ssh12:05:122
311759950,4cyclictest0-21swapper/209:25:132
311709951,2cyclictest0-21swapper/110:15:121
311709951,2cyclictest0-21swapper/109:55:141
311709951,2cyclictest0-21swapper/109:50:111
311709951,2cyclictest0-21swapper/108:35:131
311709950,5cyclictest0-21swapper/111:47:111
311709950,5cyclictest0-21swapper/110:46:491
311709950,5cyclictest0-21swapper/110:23:321
311709950,5cyclictest0-21swapper/110:13:381
311669955,0cyclictest41ktimersoftd/007:55:180
311669954,0cyclictest3-21ksoftirqd/010:45:120
311669954,0cyclictest3-21ksoftirqd/007:45:130
311669954,0cyclictest3-21ksoftirqd/007:20:150
311669953,2cyclictest41ktimersoftd/008:15:170
311669953,2cyclictest3-21ksoftirqd/007:50:140
311669953,0cyclictest3-21ksoftirqd/011:25:120
311669953,0cyclictest3-21ksoftirqd/009:00:120
311669952,0cyclictest81rcu_preempt07:40:200
311669952,0cyclictest3-21ksoftirqd/008:30:110
311669952,0cyclictest3-21ksoftirqd/008:10:140
311669951,0cyclictest3-21ksoftirqd/012:35:120
311669950,2cyclictest3-21ksoftirqd/010:35:050
311669950,1cyclictest3-21ksoftirqd/009:40:130
311669950,1cyclictest3-21ksoftirqd/008:05:130
311669950,1cyclictest25373-21fschecks_count08:00:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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