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2026-03-01 - 09:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot2.osadl.org (updated Sun Mar 01, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
241972189172,12sleep30-21swapper/319:06:093
241762185167,13sleep20-21swapper/219:05:522
241892184168,11sleep00-21swapper/019:06:030
244872178160,12sleep10-21swapper/119:09:521
115372500,0sleep00-21swapper/022:54:300
55182460,0sleep20-21swapper/223:23:062
322102450,0sleep30-21swapper/321:14:083
78882440,0sleep10-21swapper/122:52:141
33552410,0sleep00-21swapper/023:37:570
98982390,0sleep10-21swapper/121:34:561
313772140,0sleep00-21swapper/022:32:030
295752140,0sleep10-21swapper/122:00:061
233872110,0sleep30-21swapper/323:31:353
123552100,0sleep20-21swapper/222:54:592
1463290,0sleep30-21swapper/322:01:373
246719981,3cyclictest11973-21perf20:25:000
246789960,5cyclictest26428-21ntp_states22:45:193
246719962,4cyclictest18985-21munin-run20:50:000
246719960,3cyclictest3470-21munin-run19:50:010
246719960,3cyclictest21900-21perf21:25:010
246789955,0cyclictest12335-21kworker/3:221:55:063
246789955,0cyclictest12335-21kworker/3:220:47:563
246789953,1cyclictest2070-21ssh00:25:123
246789950,5cyclictest0-21swapper/323:15:243
246789950,4cyclictest9969-21perl21:50:133
246789950,4cyclictest0-21swapper/300:00:103
246749955,0cyclictest0-21swapper/200:01:192
246749950,5cyclictest0-21swapper/223:05:452
246749950,5cyclictest0-21swapper/222:12:132
246749950,5cyclictest0-21swapper/221:16:022
246749950,5cyclictest0-21swapper/200:11:482
246749950,4cyclictest17057-21munin-run23:45:002
246749950,0cyclictest0-21swapper/223:15:292
246729951,3cyclictest0-21swapper/121:15:121
246729951,2cyclictest0-21swapper/122:40:121
246729951,2cyclictest0-21swapper/120:15:131
246729951,2cyclictest0-21swapper/100:30:121
246719954,1cyclictest0-21swapper/021:46:150
246719952,3cyclictest0-21swapper/000:00:040
246719951,4cyclictest57250irq/130-eth021:35:570
246719950,5cyclictest28720-21ssh23:34:520
246719950,5cyclictest21562-21memory21:00:170
246719950,5cyclictest0-21swapper/023:15:490
246719950,5cyclictest0-21swapper/023:11:220
246719950,5cyclictest0-21swapper/022:25:060
246719950,5cyclictest0-21swapper/021:54:010
246719950,4cyclictest2457-21head23:05:210
246719950,4cyclictest15692-21basename20:40:010
246719950,3cyclictest28511-21ssh21:59:370
246719950,1cyclictest0-21swapper/023:44:170
246719950,1cyclictest0-21swapper/022:24:170
246719950,1cyclictest0-21swapper/021:42:450
4532240,3sleep20-21swapper/222:19:332
26624240,3sleep30-21swapper/323:01:143
246789944,0cyclictest5348-21ssh22:50:413
246789944,0cyclictest12335-21kworker/3:220:36:453
246789944,0cyclictest0-21swapper/323:20:393
246789944,0cyclictest0-21swapper/323:10:093
246789943,1cyclictest22484-21perl00:35:153
246789943,1cyclictest14763-21cut00:15:163
246789942,1cyclictest5818-21ssh00:10:283
246789942,1cyclictest26517-21ssh22:30:123
246789942,1cyclictest18346-21ssh22:25:203
246789942,1cyclictest11659-21ssh23:57:483
246789941,3cyclictest481-21nscd21:40:523
246789940,4cyclictest20132-21ssh22:10:303
246789940,4cyclictest14772-21ssh00:31:003
246789940,4cyclictest0-21swapper/323:05:103
246789940,4cyclictest0-21swapper/322:55:123
246789940,4cyclictest0-21swapper/322:40:113
246789940,4cyclictest0-21swapper/322:35:123
246789940,4cyclictest0-21swapper/322:08:433
246789940,4cyclictest0-21swapper/321:45:013
246789940,4cyclictest0-21swapper/321:35:123
246789940,4cyclictest0-21swapper/321:30:123
246789940,4cyclictest0-21swapper/321:20:113
246789940,4cyclictest0-21swapper/321:15:113
246789940,4cyclictest0-21swapper/320:15:133
246789940,4cyclictest0-21swapper/319:30:123
246789940,4cyclictest0-21swapper/319:30:123
246789940,4cyclictest0-21swapper/300:20:113
246789940,3cyclictest5559-21ssh22:20:023
246789940,3cyclictest30405-21ssh23:50:363
246789940,3cyclictest29336-21ssh23:35:063
246789940,3cyclictest28769-21ssh00:05:503
246789940,3cyclictest27750-21ssh22:15:013
246789940,3cyclictest25505-21irqstats19:15:013
246789940,3cyclictest24731-21ssh21:25:303
246789940,3cyclictest20831-21chrt23:45:583
246789940,3cyclictest20432-21sed21:00:003
246789940,3cyclictest13380-21ssh23:26:413
246789940,1cyclictest6431-21ntp_states20:00:173
246749944,0cyclictest0-21swapper/223:46:202
246749943,1cyclictest8018-21sh20:10:002
246749943,1cyclictest26287-21tail22:45:182
246749941,3cyclictest23868-21cut23:00:142
246749940,4cyclictest5888-21ssh22:20:132
246749940,4cyclictest23338-21diskmemload21:58:582
246749940,4cyclictest0-21swapper/223:37:142
246749940,4cyclictest0-21swapper/223:10:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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