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2026-01-26 - 03:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot2.osadl.org (updated Mon Jan 26, 2026 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
254442197182,10sleep10-21swapper/119:09:441
251342196179,12sleep30-21swapper/319:05:453
251682194174,14sleep00-21swapper/019:06:110
232382178160,13sleep20-21swapper/219:05:042
132562500,0sleep30-21swapper/320:50:173
109262490,0sleep00-21swapper/023:25:130
310352460,0sleep10-21swapper/100:22:211
82982430,0sleep10-21swapper/100:10:531
67172430,0sleep10-21swapper/122:04:421
243852420,0sleep20-21swapper/221:25:482
86182110,0sleep30-21swapper/323:40:003
28972110,0sleep20-21swapper/222:18:132
139322110,0sleep10-21swapper/121:20:511
31006290,0sleep30-21swapper/322:31:273
256909970,3cyclictest14775-21sh22:40:010
256909970,3cyclictest14089-21perf19:50:010
257049963,1cyclictest0-21swapper/321:30:113
257049960,6cyclictest0-21swapper/323:14:373
257039960,6cyclictest14046-21rm00:14:262
256909960,5cyclictest0-21swapper/020:15:110
256909960,3cyclictest12996-21awk00:30:010
13344260,0sleep00-21swapper/000:30:050
257049955,0cyclictest29224-21kworker/3:020:48:583
257049955,0cyclictest29224-21kworker/3:020:26:363
257049955,0cyclictest0-21swapper/322:15:593
257049951,3cyclictest814-21snmpd23:59:403
257049950,5cyclictest0-21swapper/320:20:103
257049950,5cyclictest0-21swapper/300:06:163
257049950,4cyclictest30053-21diskstats23:50:133
257039951,2cyclictest0-21swapper/220:35:132
257039950,5cyclictest21445-21diskmemload22:38:552
257039950,5cyclictest0-21swapper/223:43:542
257039950,5cyclictest0-21swapper/223:37:042
257039950,5cyclictest0-21swapper/223:30:132
257039950,5cyclictest0-21swapper/223:23:222
257039950,5cyclictest0-21swapper/222:30:112
257039950,5cyclictest0-21swapper/200:17:292
257039950,5cyclictest0-21swapper/200:02:572
257039950,5cyclictest0-21swapper/200:02:572
257039950,0cyclictest0-21swapper/223:00:412
256969951,2cyclictest0-21swapper/120:50:111
256969950,5cyclictest0-21swapper/121:59:251
256969950,5cyclictest0-21swapper/121:38:001
256909950,5cyclictest0-21swapper/023:30:120
256909950,5cyclictest0-21swapper/022:40:250
256909950,5cyclictest0-21swapper/020:20:000
256909950,5cyclictest0-21swapper/019:50:120
256909950,0cyclictest0-21swapper/023:41:070
1394250,0sleep10-21swapper/123:04:511
9276240,0sleep00-21swapper/023:24:260
28188240,0sleep00-21swapper/022:45:300
257049944,0cyclictest40-21ksoftirqd/320:15:013
257049944,0cyclictest0-21swapper/322:36:573
257049944,0cyclictest0-21swapper/322:10:013
257049944,0cyclictest0-21swapper/321:56:383
257049944,0cyclictest0-21swapper/320:40:493
257049944,0cyclictest0-21swapper/300:15:273
257049942,2cyclictest17423-21ssh00:00:133
257049942,2cyclictest17423-21ssh00:00:123
257049942,2cyclictest0-21swapper/322:06:513
257049942,1cyclictest22495-21ssh23:30:193
257049942,1cyclictest20141-21if_eth021:05:173
257049941,2cyclictest0-21swapper/319:25:113
257049940,4cyclictest32457-21ssh21:15:033
257049940,4cyclictest24753-21ssh22:28:553
257049940,4cyclictest12115-21ssh21:50:573
257049940,4cyclictest0-21swapper/323:43:253
257049940,4cyclictest0-21swapper/323:25:123
257049940,4cyclictest0-21swapper/323:20:123
257049940,4cyclictest0-21swapper/323:18:043
257049940,4cyclictest0-21swapper/323:05:133
257049940,4cyclictest0-21swapper/323:02:263
257049940,4cyclictest0-21swapper/322:55:113
257049940,4cyclictest0-21swapper/322:50:123
257049940,4cyclictest0-21swapper/322:45:113
257049940,4cyclictest0-21swapper/321:45:123
257049940,4cyclictest0-21swapper/321:40:123
257049940,4cyclictest0-21swapper/321:24:403
257049940,4cyclictest0-21swapper/321:10:103
257049940,4cyclictest0-21swapper/320:30:123
257049940,4cyclictest0-21swapper/320:15:113
257049940,4cyclictest0-21swapper/319:19:203
257049940,4cyclictest0-21swapper/319:10:173
257049940,4cyclictest0-21swapper/300:20:073
257049940,3cyclictest7540-21uname22:20:163
257049940,3cyclictest5320-21cat00:25:213
257049940,3cyclictest5219-21ssh00:10:083
257049940,3cyclictest31926-21ssh22:00:223
257049940,3cyclictest21433-21ssh23:45:233
257049940,3cyclictest21232-21ssh21:25:023
257049940,3cyclictest20042-21ssh00:33:073
257049940,3cyclictest18752-21ssh21:39:123
257049940,3cyclictest16770-21/usr/sbin/munin19:55:193
257049940,3cyclictest15315-21ssh22:40:103
257049940,0cyclictest0-21swapper/320:03:173
257049940,0cyclictest0-21swapper/319:43:303
257039944,0cyclictest0-21swapper/222:40:192
257039944,0cyclictest0-21swapper/221:56:562
257039944,0cyclictest0-21swapper/200:34:232
257039944,0cyclictest0-21swapper/200:06:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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