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2026-02-27 - 17:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot2.osadl.org (updated Fri Feb 27, 2026 12:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
70802201185,11sleep10-21swapper/107:09:441
48792188172,11sleep00-21swapper/007:05:070
68422185168,12sleep30-21swapper/307:06:423
48762174154,15sleep20-21swapper/207:05:042
76972470,0sleep30-21swapper/311:02:103
257382430,0sleep10-21swapper/111:10:371
53692420,0sleep10-21swapper/109:41:521
79602110,0sleep00-21swapper/012:37:500
270052110,1sleep30-21swapper/309:20:373
133262110,0sleep30-21swapper/309:45:283
133262110,0sleep30-21swapper/309:45:273
72669992,3cyclictest27693-21munin-run12:00:010
30819290,0sleep10-21swapper/112:33:111
1137290,0sleep30-21swapper/310:11:093
72669982,3cyclictest23646-21munin-run12:30:010
72769971,1cyclictest40-21ksoftirqd/307:12:303
72769966,0cyclictest40-21ksoftirqd/311:35:013
72769966,0cyclictest40-21ksoftirqd/308:35:163
72769965,0cyclictest40-21ksoftirqd/311:20:173
72769965,0cyclictest40-21ksoftirqd/310:15:133
72769964,2cyclictest40-21ksoftirqd/309:35:213
72769964,0cyclictest40-21ksoftirqd/310:40:193
72769964,0cyclictest40-21ksoftirqd/308:05:173
72769960,1cyclictest81rcu_preempt07:40:123
72769960,1cyclictest40-21ksoftirqd/312:10:113
72709960,1cyclictest18773-21df10:20:122
72669961,5cyclictest0-21swapper/009:30:110
72669960,3cyclictest12903-21awk07:20:010
72769955,0cyclictest40-21ksoftirqd/312:35:123
72769955,0cyclictest40-21ksoftirqd/310:50:003
72769955,0cyclictest40-21ksoftirqd/309:50:113
72769955,0cyclictest40-21ksoftirqd/307:25:013
72769955,0cyclictest0-21swapper/311:40:023
72769955,0cyclictest0-21swapper/310:28:113
72769954,1cyclictest40-21ksoftirqd/308:25:173
72769954,0cyclictest40-21ksoftirqd/311:35:013
72769954,0cyclictest40-21ksoftirqd/311:25:013
72769953,1cyclictest40-21ksoftirqd/311:55:143
72769953,0cyclictest40-21ksoftirqd/311:15:133
72769953,0cyclictest40-21ksoftirqd/310:50:123
72769953,0cyclictest40-21ksoftirqd/310:05:203
72769953,0cyclictest40-21ksoftirqd/309:15:143
72769953,0cyclictest40-21ksoftirqd/308:10:193
72769952,3cyclictest40-21ksoftirqd/312:25:173
72769952,1cyclictest40-21ksoftirqd/310:40:013
72769951,3cyclictest40-21ksoftirqd/312:20:123
72769951,3cyclictest40-21ksoftirqd/309:40:023
72769951,1cyclictest40-21ksoftirqd/310:20:123
72769951,1cyclictest40-21ksoftirqd/309:30:143
72769951,0cyclictest81rcu_preempt11:05:173
72769950,5cyclictest0-21swapper/309:59:303
72769950,4cyclictest6197-21ssh10:30:103
72769950,4cyclictest0-21swapper/311:50:113
72769950,1cyclictest8843-21tune2fs08:15:143
72769950,1cyclictest40-21ksoftirqd/312:05:153
72769950,0cyclictest81rcu_preempt09:05:163
72709951,3cyclictest814-21snmpd11:38:402
72709950,5cyclictest0-21swapper/212:08:282
72709950,5cyclictest0-21swapper/210:56:172
72709950,4cyclictest0-21swapper/212:00:112
72709950,4cyclictest0-21swapper/210:50:112
72679951,2cyclictest0-21swapper/109:15:101
72679951,2cyclictest0-21swapper/107:25:111
72669954,0cyclictest3-21ksoftirqd/011:10:000
72669952,1cyclictest814-21snmpd09:16:220
72669951,3cyclictest18292-21wget08:35:110
72669950,5cyclictest0-21swapper/012:07:570
72669950,5cyclictest0-21swapper/011:11:120
72669950,5cyclictest0-21swapper/008:50:110
72669950,4cyclictest31042-21hddtemp_smartct10:10:130
72669950,3cyclictest0-21swapper/012:13:570
72669950,0cyclictest9581-21ssh11:35:040
14232250,4sleep214662-21df09:15:122
72769944,0cyclictest40-21ksoftirqd/312:30:143
72769944,0cyclictest40-21ksoftirqd/309:25:193
72769944,0cyclictest40-21ksoftirqd/309:00:003
72769944,0cyclictest40-21ksoftirqd/308:50:143
72769944,0cyclictest40-21ksoftirqd/308:00:113
72769944,0cyclictest40-21ksoftirqd/307:45:153
72769944,0cyclictest40-21ksoftirqd/307:40:003
72769944,0cyclictest40-21ksoftirqd/307:25:123
72769944,0cyclictest381rcuc/309:10:193
72769943,0cyclictest40-21ksoftirqd/311:45:003
72769942,1cyclictest10520-21tune2fs07:15:013
72769942,0cyclictest40-21ksoftirqd/311:10:003
72769941,2cyclictest0-21swapper/308:45:113
72769941,0cyclictest81rcu_preempt08:20:193
72769941,0cyclictest81rcu_preempt07:55:123
72769940,4cyclictest0-21swapper/312:15:103
72769940,4cyclictest0-21swapper/309:00:153
72769940,4cyclictest0-21swapper/307:50:113
72769940,3cyclictest0-21swapper/312:00:103
72769940,1cyclictest40-21ksoftirqd/310:55:143
72769940,0cyclictest81rcu_preempt10:00:133
72769940,0cyclictest81rcu_preempt08:40:113
72769940,0cyclictest81rcu_preempt07:30:103
72709944,0cyclictest0-21swapper/211:45:192
72709944,0cyclictest0-21swapper/209:51:242
72709942,1cyclictest814-21snmpd10:32:032
72709941,2cyclictest0-21swapper/208:55:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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