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2026-05-21 - 08:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot2.osadl.org (updated Thu May 21, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22832202170,12sleep00-21swapper/019:05:500
24812200184,11sleep10-21swapper/119:08:241
25752189172,12sleep30-21swapper/319:09:373
2429210487,12sleep20-21swapper/219:07:452
92012460,0sleep1278299cyclictest23:21:051
324832450,0sleep10-21swapper/121:25:471
250232450,0sleep00-21swapper/022:41:080
81112430,0sleep10-21swapper/121:45:251
325672420,0sleep30-21swapper/323:00:373
61802100,0sleep30-21swapper/300:23:563
114552100,0sleep10-21swapper/122:03:261
6023290,0sleep10-21swapper/120:20:121
27899991,7cyclictest0-21swapper/323:10:113
27899970,1cyclictest24101-21hddtemp_smartct22:25:163
27849970,6cyclictest0-21swapper/221:45:122
27779972,5cyclictest17160-21kworker/0:123:39:120
27779972,5cyclictest17160-21kworker/0:123:03:370
27779972,5cyclictest17160-21kworker/0:122:18:370
27779972,5cyclictest17160-21kworker/0:100:36:050
27779972,5cyclictest17160-21kworker/0:100:18:090
27779972,5cyclictest17160-21kworker/0:100:10:570
27779972,5cyclictest17160-21kworker/0:100:06:560
27779971,6cyclictest17160-21kworker/0:123:31:290
27779971,6cyclictest17160-21kworker/0:121:32:100
27779971,3cyclictest712-21perf20:10:000
27779970,4cyclictest24121-21munin-run23:44:590
27899964,1cyclictest40-21ksoftirqd/300:25:113
27899964,0cyclictest40-21ksoftirqd/323:45:113
27899964,0cyclictest40-21ksoftirqd/300:00:003
27779962,4cyclictest17160-21kworker/0:123:50:330
27779962,4cyclictest17160-21kworker/0:123:46:410
27779962,4cyclictest17160-21kworker/0:123:22:370
27779962,4cyclictest17160-21kworker/0:122:50:130
27779962,4cyclictest17160-21kworker/0:122:34:260
27779962,4cyclictest17160-21kworker/0:122:13:170
27779962,4cyclictest17160-21kworker/0:121:23:090
27779962,4cyclictest17160-21kworker/0:119:40:170
27779961,5cyclictest17160-21kworker/0:123:58:170
27779961,5cyclictest17160-21kworker/0:123:25:130
27779961,5cyclictest17160-21kworker/0:123:15:050
27779961,5cyclictest17160-21kworker/0:122:59:290
27779961,5cyclictest17160-21kworker/0:122:35:460
27779961,5cyclictest17160-21kworker/0:122:29:460
27779961,5cyclictest17160-21kworker/0:122:02:100
27779961,5cyclictest17160-21kworker/0:121:59:100
27779961,5cyclictest17160-21kworker/0:121:48:250
27779961,5cyclictest17160-21kworker/0:121:13:580
27779961,5cyclictest17160-21kworker/0:120:10:170
27779961,5cyclictest17160-21kworker/0:100:22:290
13901260,2sleep313900-21cut23:39:593
27899955,0cyclictest40-21ksoftirqd/323:05:113
27899955,0cyclictest40-21ksoftirqd/322:40:013
27899955,0cyclictest40-21ksoftirqd/321:00:113
27899955,0cyclictest40-21ksoftirqd/320:50:083
27899955,0cyclictest40-21ksoftirqd/319:25:113
27899955,0cyclictest40-21ksoftirqd/300:30:103
27899955,0cyclictest31868-21ssh00:35:543
27899955,0cyclictest0-21swapper/321:43:303
27899953,1cyclictest40-21ksoftirqd/319:50:093
27899953,0cyclictest40-21ksoftirqd/321:10:143
27899952,1cyclictest40-21ksoftirqd/322:20:133
27899950,5cyclictest0-21swapper/323:30:123
27899950,5cyclictest0-21swapper/323:27:343
27899950,5cyclictest0-21swapper/321:28:483
27899950,5cyclictest0-21swapper/321:18:203
27899950,0cyclictest81rcu_preempt22:55:013
27899950,0cyclictest19367-21ssh23:42:043
27899950,0cyclictest0-21swapper/323:20:113
27849955,0cyclictest31-21ksoftirqd/223:20:002
27849955,0cyclictest0-21swapper/200:13:152
27849953,2cyclictest31-21ksoftirqd/222:00:132
27849952,3cyclictest5332-21kworker/2:223:41:052
27849951,3cyclictest799-21runrttasks22:05:112
27849950,5cyclictest0-21swapper/223:57:512
27849950,1cyclictest31836-21/usr/sbin/munin22:45:142
27829952,2cyclictest0-21swapper/122:30:101
27829951,2cyclictest0-21swapper/100:20:101
27829951,2cyclictest0-21swapper/100:15:101
27829950,5cyclictest0-21swapper/121:40:581
27779952,3cyclictest17160-21kworker/0:123:10:560
27779952,3cyclictest17160-21kworker/0:123:05:480
27779952,3cyclictest17160-21kworker/0:121:40:380
27779952,3cyclictest17160-21kworker/0:120:54:520
27779952,3cyclictest17160-21kworker/0:120:20:200
27779952,3cyclictest17160-21kworker/0:100:25:280
27779951,4cyclictest17160-21kworker/0:122:47:130
27779951,4cyclictest17160-21kworker/0:122:22:380
27779951,4cyclictest17160-21kworker/0:122:05:220
27779951,4cyclictest17160-21kworker/0:121:51:570
27779951,4cyclictest17160-21kworker/0:121:25:130
27779951,4cyclictest17160-21kworker/0:121:17:010
27779951,4cyclictest17160-21kworker/0:120:45:130
27779951,4cyclictest17160-21kworker/0:120:00:160
27779951,4cyclictest17160-21kworker/0:119:55:080
27779951,4cyclictest17160-21kworker/0:119:35:160
27779951,4cyclictest17160-21kworker/0:119:20:010
27779951,4cyclictest17160-21kworker/0:100:30:040
27779951,4cyclictest17160-21kworker/0:100:00:000
27779950,5cyclictest17160-21kworker/0:121:35:260
27779950,5cyclictest17160-21kworker/0:121:05:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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