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2026-02-19 - 08:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot2.osadl.org (updated Thu Feb 19, 2026 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
272382196179,12sleep30-21swapper/319:08:503
271382184165,14sleep00-21swapper/019:07:290
273122182167,10sleep10-21swapper/119:09:441
270682178160,13sleep20-21swapper/219:06:362
44222440,0sleep00-21swapper/022:03:000
15162440,0sleep01519-21latency23:20:160
311682430,0sleep10-21swapper/123:19:211
13062420,0sleep10-21swapper/122:17:071
272122400,0sleep00-21swapper/023:16:540
232972360,0sleep00-21swapper/022:59:500
62202150,0sleep00-21swapper/023:54:550
14090290,0sleep20-21swapper/222:07:402
275209971,3cyclictest30604-21munin-run20:20:000
275379960,5cyclictest0-21swapper/323:35:113
275379952,3cyclictest814-21snmpd23:01:553
275379951,4cyclictest30063-21kworker/3:023:32:533
275379951,4cyclictest30063-21kworker/3:023:26:213
275379950,5cyclictest13854-21ssh23:58:123
275379950,5cyclictest0-21swapper/321:29:133
275379950,4cyclictest30840-21apt-get20:20:113
275379950,4cyclictest0-21swapper/321:55:113
275379950,0cyclictest0-21swapper/322:43:073
275379950,0cyclictest0-21swapper/300:22:113
275309955,0cyclictest0-21swapper/221:26:132
275309950,5cyclictest0-21swapper/223:55:232
275309950,5cyclictest0-21swapper/223:50:362
275309950,5cyclictest0-21swapper/223:39:572
275309950,5cyclictest0-21swapper/223:17:572
275309950,5cyclictest0-21swapper/222:50:192
275309950,5cyclictest0-21swapper/222:48:082
275309950,5cyclictest0-21swapper/222:22:492
275309950,5cyclictest0-21swapper/222:03:362
275309950,5cyclictest0-21swapper/200:27:222
275309950,5cyclictest0-21swapper/200:21:322
275309950,5cyclictest0-21swapper/200:10:402
275309950,5cyclictest0-21swapper/200:06:482
275309950,1cyclictest0-21swapper/223:45:372
275309950,1cyclictest0-21swapper/223:40:092
275309950,1cyclictest0-21swapper/200:19:082
275309950,1cyclictest0-21swapper/200:00:032
275249952,1cyclictest0-21swapper/100:20:121
275249951,2cyclictest0-21swapper/122:00:121
275249951,1cyclictest0-21swapper/123:55:121
275249950,5cyclictest0-21swapper/123:09:011
275249950,5cyclictest0-21swapper/122:33:131
275249950,5cyclictest0-21swapper/100:28:541
275249950,5cyclictest0-21swapper/100:03:081
275209951,4cyclictest20860-21munin-run21:05:000
275209951,3cyclictest814-21snmpd00:12:490
275209950,5cyclictest0-21swapper/020:10:210
275209950,0cyclictest0-21swapper/021:41:180
275379944,0cyclictest0-21swapper/320:50:123
275379944,0cyclictest0-21swapper/319:55:213
275379942,2cyclictest30063-21kworker/3:022:45:253
275379941,3cyclictest30063-21kworker/3:023:45:213
275379941,3cyclictest30063-21kworker/3:023:20:403
275379941,3cyclictest30063-21kworker/3:020:10:153
275379941,3cyclictest30063-21kworker/3:000:39:043
275379940,4cyclictest8989-21cat20:40:133
275379940,4cyclictest3912-21ssh21:31:053
275379940,4cyclictest14417-21df_inode22:55:133
275379940,4cyclictest0-21swapper/323:50:103
275379940,4cyclictest0-21swapper/323:40:123
275379940,4cyclictest0-21swapper/323:15:113
275379940,4cyclictest0-21swapper/323:10:113
275379940,4cyclictest0-21swapper/322:50:393
275379940,4cyclictest0-21swapper/322:25:113
275379940,4cyclictest0-21swapper/322:20:483
275379940,4cyclictest0-21swapper/321:45:433
275379940,4cyclictest0-21swapper/321:40:463
275379940,4cyclictest0-21swapper/321:35:103
275379940,4cyclictest0-21swapper/321:20:113
275379940,4cyclictest0-21swapper/321:15:123
275379940,4cyclictest0-21swapper/320:05:113
275379940,4cyclictest0-21swapper/319:45:123
275379940,4cyclictest0-21swapper/319:45:113
275379940,4cyclictest0-21swapper/300:10:123
275379940,4cyclictest0-21swapper/300:05:093
275379940,3cyclictest9965-21ssh22:37:063
275379940,3cyclictest9417-21/usr/sbin/munin22:05:163
275379940,3cyclictest5891-21ssh22:03:543
275379940,3cyclictest3570-21/usr/sbin/munin00:25:133
275379940,3cyclictest3293-21ssh23:05:163
275379940,3cyclictest29537-21ssh22:30:323
275379940,3cyclictest28846-21ssh21:12:073
275379940,3cyclictest284402sleep322:15:013
275379940,3cyclictest20975-21basename20:00:113
275379940,3cyclictest18525-21grep21:00:003
275379940,3cyclictest1771-21hddtemp_smartct19:20:143
275379940,3cyclictest17036-21ssh00:00:013
275379940,3cyclictest15308-21ssh00:15:053
275379940,3cyclictest15127-21ssh21:52:223
275379940,3cyclictest13589-21ssh00:30:073
275379940,3cyclictest13476-21cat19:45:013
275379940,3cyclictest0-21swapper/322:10:123
275379940,3cyclictest0-21swapper/319:35:123
275309944,0cyclictest0-21swapper/222:44:292
275309944,0cyclictest0-21swapper/222:11:012
275309944,0cyclictest0-21swapper/220:30:022
275309943,1cyclictest14011-21tr00:30:102
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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