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2026-03-09 - 07:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot2.osadl.org (updated Mon Mar 09, 2026 00:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
126312202185,12sleep10-21swapper/119:08:201
124542191174,12sleep00-21swapper/019:06:020
125612189172,12sleep30-21swapper/319:07:253
124882171152,14sleep20-21swapper/219:06:282
254582460,0sleep10-21swapper/122:52:231
93782440,0sleep10-21swapper/121:56:501
62852440,0sleep00-21swapper/022:10:580
45032430,0sleep00-21swapper/000:01:310
291312140,0sleep20-21swapper/221:35:122
129619993,3cyclictest7385-21ssh21:25:010
129619982,3cyclictest5889-21munin-run00:35:000
129719960,5cyclictest0-21swapper/320:25:123
129619962,4cyclictest1128-21munin-run20:55:000
10772260,1sleep011012-21cat21:10:220
6969250,0sleep26998-21sh23:30:432
129719955,0cyclictest15506-21kworker/3:023:25:073
129719955,0cyclictest15506-21kworker/3:022:40:203
129719955,0cyclictest0-21swapper/322:08:123
129719955,0cyclictest0-21swapper/322:02:573
129719950,5cyclictest0-21swapper/323:15:343
129719950,5cyclictest0-21swapper/321:40:123
129719950,5cyclictest0-21swapper/321:14:483
129719950,4cyclictest29366-21df_inode20:45:133
129719950,4cyclictest2522-21ssh23:45:113
129719950,4cyclictest1285-21perl00:00:153
129719950,0cyclictest0-21swapper/300:08:323
129679955,0cyclictest0-21swapper/220:25:222
129679950,5cyclictest0-21swapper/222:57:002
129679950,5cyclictest0-21swapper/221:31:002
129679950,5cyclictest0-21swapper/200:35:212
129679950,0cyclictest0-21swapper/223:11:152
129629955,0cyclictest0-21swapper/123:15:111
129629951,2cyclictest0-21swapper/123:45:111
129629950,5cyclictest0-21swapper/121:48:371
129629950,5cyclictest0-21swapper/121:33:391
129629950,5cyclictest0-21swapper/100:29:251
129619952,3cyclictest814-21snmpd21:09:050
129619950,5cyclictest0-21swapper/023:44:390
129619950,5cyclictest0-21swapper/023:14:060
129619950,5cyclictest0-21swapper/019:58:150
129619950,0cyclictest0-21swapper/022:48:560
129619950,0cyclictest0-21swapper/021:40:240
129619950,0cyclictest0-21swapper/000:39:390
17911240,0sleep30-21swapper/322:16:513
129719944,0cyclictest0-21swapper/300:16:143
129719942,1cyclictest2392-21ssh23:13:023
129719942,1cyclictest23376-21ssh23:55:133
129719942,1cyclictest10981-21sh23:00:533
129719942,1cyclictest10220-21ssh21:25:303
129719942,1cyclictest0-21swapper/323:40:103
129719941,3cyclictest814-21snmpd20:59:583
129719941,3cyclictest814-21snmpd20:33:003
129719941,3cyclictest814-21snmpd20:21:193
129719941,3cyclictest814-21snmpd20:19:493
129719941,3cyclictest814-21snmpd20:08:213
129719941,3cyclictest814-21snmpd19:42:243
129719941,2cyclictest0-21swapper/319:50:123
129719941,2cyclictest0-21swapper/319:10:113
129719941,1cyclictest0-21swapper/323:05:133
129719940,4cyclictest8554-21diskmemload22:13:143
129719940,4cyclictest0-21swapper/323:30:123
129719940,4cyclictest0-21swapper/323:23:473
129719940,4cyclictest0-21swapper/322:35:123
129719940,4cyclictest0-21swapper/322:25:423
129719940,4cyclictest0-21swapper/321:55:123
129719940,4cyclictest0-21swapper/321:45:083
129719940,4cyclictest0-21swapper/321:35:113
129719940,4cyclictest0-21swapper/321:16:203
129719940,4cyclictest0-21swapper/320:50:123
129719940,4cyclictest0-21swapper/320:40:123
129719940,4cyclictest0-21swapper/319:32:133
129719940,4cyclictest0-21swapper/319:20:103
129719940,4cyclictest0-21swapper/319:15:123
129719940,4cyclictest0-21swapper/300:30:113
129719940,4cyclictest0-21swapper/300:25:183
129719940,4cyclictest0-21swapper/300:20:103
129719940,4cyclictest0-21swapper/300:10:493
129719940,3cyclictest9898-21ssh22:45:133
129719940,3cyclictest4382-21df19:55:133
129719940,3cyclictest26388-21apt19:35:123
129719940,3cyclictest23422-21sh22:20:033
129719940,3cyclictest20848-21perl22:50:133
129719940,3cyclictest18289-21/usr/sbin/munin21:30:103
129719940,3cyclictest12838-21memory22:30:153
129719940,3cyclictest0-21swapper/323:50:133
129719940,1cyclictest7345-21irqstats20:00:153
129679944,0cyclictest0-21swapper/223:28:342
129679944,0cyclictest0-21swapper/222:24:242
129679944,0cyclictest0-21swapper/222:15:582
129679944,0cyclictest0-21swapper/221:00:172
129679944,0cyclictest0-21swapper/220:45:002
129679944,0cyclictest0-21swapper/200:20:392
129679943,1cyclictest9024-21/usr/sbin/munin20:05:142
129679940,4cyclictest18654-21ssh00:25:112
129679940,4cyclictest10303-21memory21:10:172
129679940,4cyclictest0-21swapper/223:35:102
129679940,4cyclictest0-21swapper/222:52:172
129679940,4cyclictest0-21swapper/222:45:122
129679940,4cyclictest0-21swapper/222:31:382
129679940,4cyclictest0-21swapper/222:11:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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