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2026-02-20 - 06:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot2.osadl.org (updated Fri Feb 20, 2026 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
91752196180,11sleep10-21swapper/119:09:281
91752196180,11sleep10-21swapper/119:09:281
90112194177,12sleep30-21swapper/319:07:223
90112194177,12sleep30-21swapper/319:07:213
89932187170,12sleep00-21swapper/019:07:070
89932187170,12sleep00-21swapper/019:07:070
89092178162,11sleep20-21swapper/219:06:042
89092178162,11sleep20-21swapper/219:06:042
70242440,0sleep10-21swapper/122:45:091
270512440,0sleep10-21swapper/123:42:151
37192390,0sleep33718-21ssh21:40:143
254222130,0sleep20-21swapper/223:57:212
186092100,0sleep00-21swapper/000:10:120
23079290,0sleep10-21swapper/122:36:341
93909971,3cyclictest9348-21munin-run23:50:010
93909970,3cyclictest19913-21perf20:35:010
94039960,5cyclictest30647-21apt-get22:25:023
94039960,5cyclictest0-21swapper/322:30:123
93999965,1cyclictest0-21swapper/200:09:292
93909960,3cyclictest20163-21perf19:30:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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