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2025-06-28 - 23:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot2.osadl.org (updated Sat Jun 28, 2025 12:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165012196182,10sleep10-21swapper/107:06:271
167142192174,13sleep30-21swapper/307:09:153
167032191174,12sleep20-21swapper/207:09:052
167062186172,10sleep00-21swapper/007:09:070
78532500,0sleep30-21swapper/312:21:293
108952460,0sleep10-21swapper/112:23:261
316372450,0sleep20-21swapper/209:50:382
297172450,0sleep10-21swapper/109:18:061
254282450,0sleep10-21swapper/111:09:041
150612450,0sleep00-21swapper/011:35:490
56032440,0sleep10-21swapper/109:21:521
205392430,0sleep00-21swapper/009:13:410
166032420,0sleep10-21swapper/109:27:281
215992390,0sleep20-21swapper/208:20:232
169349980,4cyclictest25014-21perf08:30:000
169349980,4cyclictest20755-21munin-run09:30:020
169479960,5cyclictest0-21swapper/311:15:173
169409964,2cyclictest0-21swapper/211:51:282
169479955,0cyclictest0-21swapper/311:11:313
169479954,1cyclictest16470-21kworker/3:112:38:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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