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2025-10-06 - 13:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot2.osadl.org (updated Mon Oct 06, 2025 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
195012203182,17sleep30-21swapper/319:05:043
216272200183,12sleep10-21swapper/119:08:441
214162179162,12sleep00-21swapper/019:06:020
21458210891,12sleep20-21swapper/219:06:322
189072490,0sleep10-21swapper/100:25:381
98162470,0sleep10-21swapper/100:05:171
307802460,0sleep00-21swapper/000:31:530
264232430,0sleep30-21swapper/300:13:443
8283280,0sleep10-21swapper/121:21:471
219199982,3cyclictest32472-21perf19:30:010
219199981,3cyclictest3105-21idleruntime-cro20:45:000
219199971,3cyclictest22518-21munin-run20:15:000
18364270,0sleep30-21swapper/321:26:493
219199960,3cyclictest21031-21basename23:55:000
17623260,0sleep317625-21ntp_kernel_pll_21:10:203
219269955,0cyclictest0-21swapper/322:55:223
219269955,0cyclictest0-21swapper/321:37:143
219269954,1cyclictest0-21swapper/323:51:053
219269953,1cyclictest8048-21uname00:20:203
219269951,2cyclictest0-21swapper/320:35:083
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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