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2026-02-11 - 06:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot2.osadl.org (updated Wed Feb 11, 2026 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
105762197180,12sleep30-21swapper/319:09:093
104662185169,11sleep00-21swapper/019:07:420
104632172153,14sleep20-21swapper/219:07:412
103902159143,11sleep10-21swapper/119:06:431
210702510,0sleep00-21swapper/021:16:130
217112500,0sleep00-21swapper/023:38:560
287682440,0sleep20-21swapper/222:23:002
176822430,0sleep30-21swapper/322:33:313
168582430,0sleep10-21swapper/122:49:021
21473280,0sleep021477-21uniq22:35:150
108159982,3cyclictest11655-21munin-run23:50:010
108159971,3cyclictest6489-21awk20:05:000
108159970,3cyclictest26344-21sendmail-msp19:40:000
108299960,6cyclictest0-21swapper/300:20:123
108249962,3cyclictest0-21swapper/219:15:122
108249960,1cyclictest0-21swapper/223:19:372
108199963,2cyclictest0-21swapper/121:55:131
108299955,0cyclictest25382-21kworker/3:023:15:213
108299955,0cyclictest0-21swapper/323:39:413
108299950,5cyclictest0-21swapper/323:30:113
108299950,5cyclictest0-21swapper/323:30:103
108299950,5cyclictest0-21swapper/323:14:313
108299950,5cyclictest0-21swapper/322:42:223
108299950,5cyclictest0-21swapper/319:47:193
108299950,5cyclictest0-21swapper/300:28:523
108299950,4cyclictest0-21swapper/323:45:113
108299950,4cyclictest0-21swapper/322:05:123
108299950,4cyclictest0-21swapper/319:40:093
108249950,5cyclictest0-21swapper/223:34:022
108249950,5cyclictest0-21swapper/223:34:022
108249950,5cyclictest0-21swapper/222:01:122
108249950,5cyclictest0-21swapper/221:28:112
108249950,4cyclictest6443-21/usr/sbin/munin00:35:192
108199952,1cyclictest0-21swapper/121:40:111
108199951,2cyclictest0-21swapper/119:10:121
108199950,5cyclictest0-21swapper/121:45:131
108199950,5cyclictest0-21swapper/100:19:451
108199950,5cyclictest0-21swapper/100:09:261
108159951,4cyclictest21873-21basename23:55:000
108159951,2cyclictest0-21swapper/019:20:120
108159950,5cyclictest0-21swapper/023:08:300
108159950,5cyclictest0-21swapper/022:42:320
108159950,5cyclictest0-21swapper/022:10:580
27931240,0sleep00-21swapper/023:25:240
2295240,0sleep10-21swapper/100:32:471
21313240,0sleep1201rcuc/121:16:211
108299944,0cyclictest25382-21kworker/3:020:49:523
108299944,0cyclictest25382-21kworker/3:000:33:433
108299944,0cyclictest25382-21kworker/3:000:11:213
108299944,0cyclictest0-21swapper/323:26:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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