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2025-07-19 - 11:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot2.osadl.org (updated Sat Jul 19, 2025 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
130692201186,10sleep10-21swapper/119:10:001
108432185169,12sleep30-21swapper/319:05:083
128522184168,11sleep00-21swapper/019:07:100
108372175157,13sleep20-21swapper/219:05:032
121202490,1sleep012125-21latency_hist22:50:010
245842450,0sleep20-21swapper/222:06:152
86552430,0sleep30-21swapper/323:36:443
327192430,0sleep032718-21ntp_kernel_pll_19:45:170
267372420,0sleep10-21swapper/121:18:501
3432100,0sleep10-21swapper/100:21:411
132429993,3cyclictest15031-21munin-run22:35:010
132429992,3cyclictest1453-21awk20:55:000
132429981,6cyclictest0-21swapper/020:05:140
20915260,0sleep10-21swapper/100:15:251
132519960,5cyclictest0-21swapper/322:45:133
4203250,0sleep10-21swapper/122:12:391
31800250,0sleep331802-21unixbench_multi23:15:223
31800250,0sleep331802-21unixbench_multi23:15:223
132519950,5cyclictest0-21swapper/323:14:173
132519950,5cyclictest0-21swapper/322:42:423
132519950,5cyclictest0-21swapper/322:18:163
132519950,5cyclictest0-21swapper/300:33:003
132519950,0cyclictest0-21swapper/321:27:053
132469955,0cyclictest0-21swapper/222:20:032
132469950,5cyclictest0-21swapper/223:41:582
132469950,5cyclictest0-21swapper/222:53:482
132469950,5cyclictest0-21swapper/222:17:002
132469950,5cyclictest0-21swapper/222:11:372
132469950,5cyclictest0-21swapper/221:52:242
132469950,5cyclictest0-21swapper/200:07:142
132469950,4cyclictest12579-21hddtemp_smartct23:55:162
132469950,1cyclictest0-21swapper/223:20:232
132469950,0cyclictest0-21swapper/223:53:192
132469950,0cyclictest0-21swapper/200:17:112
132439955,0cyclictest0-21swapper/123:21:211
132439950,5cyclictest0-21swapper/122:22:081
132439950,5cyclictest0-21swapper/120:30:491
132429953,1cyclictest15540-21ntpq20:15:160
132429953,0cyclictest3-21ksoftirqd/022:10:010
132429952,1cyclictest5127-21sh22:30:010
132429950,5cyclictest0-21swapper/023:51:070
132429950,5cyclictest0-21swapper/023:45:110
132429950,5cyclictest0-21swapper/022:53:480
132429950,5cyclictest0-21swapper/022:20:460
132429950,5cyclictest0-21swapper/022:12:190
132429950,5cyclictest0-21swapper/021:43:130
132429950,5cyclictest0-21swapper/021:23:170
132429950,5cyclictest0-21swapper/000:19:290
132429950,0cyclictest0-21swapper/023:04:340
30289240,1sleep10-21swapper/121:20:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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