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2026-02-14 - 07:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot2.osadl.org (updated Sat Feb 14, 2026 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33142202185,12sleep10-21swapper/119:08:591
32912191175,11sleep30-21swapper/319:08:413
32832178161,12sleep00-21swapper/019:08:340
31662178160,13sleep20-21swapper/219:07:042
194652390,0sleep10-21swapper/121:19:501
305822160,0sleep20-21swapper/222:27:292
205012100,0sleep00-21swapper/000:13:250
35769992,7cyclictest18115-21kworker/3:000:21:263
35769982,6cyclictest18115-21kworker/3:022:24:153
35769982,6cyclictest18115-21kworker/3:021:41:433
35769972,5cyclictest18115-21kworker/3:023:53:303
35769972,5cyclictest18115-21kworker/3:023:48:033
35769972,5cyclictest18115-21kworker/3:023:39:143
35769972,5cyclictest18115-21kworker/3:022:43:113
35769972,5cyclictest18115-21kworker/3:022:30:323
35769972,5cyclictest18115-21kworker/3:022:28:313
35769972,5cyclictest18115-21kworker/3:022:17:313
35769972,5cyclictest18115-21kworker/3:022:06:273
35769972,5cyclictest18115-21kworker/3:022:02:353
35769972,5cyclictest18115-21kworker/3:021:30:033
35769972,5cyclictest18115-21kworker/3:000:07:383
35769972,5cyclictest18115-21kworker/3:000:03:063
35719971,5cyclictest0-21swapper/219:20:122
35769962,4cyclictest18115-21kworker/3:023:26:303
35769962,4cyclictest18115-21kworker/3:023:22:343
35769962,4cyclictest18115-21kworker/3:023:15:393
35769962,4cyclictest18115-21kworker/3:023:13:223
35769962,4cyclictest18115-21kworker/3:023:07:063
35769962,4cyclictest18115-21kworker/3:023:07:063
35769962,4cyclictest18115-21kworker/3:022:56:073
35769962,4cyclictest18115-21kworker/3:022:35:593
35769962,4cyclictest18115-21kworker/3:022:10:593
35769962,4cyclictest18115-21kworker/3:021:51:393
35769962,4cyclictest18115-21kworker/3:021:20:113
35769962,4cyclictest18115-21kworker/3:000:25:103
35769962,4cyclictest18115-21kworker/3:000:16:353
35769961,5cyclictest18115-21kworker/3:023:57:143
35769961,5cyclictest18115-21kworker/3:023:42:023
35769961,5cyclictest18115-21kworker/3:023:30:303
35769961,5cyclictest18115-21kworker/3:023:01:463
35769961,5cyclictest18115-21kworker/3:022:54:023
35769961,5cyclictest18115-21kworker/3:021:55:033
35769961,5cyclictest18115-21kworker/3:021:46:353
35769961,5cyclictest18115-21kworker/3:021:37:353
35769961,5cyclictest18115-21kworker/3:021:26:113
35769961,5cyclictest18115-21kworker/3:021:13:473
35769961,5cyclictest18115-21kworker/3:000:36:303
35769961,5cyclictest18115-21kworker/3:000:33:343
35769961,5cyclictest18115-21kworker/3:000:10:023
35769960,6cyclictest0-21swapper/321:18:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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