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2026-02-27 - 01:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot2.osadl.org (updated Thu Feb 26, 2026 12:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
256262200183,12sleep10-21swapper/107:07:201
254842189173,11sleep30-21swapper/307:05:283
255532186168,13sleep00-21swapper/007:06:220
254832184167,12sleep20-21swapper/207:05:282
247412420,0sleep30-21swapper/309:58:353
49522410,0sleep10-21swapper/108:35:141
2600399132,3cyclictest6216-21perf11:25:000
235662130,0sleep00-21swapper/009:25:500
2600399122,6cyclictest2468-21awk11:54:590
35812100,0sleep30-21swapper/309:48:113
272602100,0sleep30-21swapper/309:28:053
2601399101,8cyclictest0-21swapper/309:20:123
2600399103,3cyclictest26520-21perf11:35:000
141962100,0sleep00-21swapper/009:37:230
260089970,7cyclictest0-21swapper/212:26:022
260089962,4cyclictest0-21swapper/211:55:262
260089962,4cyclictest0-21swapper/211:06:312
260089960,6cyclictest0-21swapper/212:32:572
260089960,6cyclictest0-21swapper/211:15:152
260089960,0cyclictest0-21swapper/212:15:142
260049960,6cyclictest0-21swapper/112:14:421
260039960,6cyclictest0-21swapper/010:42:380
7441250,0sleep10-21swapper/109:50:131
260139955,0cyclictest3622-21ssh09:16:153
260139955,0cyclictest0-21swapper/311:41:543
260139952,3cyclictest8212-21kworker/3:009:35:113
260139950,5cyclictest15433-21ssh10:41:063
260139950,5cyclictest0-21swapper/312:32:583
260139950,5cyclictest0-21swapper/310:39:203
260139950,5cyclictest0-21swapper/309:40:423
260139950,4cyclictest28992-21hddtemp_smartct07:15:023
260139950,0cyclictest0-21swapper/309:31:503
260089952,3cyclictest0-21swapper/212:35:222
260089952,3cyclictest0-21swapper/212:00:142
260089952,3cyclictest0-21swapper/211:20:432
260089951,4cyclictest0-21swapper/212:20:422
260089950,5cyclictest5270-21ssh11:40:102
260089950,5cyclictest0-21swapper/212:10:142
260089950,5cyclictest0-21swapper/212:05:102
260089950,5cyclictest0-21swapper/211:50:342
260089950,5cyclictest0-21swapper/211:45:182
260089950,5cyclictest0-21swapper/211:35:302
260089950,5cyclictest0-21swapper/211:30:012
260089950,5cyclictest0-21swapper/211:25:352
260089950,5cyclictest0-21swapper/211:11:072
260089950,5cyclictest0-21swapper/210:56:422
260089950,5cyclictest0-21swapper/210:30:222
260089950,5cyclictest0-21swapper/210:20:112
260089950,5cyclictest0-21swapper/210:15:312
260089950,4cyclictest31619-21munin-run07:20:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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