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2026-07-06 - 23:37

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4s.osadl.org (updated Mon Jul 06, 2026 12:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
387970123520,4sleep3481ktimers/307:50:153
3836510997368,4cyclictest4047870-21kworker/u8:0+events_unbound11:00:261
3836510996459,4cyclictest4002574-21kworker/u8:2+events_unbound10:00:261
3836510996459,3cyclictest3897816-21kworker/u8:2+flush-8:008:20:251
3836506996353,8cyclictest2473324-21kworker/u8:0+flush-8:007:10:270
3836510996055,3cyclictest4047870-21kworker/u8:0+flush-8:011:10:231
3836510995953,4cyclictest2473324-21kworker/u8:0+flush-8:007:15:021
3836510995752,3cyclictest3878154-21kworker/u8:1+events_unbound09:10:251
3836510995751,4cyclictest4047870-21kworker/u8:0+flush-8:011:30:211
3836510995751,4cyclictest4047870-21kworker/u8:0+flush-8:011:30:201
3836510995551,3cyclictest3952957-21kworker/u8:3+events_unbound09:50:251
3836510995551,3cyclictest3897816-21kworker/u8:2+events_unbound08:45:221
3836510995550,3cyclictest3942787-21kworker/u8:0+events_unbound09:25:251
3836510995549,5cyclictest3942787-21kworker/u8:0+flush-8:010:25:261
3836510995549,4cyclictest3863426-21kworker/u8:2+flush-8:007:40:211
3836510995449,4cyclictest3897816-21kworker/u8:2+flush-8:008:35:201
3836510995448,4cyclictest4047870-21kworker/u8:0+events_unbound11:05:241
3836510995447,6cyclictest2473324-21kworker/u8:0+events_unbound07:10:211
3836510995348,4cyclictest3897816-21kworker/u8:2+events_unbound09:00:231
3836510995348,3cyclictest3942787-21kworker/u8:0+flush-8:009:15:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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