You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-15 - 23:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4s.osadl.org (updated Sun Feb 15, 2026 12:44:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34148212630,2chrt281rcuc/108:41:111
3319979995847,8cyclictest274-21systemd-journal09:20:011
3319975995137,11cyclictest3470753-21apt-get09:40:000
3319979995047,2cyclictest3346910-21kworker/u8:1+events_unbound07:45:011
3319979995046,3cyclictest3636407-21kworker/u8:2+flush-8:012:26:061
3319979994945,3cyclictest3505557-21kworker/u8:1+events_unbound11:06:031
3319979994945,3cyclictest3505557-21kworker/u8:1+events_unbound11:06:031
3319975994942,5cyclictest3325153-21kworker/u8:0+flush-8:008:11:180
3319981994738,7cyclictest3505963-21cp10:15:012
3319979994736,5cyclictest3431355-21kworker/u8:2+events_unbound09:06:041
34639982460,1sleep03464001-21cut09:31:130
34718322450,2sleep0201rcuc/009:41:080
3319979994538,5cyclictest3515902-21kworker/u8:2+events_unbound10:35:031
3319975994535,8cyclictest3530784-21latency_hist10:40:010
3319979994440,3cyclictest3431378-21kworker/u8:4+events_unbound09:11:031
3319979994438,5cyclictest3550766-21kworker/u8:2+flush-8:011:16:131
331997599440,42cyclictest3631245-21munin-run12:20:000
3319979994339,3cyclictest3505557-21kworker/u8:1+events_unbound10:41:051
3319979994337,4cyclictest3431378-21kworker/u8:4+flush-8:010:46:151
3319975994334,7cyclictest3337105-21/usr/sbin/munin07:26:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional