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2025-08-30 - 01:06

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4s.osadl.org (updated Fri Aug 29, 2025 12:44:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2530352996154,5cyclictest2530478-21kworker/u8:3+flush-8:007:15:461
2530349996157,3cyclictest2633103-21kworker/u8:2+flush-8:009:10:410
2530352995950,6cyclictest2561804-21kworker/u8:1+flush-8:008:00:271
2530349995952,5cyclictest2597063-21kworker/u8:3+events_unbound08:25:410
2530349995853,4cyclictest2551875-21kworker/u8:0+events_unbound07:55:440
2530352995749,5cyclictest2551875-21kworker/u8:0+flush-8:007:50:311
2530352995443,8cyclictest2820141-21ntpq11:55:341
2530349995449,3cyclictest2741665-21kworker/u8:0+events_unbound11:55:390
2530349995446,3cyclictest2692138-21kworker/u8:1+events_unbound10:25:280
2530352995346,5cyclictest2561804-21kworker/u8:1+events_unbound09:05:011
2530352995344,6cyclictest2666869-21latency_hist09:25:011
2530349995349,3cyclictest1133768-21kworker/u8:4+events_unbound07:35:460
2530349995342,3cyclictest2551875-21kworker/u8:0+events_unbound08:00:030
2530349995248,3cyclictest2736453-21kworker/u8:3+events_unbound11:35:270
2530349995242,3cyclictest1133768-21kworker/u8:4+events_unbound07:15:110
2530349995147,3cyclictest2741665-21kworker/u8:0+events_unbound12:10:300
2530349995146,4cyclictest2561804-21kworker/u8:1+events_unbound08:35:350
2530349995146,4cyclictest2561804-21kworker/u8:1+events_unbound08:35:350
2530349995141,3cyclictest2561804-21kworker/u8:1+events_unbound08:15:290
2530349995140,3cyclictest2561804-21kworker/u8:1+events_unbound09:01:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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