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2026-02-14 - 21:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4s.osadl.org (updated Sat Feb 14, 2026 12:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35678072820,3chrt451irq_work/308:56:133
37737492810,2chrt161rcu_preempt12:25:000
3457171996459,3cyclictest3462118-21kworker/u8:1+events_unbound07:15:031
36984492560,3sleep0201rcuc/011:06:210
3457171995650,4cyclictest3688882-21kworker/u8:2+events_unbound11:06:031
3457171995650,4cyclictest3462118-21kworker/u8:1+events_unbound08:06:061
3457171995045,3cyclictest3708386-21kworker/u8:1+events_unbound11:51:111
3457171994943,5cyclictest3728947-21kworker/u8:0+events_unbound12:10:011
3457171994841,6cyclictest3688882-21kworker/u8:2+events_unbound11:56:031
3457171994840,6cyclictest3609183-21kworker/u8:4+flush-8:009:46:051
3457171994540,3cyclictest3462118-21kworker/u8:1+flush-8:008:11:111
3457171994537,6cyclictest3553951-21latency_hist08:45:011
35760532440,1chrt3575256-21kthreadcore09:06:090
3457171994439,3cyclictest3629273-21kworker/u8:2+events_unbound10:06:191
3457171994438,4cyclictest3609183-21kworker/u8:4+flush-8:009:56:211
3457176994322,18cyclictest3709045-21cat11:20:012
3457171994339,3cyclictest3589074-21kworker/u8:1+events_unbound10:30:001
3457171994337,4cyclictest3694082-21kworker/u8:3+flush-8:011:36:111
3457171994337,4cyclictest3694082-21kworker/u8:3+flush-8:011:36:111
3457171994337,4cyclictest3629273-21kworker/u8:2+events_unbound10:01:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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