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2026-02-25 - 18:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4s.osadl.org (updated Wed Feb 25, 2026 12:44:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1781880996543,6cyclictest2016698-21latency_hist11:05:010
1781880996240,9cyclictest2021019-21ntpq11:06:080
1781880996240,8cyclictest1918014-21/usr/sbin/munin09:26:060
1781883995949,7cyclictest2021861-21latency_hist11:10:011
1781880995643,10cyclictest1972698-21diskstats10:20:570
1781886995348,3cyclictest1719494-21kworker/u8:3+events_unbound07:26:012
1781883995347,4cyclictest1986732-21kworker/u8:3+events_unbound10:55:581
1781883995345,6cyclictest1719494-21kworker/u8:3+flush-8:008:21:121
1781883995246,4cyclictest1976862-21kworker/u8:1+events_unbound10:31:131
1781883995244,6cyclictest2046834-21kworker/u8:0+flush-8:011:56:111
1781883995146,3cyclictest1818768-21kworker/u8:2+events_unbound08:11:061
1781883995145,5cyclictest2066651-21kworker/u8:2+flush-8:012:15:581
1781883995145,4cyclictest2046834-21kworker/u8:0+events_unbound12:26:131
1781883995145,4cyclictest1867989-21latency_hist08:35:011
1781883995142,6cyclictest2110865-21latency_hist12:40:011
1781883995037,10cyclictest274-21systemd-journal08:45:001
1781886994943,4cyclictest1803861-21kworker/u8:1+events_unbound07:30:372
1781883994943,4cyclictest1986732-21kworker/u8:3+flush-8:011:46:001
1781883994942,5cyclictest1863048-21kworker/u8:0+flush-8:009:11:031
1781883994942,5cyclictest1818768-21kworker/u8:2+events_unbound07:50:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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