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2026-02-24 - 18:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4s.osadl.org (updated Tue Feb 24, 2026 12:44:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
226955721790,2sleep3481ktimers/312:36:033
1941157997264,6cyclictest2222713-21kworker/u8:0+events_unbound12:01:141
1941153996655,8cyclictest2067807-21latency_hist09:15:010
1941157996352,8cyclictest2042995-21latency_hist08:50:001
1941157996352,8cyclictest2042995-21latency_hist08:50:001
1941157996153,6cyclictest1909101-21kworker/u8:3+events_unbound07:30:001
1941157996153,6cyclictest1909101-21kworker/u8:3+events_unbound07:30:001
1941157995949,7cyclictest2271926-21latency_hist12:40:001
1941153995849,6cyclictest2207322-21latency_hist11:35:000
20606332570,4chrt0-21swapper/109:06:031
1941157995648,6cyclictest2068054-21kworker/u8:0+flush-8:009:16:121
1941153995545,7cyclictest2127306-21latency_hist10:15:000
1941153995545,7cyclictest2127306-21latency_hist10:15:000
1941153995344,6cyclictest1983181-21latency_hist07:50:010
1941159995241,8cyclictest2242361-21cat12:10:012
1941157995246,4cyclictest1953383-21kworker/u8:2+events_unbound08:15:011
1941157995240,8cyclictest2147539-21latency_hist10:35:011
1941153995142,6cyclictest2077694-21latency_hist09:25:010
21267112500,3chrt0-21swapper/210:11:132
21267112500,3chrt0-21swapper/210:11:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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