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2026-03-05 - 02:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4s.osadl.org (updated Thu Mar 05, 2026 00:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184757421870,2sleep375-21kworker/3:1-events23:01:513
183871821820,2sleep3471rcuc/322:52:003
17737522580,6chrt0-21swapper/221:46:562
1612833995448,4cyclictest1754669-21kworker/u8:0+events_unbound22:46:461
1612832995147,3cyclictest1754669-21kworker/u8:0+events_unbound21:56:580
1612832995046,3cyclictest1649889-21kworker/u8:3+events_unbound20:36:450
1612832995044,5cyclictest1904008-21kworker/u8:0+events_unbound00:30:010
1612833994941,6cyclictest1665441-21kworker/u8:1+events_unbound20:01:551
1612832994945,3cyclictest1754669-21kworker/u8:0+events_unbound23:26:580
1612832994937,4cyclictest1639825-21cp19:35:010
1612833994843,4cyclictest1904515-21kworker/u8:4+flush-8:000:21:471
1612833994843,4cyclictest1904008-21kworker/u8:0+events_unbound00:16:591
1612832994843,3cyclictest1665441-21kworker/u8:1+events_unbound20:06:540
19053352470,1sleep11905338-21cut00:01:481
1612833994742,4cyclictest1762633-21kworker/u8:1+flush-8:022:51:571
1612833994741,5cyclictest1854082-21kworker/u8:2+flush-8:023:51:561
1612833994740,5cyclictest1794464-21latency_hist22:10:011
1612833994736,8cyclictest1658953-21ntpq19:51:551
1612832994743,3cyclictest1904008-21kworker/u8:0+events_unbound00:11:580
1612832994743,3cyclictest1754669-21kworker/u8:0+events_unbound21:46:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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