You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-21 - 20:14

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4s.osadl.org (updated Sun Jun 21, 2026 12:44:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2841762998678,6cyclictest2951787-21kworker/u8:2+flush-8:009:05:360
2841762997872,4cyclictest3087243-21kworker/u8:1+events_unbound11:55:370
2841762997665,8cyclictest2938299-21diskstats08:45:240
2841762997465,7cyclictest3092485-21kworker/u8:3+flush-8:011:25:360
2841764997367,4cyclictest2841637-21kworker/u8:0+flush-8:007:20:011
2841762997267,3cyclictest2841637-21kworker/u8:0+flush-8:007:50:350
2841764996557,6cyclictest2873721-21kworker/u8:1+flush-8:008:25:371
2841764996460,3cyclictest3016836-21kworker/u8:2+events_unbound10:40:381
2841764996458,4cyclictest3167017-21kworker/u8:0+events_unbound12:35:351
2841762996358,4cyclictest2841637-21kworker/u8:0+flush-8:007:55:370
2841762996157,3cyclictest2841637-21kworker/u8:0+flush-8:008:15:360
2841762996151,7cyclictest2907199-21ntpq08:10:320
2841762996054,4cyclictest3062026-21kworker/u8:3+flush-8:011:00:410
2841764995949,7cyclictest3126205-21ntpq11:50:321
2841762995954,4cyclictest3137016-21kworker/u8:3+flush-8:012:30:300
2841764995848,8cyclictest2947890-21/usr/sbin/munin08:55:321
2841762995853,3cyclictest2873721-21kworker/u8:1+flush-8:008:30:240
2841762995852,5cyclictest3016836-21kworker/u8:2+flush-8:011:05:410
2841764995753,3cyclictest3137016-21kworker/u8:3+flush-8:012:15:301
2841764995748,7cyclictest2893560-21/usr/sbin/munin08:00:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional