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2026-02-04 - 18:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4s.osadl.org (updated Wed Feb 04, 2026 12:44:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
412092923580,2sleep3481ktimers/312:09:563
396953221730,2sleep3471rcuc/309:34:573
388630021330,2chrt3886292-21munin-run08:10:012
388630021330,2chrt3886292-21munin-run08:10:012
3824995999081,6cyclictest2982860-21kworker/u8:4+flush-8:009:10:010
3824999997972,5cyclictest3841745-21kworker/u8:1+flush-8:008:25:001
3824999997871,6cyclictest4092878-21kworker/u8:2+events_unbound12:00:001
3824999997570,3cyclictest3941972-21kworker/u8:1+flush-8:009:50:011
3824999997367,4cyclictest3808825-21kworker/u8:0+events_unbound08:10:011
3824999997367,4cyclictest3808825-21kworker/u8:0+events_unbound08:10:011
3824999997366,4cyclictest4017218-21kworker/u8:0+events_unbound10:25:011
3824999997165,4cyclictest3907000-21kworker/u8:2+events_unbound08:50:011
3824999996956,9cyclictest4061623-21latency_hist11:05:011
3824999996660,4cyclictest3967045-21kworker/u8:2+events_unbound10:09:501
3824999996660,4cyclictest3967045-21kworker/u8:2+events_unbound10:09:501
3824999996660,4cyclictest2982860-21kworker/u8:4+flush-8:009:25:081
3824999996659,5cyclictest3829952-21kworker/u8:2+events_unbound07:24:521
3824999996659,4cyclictest3967045-21kworker/u8:2+flush-8:011:00:011
3824999996559,4cyclictest3986642-21kworker/u8:3+events_unbound09:54:511
3824999996559,4cyclictest2982860-21kworker/u8:4+events_unbound07:30:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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