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2026-02-09 - 10:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4s.osadl.org (updated Fri Feb 06, 2026 12:44:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3403381999571,20cyclictest3630209-21apt-get10:55:000
3403384998062,13cyclictest3555127-21latency_hist09:40:001
3403381997161,7cyclictest3731440-21apt-get12:40:000
3403381997145,17cyclictest3685514-21latency_hist11:50:010
3403381996961,5cyclictest2578980-21kworker/u8:1+flush-8:009:10:010
3403381996644,19cyclictest3589992-21ntpq10:14:580
3403381996530,26cyclictest3485577-21python308:30:050
3403381996438,23cyclictest3471335-21diskstats08:19:480
3403384996354,7cyclictest2577496-21kworker/u8:4+flush-8:008:49:511
3403381996349,9cyclictest3459986-21latency_hist08:05:010
3403381996257,4cyclictest2577496-21kworker/u8:4+events_unbound08:44:520
3403386996155,4cyclictest3510776-21kworker/u8:2+flush-8:009:35:052
3403384995951,6cyclictest3515310-21ntpq09:00:031
3403384995853,4cyclictest3379406-21kworker/u8:0+flush-8:008:14:511
3403384995849,6cyclictest3716339-21latency_hist12:25:011
3403386995753,3cyclictest2577496-21kworker/u8:4+events_unbound09:09:552
3403384995749,6cyclictest3414794-21ntpq07:20:011
3403381995748,6cyclictest3495033-21latency_hist08:40:010
3403384995448,4cyclictest2577496-21kworker/u8:4+flush-8:011:09:571
3403384995348,4cyclictest3651328-21kworker/u8:1+flush-8:012:34:511
3403384995348,4cyclictest2578980-21kworker/u8:1+flush-8:008:39:511
3403384995348,4cyclictest2578980-21kworker/u8:1+flush-8:008:34:511
340338199531,50cyclictest1-21systemd11:20:010
3403386995246,4cyclictest3510776-21kworker/u8:2+flush-8:009:24:552
3403386995246,4cyclictest3510776-21kworker/u8:2+flush-8:009:24:552
3403386995244,6cyclictest3711791-21cat12:20:012
3403386995146,4cyclictest2578980-21kworker/u8:1+events_unbound07:34:562
3403386995145,4cyclictest3510776-21kworker/u8:2+flush-8:009:30:082
3403384995146,4cyclictest2578980-21kworker/u8:1+flush-8:008:40:041
3403384995143,5cyclictest2577496-21kworker/u8:4+flush-8:010:35:011
3403386995045,3cyclictest2577496-21kworker/u8:4+flush-8:009:25:052
3403384994944,4cyclictest2578980-21kworker/u8:1+flush-8:010:05:051
3403384994943,5cyclictest3379406-21kworker/u8:0+flush-8:007:24:491
3403384994843,4cyclictest2577496-21kworker/u8:4+flush-8:011:15:011
3403384994842,4cyclictest2577496-21kworker/u8:4+flush-8:010:20:001
3403381994829,16cyclictest3510016-21latency_hist08:55:010
3403381994825,20cyclictest286-21systemd-journal12:24:140
3403381994823,22cyclictest3601434-21diskstats10:29:500
3403384994737,7cyclictest3695460-21latency_hist12:00:011
3403384994733,10cyclictest3464969-21latency_hist08:10:001
3403384994637,7cyclictest2578980-21kworker/u8:1+flush-8:010:34:581
36207772450,5sleep20-21swapper/210:45:052
3403384994540,4cyclictest3666488-21kworker/u8:2+events_unbound12:05:051
3403384994540,4cyclictest3379406-21kworker/u8:0+flush-8:008:19:491
3403381994537,5cyclictest3560151-21latency_hist09:45:000
36571092440,4sleep0201rcuc/011:24:520
3403386994441,2cyclictest2577496-21kworker/u8:4+events_unbound08:15:012
3403384994438,4cyclictest3666488-21kworker/u8:2+flush-8:011:40:021
3403384994438,4cyclictest3379406-21kworker/u8:0+flush-8:007:59:571
3403384994438,4cyclictest3379406-21kworker/u8:0+flush-8:007:45:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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