You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-08-30 - 08:24
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 3616 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot4.osadl.org (updated Sat Aug 30, 2025 01:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6448
"cycles":100000000,6447
"load":"idle",6446
"condition":{6445
"clock":"1100"6443
"family":"x86",6442
"vendor":"Intel",6441
"processor":{6439
"dataset":"2024-01-08T03:36:49+01:00"6437
"origin":"2024-01-08T00:43:22+01:00",6436
"timestamps":{6435
"granularity":"microseconds"6433
32409:38:396431
331,09:33:156430
"maxima":[6429
009:33:156426
0,09:33:156425
0,09:33:156424
0,09:33:156423
0,09:33:156422
0,09:33:156421
0,09:33:156420
0,09:33:156419
0,09:33:156418
0,09:33:156417
0,09:33:156416
0,09:33:156415
0,09:33:156414
0,09:33:156413
0,09:33:156412
0,09:33:156411
0,09:33:156410
0,09:33:156409
0,09:33:156408
0,09:33:156407
0,09:33:156406
0,09:33:156405
0,09:33:156404
0,09:33:156403
0,09:33:156402
0,09:33:156401
0,09:33:156400
0,09:33:156399
0,09:33:156398
0,09:33:156397
0,09:33:156396
0,09:33:156395
0,09:33:156394
0,09:33:156393
0,09:33:156392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional