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2025-10-31 - 13:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 3618 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot4.osadl.org (updated Fri Oct 31, 2025 01:42:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6448
"cycles":100000000,6447
"load":"idle",6446
"condition":{6445
"clock":"1100"6443
"family":"x86",6442
"vendor":"Intel",6441
"processor":{6439
"dataset":"2024-01-08T03:36:49+01:00"6437
"origin":"2024-01-08T00:43:22+01:00",6436
"timestamps":{6435
"granularity":"microseconds"6433
32417:11:486431
331,17:06:246430
"maxima":[6429
017:06:246426
0,17:06:246425
0,17:06:246424
0,17:06:246423
0,17:06:246422
0,17:06:246421
0,17:06:246420
0,17:06:246419
0,17:06:246418
0,17:06:246417
0,17:06:246416
0,17:06:246415
0,17:06:246414
0,17:06:246413
0,17:06:246412
0,17:06:246411
0,17:06:246410
0,17:06:246409
0,17:06:246408
0,17:06:246407
0,17:06:246406
0,17:06:246405
0,17:06:246404
0,17:06:246403
0,17:06:246402
0,17:06:246401
0,17:06:246400
0,17:06:246399
0,17:06:246398
0,17:06:246397
0,17:06:246396
0,17:06:246395
0,17:06:246394
0,17:06:246393
0,17:06:246392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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