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2024-04-18 - 04:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Thu Apr 18, 2024 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950650,0irq/26-eth1-rx-0-21swapper/119:08:081
110050640,0irq/25-eth00-21swapper/319:08:093
110050550,0irq/25-eth00-21swapper/219:06:202
1728124520,0sleep00-21swapper/019:07:050
271200,0ktimersoftd/24092-21sshd22:02:092
41190,0ktimersoftd/04105-21sshd22:02:100
191190,0ktimersoftd/14108-21sshd22:02:101
351180,0ktimersoftd/36893-21sshd21:51:253
271180,0ktimersoftd/22548-21sshd22:13:102
1758199180,0cyclictest0-21swapper/223:53:492
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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