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2025-08-26 - 21:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Tue Aug 26, 2025 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950610,0irq/26-eth1-rx-0-21swapper/107:06:111
117950590,0irq/26-eth1-rx-0-21swapper/007:05:590
110050590,0irq/25-eth00-21swapper/307:08:353
1948024927,0sleep20-21swapper/207:07:272
1975399200,0cyclictest0-21swapper/112:22:361
19754991613,0cyclictest17775-21bash11:22:502
19753991512,0cyclictest10903-21sshd11:49:441
1975299151,0cyclictest0-21swapper/009:23:120
1975599140,0cyclictest0-21swapper/309:40:363
19754991412,0cyclictest0-21swapper/209:16:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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