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2025-05-09 - 06:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Fri May 09, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050620,0irq/25-eth00-21swapper/119:05:281
110050600,0irq/25-eth00-21swapper/319:05:103
110050590,0irq/25-eth00-21swapper/219:06:472
9950560,0irq/24-0000:00:0-21swapper/019:05:340
2130099212,0cyclictest16493-21tr00:00:150
21303991613,0cyclictest0-21swapper/322:05:213
110050160,0irq/25-eth00-21swapper/023:05:150
21303991514,0cyclictest0-21swapper/322:35:053
21303991512,0cyclictest0-21swapper/322:18:003
41140,0ktimersoftd/00-21swapper/021:48:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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