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2026-09-24 - 04:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Thu Sep 24, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750690,0irq/25-eth00-21swapper/119:05:261
120650630,0irq/26-eth1-rx-351ktimersoftd/319:09:053
120750540,0irq/27-eth1-tx-0-21swapper/219:05:292
112750450,0irq/25-eth00-21swapper/019:05:330
41190,0ktimersoftd/06130-21diskmemload00:16:580
271180,0ktimersoftd/217359-21chrt20:23:362
271170,0ktimersoftd/26130-21diskmemload22:34:282
14214991613,0cyclictest14948-21sshd23:45:161
14216991513,0cyclictest22588-21munin-run23:50:003
1421699151,0cyclictest0-21swapper/321:12:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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