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2026-07-26 - 04:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Sun Jul 26, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750680,0irq/25-eth00-21swapper/119:05:161
112750640,0irq/25-eth00-21swapper/319:08:033
112750630,0irq/25-eth00-21swapper/219:06:152
9950470,0irq/24-0000:00:0-21swapper/019:05:360
21406991914,0cyclictest9968-21sshd23:16:393
271180,0ktimersoftd/219743-21sshd00:31:492
21405991615,0cyclictest0-21swapper/200:14:502
21406991512,0cyclictest0-21swapper/300:04:593
21406991413,0cyclictest13367-21diskmemload00:12:323
21406991412,0cyclictest0-21swapper/323:56:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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