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2025-06-29 - 01:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Sat Jun 28, 2025 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950620,0irq/26-eth1-rx-0-21swapper/107:05:361
117950620,0irq/26-eth1-rx-0-21swapper/107:05:361
110050610,0irq/25-eth00-21swapper/307:05:353
110050610,0irq/25-eth00-21swapper/307:05:343
117950590,0irq/26-eth1-rx-0-21swapper/007:07:300
117950590,0irq/26-eth1-rx-0-21swapper/007:07:300
110050550,0irq/25-eth00-21swapper/207:06:112
110050550,0irq/25-eth00-21swapper/207:06:102
13382991612,0cyclictest21470-21sshd09:33:431
13381991615,0cyclictest0-21swapper/009:20:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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