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2026-01-13 - 00:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Mon Jan 12, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650610,0irq/26-eth1-rx-0-21swapper/307:07:273
112750590,0irq/25-eth00-21swapper/207:08:312
112750590,0irq/25-eth00-21swapper/107:07:271
1941424320,0sleep00-21swapper/007:07:050
1971899140,0cyclictest0-21swapper/310:21:163
1971799140,0cyclictest0-21swapper/210:25:562
19716991412,0cyclictest0-21swapper/109:28:201
19715991412,0cyclictest0-21swapper/009:37:030
1971599140,0cyclictest0-21swapper/009:34:380
1971599140,0cyclictest0-21swapper/009:34:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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