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2026-02-11 - 21:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Wed Feb 11, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750640,0irq/25-eth00-21swapper/307:07:353
120650630,0irq/26-eth1-rx-0-21swapper/107:07:351
112750550,0irq/25-eth00-21swapper/207:09:002
120650450,0irq/26-eth1-rx-0-21swapper/007:08:070
16219991918,0cyclictest0-21swapper/111:22:051
16220991615,0cyclictest0-21swapper/210:49:212
1621899160,0cyclictest8264-21diskmemload11:20:240
1621899160,0cyclictest0-21swapper/007:55:190
1622199150,0cyclictest0-21swapper/308:45:193
16220991513,0cyclictest0-21swapper/210:01:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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