You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-29 - 16:15
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Mon Dec 29, 2025 12:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750660,0irq/25-eth00-21swapper/107:07:121
120650640,0irq/26-eth1-rx-0-21swapper/307:07:123
112750610,0irq/25-eth00-21swapper/207:08:412
130624721,0sleep00-21swapper/007:08:190
1535991513,0cyclictest0-21swapper/311:07:523
1535991513,0cyclictest0-21swapper/311:07:523
1534991511,0cyclictest0-21swapper/210:45:152
153499150,0cyclictest0-21swapper/207:45:202
153499150,0cyclictest0-21swapper/207:10:172
153399150,0cyclictest0-21swapper/107:30:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional