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2026-03-28 - 02:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Fri Mar 27, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/307:08:123
120650640,0irq/26-eth1-rx-0-21swapper/007:05:140
112750630,0irq/25-eth00-21swapper/107:09:281
1687924520,0sleep20-21swapper/207:08:342
41190,0ktimersoftd/09016-21diskmemload11:36:480
351180,0ktimersoftd/327816-21sshd11:36:493
17068991817,0cyclictest0-21swapper/312:37:473
112750150,0irq/25-eth036-21ksoftirqd/312:21:453
17068991413,0cyclictest0-21swapper/311:18:553
1706699140,0cyclictest27975-21sshd11:32:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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