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2026-02-25 - 23:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Wed Feb 25, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650660,0irq/26-eth1-rx-0-21swapper/107:08:141
120650590,0irq/26-eth1-rx-0-21swapper/307:06:293
112750590,0irq/25-eth00-21swapper/207:06:242
112750420,0irq/25-eth00-21swapper/007:08:420
2049199180,0cyclictest1480-21nfsd11:48:352
20490991512,0cyclictest0-21swapper/111:29:171
20492991413,0cyclictest0-21swapper/312:35:383
20492991413,0cyclictest0-21swapper/312:34:083
20492991413,0cyclictest0-21swapper/312:17:593
20492991413,0cyclictest0-21swapper/311:53:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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