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2025-12-22 - 00:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Sun Dec 21, 2025 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650660,0irq/26-eth1-rx-0-21swapper/107:07:351
120650600,0irq/26-eth1-rx-0-21swapper/307:09:203
2693724520,0sleep20-21swapper/207:07:542
2679724420,0sleep00-21swapper/007:06:080
2718199220,0cyclictest0-21swapper/212:15:172
27181991615,0cyclictest19097-21diskmemload11:53:062
27180991411,0cyclictest0-21swapper/111:34:231
2718099140,0cyclictest0-21swapper/111:38:201
27179991413,0cyclictest19097-21diskmemload10:24:060
27179991412,0cyclictest0-21swapper/011:37:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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