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2026-06-26 - 04:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Fri Jun 26, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750600,0irq/25-eth00-21swapper/219:08:332
112750580,0irq/25-eth00-21swapper/119:08:581
112750570,0irq/25-eth00-21swapper/319:06:203
112750440,0irq/25-eth00-21swapper/019:05:180
3232799180,0cyclictest32132-21sshd23:37:070
32328991715,0cyclictest0-21swapper/100:28:061
3233099150,0cyclictest0-21swapper/300:00:173
112750150,0irq/25-eth00-21swapper/123:20:571
41140,0ktimersoftd/07698-21sshd22:55:270
3233099140,0cyclictest13717-21sshd21:35:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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