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2025-10-23 - 09:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Thu Oct 23, 2025 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950620,0irq/26-eth1-rx-0-21swapper/119:09:071
110050590,0irq/25-eth00-21swapper/319:05:163
110050550,0irq/25-eth00-21swapper/219:05:332
117950490,0irq/26-eth1-rx-0-21swapper/019:05:320
271180,0ktimersoftd/230531-21bash22:53:522
2182999170,0cyclictest0-21swapper/023:24:520
21832991615,0cyclictest0-21swapper/323:43:503
2183099160,0cyclictest0-21swapper/123:55:221
110050160,0irq/25-eth02774-21sshd21:45:471
2183199150,0cyclictest0-21swapper/222:07:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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