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2025-11-07 - 22:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Fri Nov 07, 2025 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950660,0irq/26-eth1-rx-0-21swapper/307:05:463
110050640,0irq/25-eth00-21swapper/107:05:461
110050550,0irq/25-eth00-21swapper/207:08:202
782324920,0sleep00-21swapper/007:05:590
8217991817,0cyclictest478-21jbd2/dm-0-812:14:560
8217991717,0cyclictest0-21swapper/011:23:170
8218991514,0cyclictest18143-21memory10:20:191
8217991514,0cyclictest0-21swapper/011:55:070
8220991413,0cyclictest1453-21nfsd10:58:343
8219991413,0cyclictest22416-21sshd09:28:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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