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2026-08-25 - 04:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Tue Aug 25, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750690,0irq/25-eth00-21swapper/119:08:071
120650630,0irq/26-eth1-rx-0-21swapper/319:07:433
112750560,0irq/25-eth00-21swapper/219:06:002
9950540,0irq/24-0000:00:0-21swapper/019:05:340
191190,0ktimersoftd/18626-21sshd00:16:471
351180,0ktimersoftd/30-21swapper/300:16:473
271180,0ktimersoftd/28625-21sshd00:16:472
2271799180,0cyclictest28397-21sshd22:56:043
22717991514,0cyclictest12559-21sshd23:28:053
22716991514,0cyclictest14626-21diskmemload22:10:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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