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2026-05-27 - 03:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Wed May 27, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750590,0irq/25-eth00-21swapper/119:06:081
112750570,0irq/25-eth00-21swapper/319:05:263
112750480,0irq/25-eth00-21swapper/219:05:142
120650450,0irq/26-eth1-rx-0-21swapper/019:07:450
10162991615,0cyclictest0-21swapper/322:58:043
1016299155,0cyclictest0-21swapper/321:50:163
1016099150,0cyclictest0-21swapper/121:40:141
10159991511,0cyclictest2960-21sshd22:18:050
1015999150,0cyclictest0-21swapper/021:40:200
10161991413,0cyclictest0-21swapper/223:36:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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