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2026-05-12 - 09:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Tue May 12, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650600,0irq/26-eth1-rx-0-21swapper/319:09:573
120650600,0irq/26-eth1-rx-0-21swapper/119:09:231
112750560,0irq/25-eth00-21swapper/219:07:282
112750450,0irq/25-eth00-21swapper/019:05:120
1732699200,0cyclictest0-21swapper/322:47:293
17326991918,0cyclictest0-21swapper/322:40:543
1732599160,0cyclictest0-21swapper/219:35:192
17326991514,0cyclictest0-21swapper/323:25:423
17326991514,0cyclictest0-21swapper/322:54:483
17324991514,0cyclictest0-21swapper/123:55:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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