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2026-02-01 - 20:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Feb 01, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750660,0irq/25-eth00-21swapper/307:05:203
120650650,0irq/26-eth1-rx-0-21swapper/107:07:411
112750540,0irq/25-eth00-21swapper/207:07:522
2010124126,0sleep00-21swapper/007:06:420
20440991817,0cyclictest0-21swapper/311:27:463
41150,0ktimersoftd/029610-21sshd11:35:230
2044099150,0cyclictest0-21swapper/308:40:193
2043999150,0cyclictest0-21swapper/209:15:132
41140,0ktimersoftd/00-21swapper/009:56:310
20440991413,0cyclictest0-21swapper/310:40:153
20440991413,0cyclictest0-21swapper/310:16:333
2044099140,0cyclictest0-21swapper/311:32:103
2044099140,0cyclictest0-21swapper/310:30:093
2044099140,0cyclictest0-21swapper/309:48:473
20438991413,0cyclictest0-21swapper/112:18:211
2043899140,0cyclictest15889-21bash10:34:011
20440991312,0cyclictest0-21swapper/310:48:103
20440991310,0cyclictest0-21swapper/311:35:273
2044099130,0cyclictest0-21swapper/309:41:003
20439991312,0cyclictest5182-21sshd10:37:172
20439991312,0cyclictest0-21swapper/212:01:302
20439991312,0cyclictest0-21swapper/210:00:402
20439991312,0cyclictest0-21swapper/209:49:182
2043999130,0cyclictest0-21swapper/211:20:502
20438991311,0cyclictest23701-21sshd11:14:551
2043899130,0cyclictest0-21swapper/112:10:541
2043899130,0cyclictest0-21swapper/110:56:261
2043899130,0cyclictest0-21swapper/109:34:531
20437991313,0cyclictest112750irq/25-eth010:31:500
20437991312,0cyclictest0-21swapper/012:13:080
20437991312,0cyclictest0-21swapper/009:42:280
20437991311,0cyclictest0-21swapper/011:34:200
2043799130,0cyclictest15080-21bash11:28:250
191130,0ktimersoftd/19098-21sshd11:27:281
191130,0ktimersoftd/10-21swapper/112:28:341
112750130,0irq/25-eth00-21swapper/112:23:191
20440991212,0cyclictest0-21swapper/311:45:403
20440991212,0cyclictest0-21swapper/310:03:533
20440991211,0cyclictest5916-21sshd12:21:273
20440991211,0cyclictest14266-21id11:23:223
20440991211,0cyclictest0-21swapper/312:33:233
20440991211,0cyclictest0-21swapper/312:10:183
20440991211,0cyclictest0-21swapper/312:04:503
20440991211,0cyclictest0-21swapper/311:06:233
20440991211,0cyclictest0-21swapper/309:32:463
20440991210,0cyclictest0-21swapper/310:11:063
2044099120,0cyclictest0-21swapper/312:35:093
2044099120,0cyclictest0-21swapper/311:10:353
2044099120,0cyclictest0-21swapper/311:02:373
2044099120,0cyclictest0-21swapper/310:28:103
2044099120,0cyclictest0-21swapper/309:27:253
20439991211,0cyclictest5213-21sshd12:36:112
20439991211,0cyclictest1422-21rm10:51:332
20439991211,0cyclictest0-21swapper/210:19:152
20439991211,0cyclictest0-21swapper/209:53:002
20439991210,0cyclictest0-21swapper/212:06:572
20439991210,0cyclictest0-21swapper/209:25:012
2043999120,0cyclictest1539-21sshd10:58:302
2043999120,0cyclictest1102-21sshd12:10:402
2043999120,0cyclictest0-21swapper/212:34:012
2043999120,0cyclictest0-21swapper/211:25:152
20438991211,0cyclictest12486-21diskmemload10:29:501
20438991211,0cyclictest0-21swapper/110:36:001
20438991211,0cyclictest0-21swapper/110:23:541
20438991210,0cyclictest0-21swapper/110:52:161
20438991210,0cyclictest0-21swapper/110:07:181
2043899120,0cyclictest0-21swapper/111:37:201
2043799129,0cyclictest0-21swapper/007:11:340
20437991211,0cyclictest20641-21sshd09:25:440
20437991211,0cyclictest0-21swapper/012:03:580
20437991211,0cyclictest0-21swapper/011:51:320
20437991210,0cyclictest0-21swapper/010:46:070
20437991210,0cyclictest0-21swapper/010:12:190
20437991210,0cyclictest0-21swapper/009:39:350
2043799120,0cyclictest20641-21sshd10:19:590
2043799120,0cyclictest0-21swapper/012:37:590
2043799120,0cyclictest0-21swapper/008:41:500
191120,0ktimersoftd/10-21swapper/112:06:441
191120,0ktimersoftd/10-21swapper/109:28:371
112750120,0irq/25-eth021777-21crond10:30:000
41110,0ktimersoftd/00-21swapper/011:10:040
20440991111,0cyclictest0-21swapper/311:43:543
20440991111,0cyclictest0-21swapper/308:24:273
20440991111,0cyclictest0-21swapper/308:00:533
20440991111,0cyclictest0-21swapper/307:40:253
20440991110,0cyclictest24094-21sshd12:09:223
20440991110,0cyclictest19139-21sshd09:50:143
20440991110,0cyclictest0-21swapper/309:17:123
20440991110,0cyclictest0-21swapper/309:12:193
2044099110,0cyclictest0-21swapper/307:51:563
2043999119,0cyclictest12579-21sshd10:43:252
20439991111,0cyclictest30549-21sshd11:05:502
20439991111,0cyclictest0-21swapper/212:23:472
20439991111,0cyclictest0-21swapper/211:16:252
20439991111,0cyclictest0-21swapper/209:30:212
20439991110,0cyclictest0-21swapper/209:58:422
2043999110,0cyclictest16303-21bash10:29:082
2043999110,0cyclictest0-21swapper/210:11:502
2043999110,0cyclictest0-21swapper/209:04:552
2043999110,0cyclictest0-21swapper/208:03:492
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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