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2026-01-15 - 19:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Thu Jan 15, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750650,0irq/25-eth00-21swapper/107:08:061
120650620,0irq/26-eth1-rx-0-21swapper/307:07:213
970325126,0sleep00-21swapper/007:08:130
120650440,0irq/26-eth1-rx-0-21swapper/207:08:482
9914991711,0cyclictest0-21swapper/011:38:430
991799150,0cyclictest0-21swapper/309:30:143
9916991413,0cyclictest1387-21sshd09:26:112
991699140,0cyclictest0-21swapper/210:05:212
9914991413,0cyclictest0-21swapper/010:05:270
9917991312,0cyclictest0-21swapper/311:08:193
9917991312,0cyclictest0-21swapper/310:42:183
9917991312,0cyclictest0-21swapper/309:15:253
9917991310,0cyclictest1938-21sshd09:48:313
9916991312,0cyclictest0-21swapper/212:05:412
9916991312,0cyclictest0-21swapper/211:32:562
9916991312,0cyclictest0-21swapper/209:33:102
9916991311,0cyclictest0-21swapper/209:42:072
9915991312,0cyclictest0-21swapper/110:02:001
9915991311,0cyclictest0-21swapper/112:05:071
9915991310,0cyclictest31119-21ntp_states09:00:181
991599130,0cyclictest29523-21sshd09:47:381
9914991312,0cyclictest16464-21sshd11:19:390
9914991312,0cyclictest0-21swapper/012:00:350
9914991312,0cyclictest0-21swapper/010:20:120
112750130,0irq/25-eth00-21swapper/311:27:153
112750130,0irq/25-eth00-21swapper/310:55:193
112750130,0irq/25-eth00-21swapper/310:28:143
9917991211,0cyclictest0-21swapper/312:30:273
9917991211,0cyclictest0-21swapper/312:10:573
9917991211,0cyclictest0-21swapper/310:23:503
9917991210,0cyclictest0-21swapper/312:26:303
991799120,0cyclictest0-21swapper/311:24:003
991799120,0cyclictest0-21swapper/311:14:383
991699123,0cyclictest0-21swapper/207:40:002
9916991211,0cyclictest0-21swapper/211:06:342
9916991210,0cyclictest0-21swapper/210:58:052
991699120,0cyclictest4500-21sshd11:50:492
991699120,0cyclictest0-21swapper/211:41:522
991699120,0cyclictest0-21swapper/210:18:212
991699120,0cyclictest0-21swapper/210:00:352
991699120,0cyclictest0-21swapper/207:30:152
991599129,0cyclictest14494-21sshd12:20:271
9915991211,0cyclictest22558-21sshd09:35:161
9915991211,0cyclictest0-21swapper/111:12:581
9915991211,0cyclictest0-21swapper/110:54:301
9915991211,0cyclictest0-21swapper/110:06:451
9915991211,0cyclictest0-21swapper/109:57:141
9915991211,0cyclictest0-21swapper/109:42:011
991599120,0cyclictest0-21swapper/112:34:311
991599120,0cyclictest0-21swapper/112:01:251
991599120,0cyclictest0-21swapper/111:56:371
991599120,0cyclictest0-21swapper/111:39:351
991599120,0cyclictest0-21swapper/111:28:531
991599120,0cyclictest0-21swapper/111:19:561
991599120,0cyclictest0-21swapper/110:20:161
991599120,0cyclictest0-21swapper/109:11:421
9914991211,0cyclictest0-21swapper/011:49:250
9914991211,0cyclictest0-21swapper/011:31:310
9914991211,0cyclictest0-21swapper/010:43:540
991499120,0cyclictest0-21swapper/011:20:500
991499120,0cyclictest0-21swapper/009:22:490
112750120,0irq/25-eth018360-21bash11:59:030
112750120,0irq/25-eth00-21swapper/112:26:521
112750120,0irq/25-eth00-21swapper/012:08:320
112750120,0irq/25-eth00-21swapper/010:04:450
9917991111,0cyclictest0-21swapper/312:36:373
9917991111,0cyclictest0-21swapper/311:41:393
9917991111,0cyclictest0-21swapper/310:51:493
9917991111,0cyclictest0-21swapper/310:35:343
9917991111,0cyclictest0-21swapper/310:04:183
9917991110,0cyclictest32302-21sshd10:15:353
9917991110,0cyclictest0-21swapper/309:13:113
991799110,0cyclictest0-21swapper/312:16:513
991799110,0cyclictest0-21swapper/311:38:103
991699119,0cyclictest112750irq/25-eth012:37:472
9916991111,0cyclictest0-21swapper/210:28:212
9916991111,0cyclictest0-21swapper/210:13:222
9916991111,0cyclictest0-21swapper/208:15:132
9916991110,0cyclictest1936-21diskmemload12:24:582
9916991110,0cyclictest16818-21sshd11:58:462
9916991110,0cyclictest0-21swapper/211:22:152
9916991110,0cyclictest0-21swapper/210:46:492
9916991110,0cyclictest0-21swapper/209:13:452
991699110,0cyclictest27666-21grep08:55:112
991699110,0cyclictest0-21swapper/212:33:062
991699110,0cyclictest0-21swapper/209:55:492
991599119,0cyclictest0-21swapper/109:29:341
9915991111,0cyclictest0-21swapper/111:21:411
9915991111,0cyclictest0-21swapper/109:19:221
9915991110,0cyclictest13753-21sshd11:41:191
9915991110,0cyclictest0-21swapper/111:52:001
9915991110,0cyclictest0-21swapper/110:31:301
9915991110,0cyclictest0-21swapper/110:31:301
9915991110,0cyclictest0-21swapper/110:19:451
991599110,0cyclictest15605-21sshd11:02:451
9914991111,0cyclictest0-21swapper/010:56:400
9914991111,0cyclictest0-21swapper/009:57:260
9914991111,0cyclictest0-21swapper/008:25:040
9914991110,0cyclictest7018-21sshd09:49:250
9914991110,0cyclictest26514-21bash11:54:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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