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2026-01-19 - 18:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Mon Jan 19, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650670,0irq/26-eth1-rx-0-21swapper/107:09:471
120650640,0irq/26-eth1-rx-0-21swapper/307:06:383
112750540,0irq/25-eth00-21swapper/207:09:322
2002824521,0sleep00-21swapper/007:07:320
20300991715,0cyclictest31638-21munin-run09:30:002
20301991611,0cyclictest17288-21diskstats08:10:113
20301991513,0cyclictest0-21swapper/311:37:333
20301991512,0cyclictest0-21swapper/310:44:223
20301991510,0cyclictest8021-21sshd10:49:563
2029999151,0cyclictest0-21swapper/112:25:531
20301991413,0cyclictest12316-21diskmemload09:46:583
20301991412,0cyclictest0-21swapper/311:03:173
20301991411,0cyclictest0-21swapper/312:12:593
20300991413,0cyclictest0-21swapper/209:48:522
2030099140,0cyclictest0-21swapper/210:19:042
20298991411,0cyclictest0-21swapper/011:32:590
191140,0ktimersoftd/10-21swapper/110:50:171
20301991312,0cyclictest0-21swapper/309:59:593
20301991311,0cyclictest12316-21diskmemload12:31:073
20301991311,0cyclictest0-21swapper/309:39:323
2030199130,0cyclictest0-21swapper/311:30:433
20300991312,0cyclictest24236-21sshd10:24:392
20300991311,0cyclictest0-21swapper/209:18:252
20300991310,0cyclictest8126-21sshd10:27:192
20300991310,0cyclictest0-21swapper/212:11:392
2030099130,0cyclictest0-21swapper/209:33:462
20299991312,0cyclictest12316-21diskmemload09:40:141
20299991312,0cyclictest12316-21diskmemload09:32:471
20298991312,0cyclictest2632-21bash10:43:160
20298991312,0cyclictest0-21swapper/011:00:270
20298991312,0cyclictest0-21swapper/010:04:280
20298991312,0cyclictest0-21swapper/009:51:270
2029899130,0cyclictest6819-21sshd10:10:160
20301991211,0cyclictest0-21swapper/309:50:203
20301991211,0cyclictest0-21swapper/309:21:043
20301991210,0cyclictest24287-21sshd09:17:273
20301991210,0cyclictest23428-21sshd09:28:303
20301991210,0cyclictest0-21swapper/312:24:163
2030199120,0cyclictest0-21swapper/311:12:353
2030199120,0cyclictest0-21swapper/310:11:503
2030099125,0cyclictest0-21swapper/211:01:492
20300991212,0cyclictest0-21swapper/210:43:582
20300991211,0cyclictest0-21swapper/212:18:152
20300991211,0cyclictest0-21swapper/212:06:452
20300991211,0cyclictest0-21swapper/210:13:302
20300991211,0cyclictest0-21swapper/210:01:532
20300991210,0cyclictest0-21swapper/209:22:162
20300991210,0cyclictest0-21swapper/209:10:042
2030099120,0cyclictest0-21swapper/211:54:332
2030099120,0cyclictest0-21swapper/210:49:232
20299991212,0cyclictest0-21swapper/109:47:411
20299991211,0cyclictest13530-21sshd11:02:011
20299991211,0cyclictest0-21swapper/112:37:241
20299991211,0cyclictest0-21swapper/112:02:391
20299991210,0cyclictest30389-21sshd09:57:331
20299991210,0cyclictest0-21swapper/112:16:501
20299991210,0cyclictest0-21swapper/109:21:321
2029999120,0cyclictest32307-21sshd10:59:501
20298991211,0cyclictest0-21swapper/011:51:480
20298991211,0cyclictest0-21swapper/011:42:160
20298991211,0cyclictest0-21swapper/009:17:250
20298991210,0cyclictest0-21swapper/011:09:450
2029899120,0cyclictest23454-21sshd11:37:370
2029899120,0cyclictest0-21swapper/012:25:010
2029899120,0cyclictest0-21swapper/012:18:100
2029899120,0cyclictest0-21swapper/012:04:000
2029899120,0cyclictest0-21swapper/010:18:310
2029899120,0cyclictest0-21swapper/009:40:250
2029899120,0cyclictest0-21swapper/007:35:190
191120,0ktimersoftd/10-21swapper/109:35:221
112750120,0irq/25-eth00-21swapper/312:08:563
112750120,0irq/25-eth00-21swapper/211:32:232
351110,0ktimersoftd/30-21swapper/310:36:343
20301991111,0cyclictest0-21swapper/311:23:513
20301991111,0cyclictest0-21swapper/310:30:463
20301991110,0cyclictest112750irq/25-eth012:25:223
20301991110,0cyclictest0-21swapper/311:51:303
20301991110,0cyclictest0-21swapper/309:12:053
2030199110,0cyclictest0-21swapper/310:20:043
2030199110,0cyclictest0-21swapper/308:58:253
2030199110,0cyclictest0-21swapper/308:25:593
2030199110,0cyclictest0-21swapper/308:21:013
2030199110,0cyclictest0-21swapper/308:21:003
2030199110,0cyclictest0-21swapper/308:06:363
2030199110,0cyclictest0-21swapper/307:31:383
2030099115,0cyclictest486-21sshd11:28:032
2030099114,0cyclictest0-21swapper/210:55:252
20300991110,0cyclictest0-21swapper/212:25:072
20300991110,0cyclictest0-21swapper/211:49:412
20300991110,0cyclictest0-21swapper/211:42:362
20300991110,0cyclictest0-21swapper/211:35:302
20300991110,0cyclictest0-21swapper/207:20:112
2030099110,0cyclictest0-21swapper/211:59:272
2030099110,0cyclictest0-21swapper/210:52:182
2030099110,0cyclictest0-21swapper/209:37:362
2030099110,0cyclictest0-21swapper/208:35:342
2030099110,0cyclictest0-21swapper/207:28:392
20299991111,0cyclictest0-21swapper/111:48:161
20299991111,0cyclictest0-21swapper/111:18:241
20299991111,0cyclictest0-21swapper/111:11:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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