You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-06 - 09:17
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Dec 06, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950650,0irq/26-eth1-rx-0-21swapper/119:05:391
110050610,0irq/25-eth00-21swapper/219:08:482
117950600,0irq/26-eth1-rx-0-21swapper/319:07:393
110050410,0irq/25-eth00-21swapper/019:05:470
12009992011,0cyclictest27775-21sshd23:34:403
12007991716,0cyclictest0-21swapper/100:00:331
1200699160,0cyclictest7463-21sshd21:32:490
1200999151,0cyclictest0-21swapper/322:10:223
1200699150,0cyclictest0-21swapper/022:34:570
12009991413,0cyclictest12685-21bash23:39:543
12009991411,0cyclictest2295-21cat19:55:143
12009991411,0cyclictest0-21swapper/322:35:113
1200999140,0cyclictest19098-21cp00:29:233
12008991413,0cyclictest28920-21sshd21:12:272
12008991413,0cyclictest0-21swapper/222:56:112
12008991412,0cyclictest0-21swapper/222:00:392
12008991412,0cyclictest0-21swapper/221:58:472
12007991414,0cyclictest13095-21sshd21:10:481
12007991412,0cyclictest2666-21sshd23:59:041
12006991413,0cyclictest0-21swapper/021:53:220
110050140,0irq/25-eth00-21swapper/222:34:342
12009991312,0cyclictest30754-21sshd22:07:123
12009991312,0cyclictest0-21swapper/321:17:353
12009991312,0cyclictest0-21swapper/300:18:213
12009991311,0cyclictest0-21swapper/322:32:173
12009991311,0cyclictest0-21swapper/300:07:183
1200999130,0cyclictest6364-21sshd23:22:073
1200999130,0cyclictest0-21swapper/321:13:463
12008991312,0cyclictest0-21swapper/222:35:212
12008991312,0cyclictest0-21swapper/221:48:002
12008991312,0cyclictest0-21swapper/221:41:152
1200899130,0cyclictest0-21swapper/222:10:172
1200899130,0cyclictest0-21swapper/219:35:192
12007991312,0cyclictest14979-21sshd00:14:161
12007991311,0cyclictest31639-21munin-run20:59:591
1200799130,0cyclictest0-21swapper/121:35:211
12006991312,0cyclictest25503-21sshd00:38:190
12006991312,0cyclictest0-21swapper/023:45:350
12006991312,0cyclictest0-21swapper/022:59:000
12006991311,0cyclictest0-21swapper/022:37:160
1200699131,0cyclictest29760-21sshd22:47:090
110050130,0irq/25-eth028987-21latency_hist19:45:003
110050130,0irq/25-eth00-21swapper/200:15:032
110050130,0irq/25-eth00-21swapper/122:48:591
41120,0ktimersoftd/020317-21rm21:40:210
41120,0ktimersoftd/00-21swapper/023:20:160
41120,0ktimersoftd/00-21swapper/023:01:320
271120,0ktimersoftd/232319-21timerwakeupswit00:05:322
191120,0ktimersoftd/10-21swapper/122:38:121
191120,0ktimersoftd/10-21swapper/121:46:081
12009991211,0cyclictest31836-21sshd23:04:303
12009991211,0cyclictest13177-21sshd21:55:423
12009991211,0cyclictest0-21swapper/323:51:383
12009991210,0cyclictest0-21swapper/323:40:283
1200999120,0cyclictest7924-21sshd21:26:253
12008991211,0cyclictest9074-21sshd23:59:432
12008991211,0cyclictest0-21swapper/222:09:082
12008991210,0cyclictest9950irq/24-0000:00:23:10:442
12008991210,0cyclictest0-21swapper/220:35:172
12008991210,0cyclictest0-21swapper/220:21:122
1200899120,0cyclictest0-21swapper/219:50:192
12007991211,0cyclictest3915-21diskmemload23:27:551
12007991211,0cyclictest3915-21diskmemload22:00:401
12007991211,0cyclictest22300-21sshd21:59:591
12007991211,0cyclictest0-21swapper/122:09:091
1200799120,0cyclictest0-21swapper/121:41:171
1200799120,0cyclictest0-21swapper/120:00:131
12006991212,0cyclictest0-21swapper/021:21:250
1200699121,0cyclictest0-21swapper/022:09:170
12006991210,0cyclictest0-21swapper/022:51:270
1200699120,0cyclictest0-21swapper/022:01:580
1200699120,0cyclictest0-21swapper/019:35:200
110050120,0irq/25-eth04005-21bash22:54:341
110050120,0irq/25-eth032379-21turbostat23:25:001
110050120,0irq/25-eth014309-21sshd23:05:552
110050120,0irq/25-eth00-21swapper/323:09:283
110050120,0irq/25-eth00-21swapper/300:13:563
110050120,0irq/25-eth00-21swapper/121:26:311
110050120,0irq/25-eth00-21swapper/100:33:261
110050120,0irq/25-eth00-21swapper/100:24:081
41110,0ktimersoftd/03915-21diskmemload23:51:340
41110,0ktimersoftd/03915-21diskmemload00:17:290
41110,0ktimersoftd/019717-21bash22:19:110
41110,0ktimersoftd/00-21swapper/023:39:330
351110,0ktimersoftd/321292-21sshd22:15:523
191110,0ktimersoftd/13915-21diskmemload23:39:171
12009991111,0cyclictest0-21swapper/323:27:423
12009991110,0cyclictest18554-21sshd22:55:593
1200999110,0cyclictest4225-21sshd00:20:063
1200999110,0cyclictest1056-21sshd22:27:243
1200999110,0cyclictest0-21swapper/320:50:203
12008991111,0cyclictest0-21swapper/221:36:302
12008991111,0cyclictest0-21swapper/220:54:332
12008991110,0cyclictest13212-21sshd21:20:282
1200899110,0cyclictest12406-21sshd23:29:412
1200899110,0cyclictest0-21swapper/220:02:032
1200899110,0cyclictest0-21swapper/219:45:472
1200899110,0cyclictest0-21swapper/219:27:182
1200899110,0cyclictest0-21swapper/219:15:072
12007991111,0cyclictest20468-21sshd22:59:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional