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2026-02-05 - 18:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Thu Feb 05, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750600,0irq/25-eth00-21swapper/319:05:133
120650580,0irq/26-eth1-rx-0-21swapper/119:08:181
112750580,0irq/25-eth00-21swapper/219:08:232
120650430,0irq/26-eth1-rx-0-21swapper/019:06:330
2160699190,0cyclictest16218-21sshd23:26:113
2160699160,0cyclictest0-21swapper/323:11:383
21605991514,0cyclictest0-21swapper/200:22:492
2160399150,0cyclictest0-21swapper/020:40:140
2160699140,0cyclictest0-21swapper/323:09:573
2160599140,0cyclictest0-21swapper/222:18:032
21604991413,0cyclictest13640-21diskmemload00:05:201
21604991413,0cyclictest0-21swapper/123:11:401
2160499140,0cyclictest0-21swapper/119:55:221
2160499140,0cyclictest0-21swapper/119:30:221
21603991411,0cyclictest13640-21diskmemload23:03:550
112750140,0irq/25-eth01659-21sshd21:22:411
41130,0ktimersoftd/011008-21latency_hist23:45:000
271130,0ktimersoftd/20-21swapper/221:19:382
21606991312,0cyclictest25365-21sshd22:58:313
21606991312,0cyclictest25208-21id22:19:363
21606991312,0cyclictest0-21swapper/322:01:503
21606991312,0cyclictest0-21swapper/300:17:513
21606991311,0cyclictest0-21swapper/321:40:473
2160599130,0cyclictest0-21swapper/223:48:542
21604991312,0cyclictest7606-21sshd23:25:011
21604991312,0cyclictest0-21swapper/100:22:451
21604991311,0cyclictest0-21swapper/121:27:001
21604991311,0cyclictest0-21swapper/121:10:441
21603991312,0cyclictest13640-21diskmemload22:41:370
21603991311,0cyclictest22967-21sshd21:25:460
2160399130,0cyclictest0-21swapper/022:39:520
191130,0ktimersoftd/10-21swapper/122:02:051
21606991212,0cyclictest0-21swapper/322:35:103
21606991211,0cyclictest0-21swapper/322:47:363
21606991211,0cyclictest0-21swapper/322:33:253
21606991211,0cyclictest0-21swapper/321:38:083
21606991211,0cyclictest0-21swapper/300:07:033
21606991210,0cyclictest0-21swapper/321:25:283
21606991210,0cyclictest0-21swapper/300:26:273
2160699120,0cyclictest13640-21diskmemload22:53:033
2160699120,0cyclictest0-21swapper/323:17:483
2160699120,0cyclictest0-21swapper/322:25:453
2160699120,0cyclictest0-21swapper/300:39:423
21605991211,0cyclictest1903-21sshd22:50:092
21605991211,0cyclictest0-21swapper/223:58:322
21605991211,0cyclictest0-21swapper/223:09:032
21605991210,0cyclictest13640-21diskmemload23:03:222
21605991210,0cyclictest0-21swapper/222:57:402
2160599120,0cyclictest0-21swapper/223:11:032
2160599120,0cyclictest0-21swapper/221:38:202
21604991212,0cyclictest0-21swapper/121:16:331
21604991211,0cyclictest0-21swapper/123:49:041
21604991211,0cyclictest0-21swapper/123:35:561
21604991211,0cyclictest0-21swapper/121:47:541
21604991211,0cyclictest0-21swapper/100:00:561
21604991210,0cyclictest0-21swapper/122:56:341
21604991210,0cyclictest0-21swapper/122:21:081
2160499120,0cyclictest0-21swapper/121:55:421
2160499120,0cyclictest0-21swapper/100:27:111
21603991212,0cyclictest0-21swapper/022:06:320
21603991211,0cyclictest0-21swapper/023:47:290
21603991211,0cyclictest0-21swapper/022:28:570
21603991211,0cyclictest0-21swapper/021:52:150
21603991211,0cyclictest0-21swapper/021:30:520
21603991210,0cyclictest28562-21sshd23:13:340
21603991210,0cyclictest0-21swapper/023:36:060
2160399120,0cyclictest0-21swapper/021:36:130
2160399120,0cyclictest0-21swapper/000:14:470
191120,0ktimersoftd/10-21swapper/122:53:321
112750120,0irq/25-eth028308-21sshd23:37:473
41110,0ktimersoftd/00-21swapper/000:23:430
2160699119,0cyclictest0-21swapper/320:44:133
21606991111,0cyclictest0-21swapper/323:56:293
21606991110,0cyclictest5210-21cp21:52:173
21606991110,0cyclictest478-21sshd00:22:233
21606991110,0cyclictest31941-21sshd22:10:423
21606991110,0cyclictest30519-21sshd22:05:373
21606991110,0cyclictest30509-21sshd23:47:523
21606991110,0cyclictest27053-21sshd21:11:533
21606991110,0cyclictest25909-21sshd21:31:033
21606991110,0cyclictest23768-21sshd23:41:553
21606991110,0cyclictest23679-21bash23:51:373
21606991110,0cyclictest23292-21sshd21:55:023
21606991110,0cyclictest16305-21bash23:01:573
21606991110,0cyclictest13364-21bash00:04:513
21606991110,0cyclictest0-21swapper/321:15:433
2160699110,0cyclictest0-21swapper/320:59:193
2160699110,0cyclictest0-21swapper/320:48:043
2160699110,0cyclictest0-21swapper/320:36:063
21605991111,0cyclictest0-21swapper/221:54:222
21605991111,0cyclictest0-21swapper/200:02:572
21605991110,0cyclictest27920-21id23:23:102
21605991110,0cyclictest23837-21sshd21:11:232
21605991110,0cyclictest14329-21sshd23:35:332
21605991110,0cyclictest11643-21bash22:32:042
21605991110,0cyclictest11125-21sshd21:24:092
21605991110,0cyclictest0-21swapper/221:58:172
21605991110,0cyclictest0-21swapper/221:30:182
21605991110,0cyclictest0-21swapper/200:29:122
21605991110,0cyclictest0-21swapper/200:05:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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