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2026-01-26 - 20:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Mon Jan 26, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650590,0irq/26-eth1-rx-0-21swapper/307:05:283
120650590,0irq/26-eth1-rx-0-21swapper/107:08:481
112750550,0irq/25-eth00-21swapper/207:05:452
1274324821,0sleep00-21swapper/007:06:060
1312499221,0cyclictest2539-21sshd11:22:230
13124992120,0cyclictest0-21swapper/010:24:300
1312799170,0cyclictest0-21swapper/311:51:073
13127991615,0cyclictest19339-21sshd09:41:203
13127991512,0cyclictest0-21swapper/310:11:193
1312799150,0cyclictest0-21swapper/310:05:203
13124991514,0cyclictest0-21swapper/009:22:490
13124991511,0cyclictest21462-21bash10:35:530
13127991412,0cyclictest0-21swapper/312:33:513
13127991411,0cyclictest0-21swapper/309:53:533
1312799140,0cyclictest0-21swapper/309:06:433
1312799140,0cyclictest0-21swapper/307:45:203
13126991413,0cyclictest5170-21diskmemload09:30:282
1312699140,0cyclictest0-21swapper/210:06:072
13125991413,0cyclictest0-21swapper/109:28:171
13125991411,0cyclictest0-21swapper/112:19:521
1312599140,0cyclictest0-21swapper/110:18:491
1312499141,0cyclictest4969-21sshd10:28:340
13127991312,0cyclictest14523-21sshd11:14:233
13127991312,0cyclictest0-21swapper/311:08:253
13127991312,0cyclictest0-21swapper/310:22:493
13127991312,0cyclictest0-21swapper/310:03:323
13127991311,0cyclictest0-21swapper/308:55:203
13127991311,0cyclictest0-21swapper/308:41:383
13127991310,0cyclictest0-21swapper/308:48:293
1312799130,0cyclictest0-21swapper/308:30:123
13126991312,0cyclictest0-21swapper/211:25:352
13126991312,0cyclictest0-21swapper/211:18:582
1312699130,0cyclictest2648-21sshd11:42:052
13125991312,0cyclictest0-21swapper/112:10:131
13125991311,0cyclictest0-21swapper/110:09:311
1312599130,0cyclictest956-21sshd11:22:071
1312599130,0cyclictest20083-21sshd10:35:391
13124991312,0cyclictest0-21swapper/011:37:340
1312499130,0cyclictest29651-21sshd10:07:330
112750130,0irq/25-eth027178-21bash11:50:351
112750130,0irq/25-eth025817-21sshd11:06:060
112750130,0irq/25-eth011295-21sshd12:12:560
9950120,0irq/24-0000:00:0-21swapper/210:37:152
191120,0ktimersoftd/15170-21diskmemload10:52:021
1312799128,0cyclictest30447-21sshd10:27:283
13127991211,0cyclictest9148-21sshd12:12:353
13127991211,0cyclictest6433-21bash11:22:593
13127991211,0cyclictest25360-21irqstats12:00:143
13127991211,0cyclictest0-21swapper/312:35:493
13127991211,0cyclictest0-21swapper/312:29:543
13127991211,0cyclictest0-21swapper/310:37:273
13127991211,0cyclictest0-21swapper/310:32:203
13127991210,0cyclictest0-21swapper/309:22:383
13127991210,0cyclictest0-21swapper/309:01:013
1312799120,0cyclictest23716-21sshd10:55:553
13126991211,0cyclictest0-21swapper/209:13:512
1312699120,0cyclictest0-21swapper/211:36:232
1312699120,0cyclictest0-21swapper/211:23:222
1312699120,0cyclictest0-21swapper/210:51:542
1312699120,0cyclictest0-21swapper/210:43:592
1312699120,0cyclictest0-21swapper/210:15:122
1312699120,0cyclictest0-21swapper/209:19:332
13125991211,0cyclictest20475-21bash09:41:311
13125991211,0cyclictest0-21swapper/111:35:081
13125991210,0cyclictest4331-21sshd11:17:431
13125991210,0cyclictest0-21swapper/112:08:151
1312599120,0cyclictest0-21swapper/109:35:291
1312599120,0cyclictest0-21swapper/109:23:031
1312499129,0cyclictest0-21swapper/012:16:360
13124991211,0cyclictest0-21swapper/010:16:360
13124991210,0cyclictest25993-21sshd11:01:120
13124991210,0cyclictest0-21swapper/012:38:200
13124991210,0cyclictest0-21swapper/009:11:400
1312499120,0cyclictest8162-21sshd09:54:320
1312499120,0cyclictest0-21swapper/011:45:150
1312499120,0cyclictest0-21swapper/011:33:520
1312499120,0cyclictest0-21swapper/010:49:080
112750120,0irq/25-eth00-21swapper/012:03:560
1312799119,0cyclictest0-21swapper/310:44:043
1312799119,0cyclictest0-21swapper/307:55:373
1312799118,0cyclictest0-21swapper/309:47:233
13127991111,0cyclictest0-21swapper/311:34:013
13127991110,0cyclictest0-21swapper/311:49:073
13127991110,0cyclictest0-21swapper/311:37:443
1312799110,0cyclictest0-21swapper/311:16:373
13126991111,0cyclictest0-21swapper/212:13:262
13126991111,0cyclictest0-21swapper/212:05:332
1312699111,0cyclictest0-21swapper/210:45:582
13126991110,0cyclictest0-21swapper/212:31:002
13126991110,0cyclictest0-21swapper/211:10:222
13126991110,0cyclictest0-21swapper/210:55:502
13125991111,0cyclictest0-21swapper/111:09:081
13125991110,0cyclictest0-21swapper/111:00:451
13125991110,0cyclictest0-21swapper/110:21:011
13125991110,0cyclictest0-21swapper/109:17:221
1312599110,0cyclictest8610-21sshd10:04:241
1312599110,0cyclictest0-21swapper/109:57:401
13124991111,0cyclictest0-21swapper/012:06:580
13124991111,0cyclictest0-21swapper/009:05:170
13124991110,0cyclictest30874-21sshd12:25:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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