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2025-11-22 - 18:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Nov 22, 2025 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050610,0irq/25-eth00-21swapper/107:07:411
110050590,0irq/25-eth00-21swapper/307:05:503
110050570,0irq/25-eth00-21swapper/207:06:422
9950540,0irq/24-0000:00:0-21swapper/007:05:470
191190,0ktimersoftd/10-21swapper/111:30:321
351180,0ktimersoftd/326475-21sshd11:30:323
351180,0ktimersoftd/30-21swapper/311:24:433
271180,0ktimersoftd/24316-21sshd11:24:432
271180,0ktimersoftd/226480-21sshd11:30:322
29413991615,0cyclictest7609-21sshd10:37:553
2941099160,0cyclictest0-21swapper/009:50:500
29411991512,0cyclictest0-21swapper/111:16:341
29411991512,0cyclictest0-21swapper/111:16:341
2941199150,0cyclictest5074-21bash12:15:171
29413991413,0cyclictest0-21swapper/310:42:553
29413991413,0cyclictest0-21swapper/310:42:553
2941299140,0cyclictest0-21swapper/209:58:302
2941099140,0cyclictest0-21swapper/011:54:470
2941099140,0cyclictest0-21swapper/011:08:050
29413991312,0cyclictest20949-21sshd09:59:003
29413991312,0cyclictest0-21swapper/311:06:233
2941399130,0cyclictest21752-21sshd10:25:023
2941399130,0cyclictest0-21swapper/311:45:243
2941399130,0cyclictest0-21swapper/310:59:043
2941399130,0cyclictest0-21swapper/309:13:493
29412991312,0cyclictest0-21swapper/211:13:322
29412991312,0cyclictest0-21swapper/211:07:572
29412991312,0cyclictest0-21swapper/210:24:312
29412991311,0cyclictest0-21swapper/211:46:252
2941299130,0cyclictest17064-21sshd12:33:002
2941299130,0cyclictest0-21swapper/211:51:252
29411991313,0cyclictest0-21swapper/109:30:091
29411991312,0cyclictest0-21swapper/112:30:061
29411991312,0cyclictest0-21swapper/110:51:221
2941199130,0cyclictest0-21swapper/112:37:111
2941099137,0cyclictest3-21ksoftirqd/012:01:150
2941099130,0cyclictest0-21swapper/010:40:230
2941099130,0cyclictest0-21swapper/010:40:220
110050130,0irq/25-eth00-21swapper/012:14:240
41120,0ktimersoftd/021330-21diskmemload09:40:330
41120,0ktimersoftd/00-21swapper/011:20:190
29413991210,0cyclictest0-21swapper/310:31:453
29413991210,0cyclictest0-21swapper/309:53:393
29413991210,0cyclictest0-21swapper/309:25:333
2941399120,0cyclictest21330-21diskmemload12:15:163
2941399120,0cyclictest0-21swapper/312:34:543
2941399120,0cyclictest0-21swapper/311:11:573
29412991212,0cyclictest0-21swapper/212:22:392
29412991211,0cyclictest0-21swapper/212:36:502
29412991211,0cyclictest0-21swapper/211:38:442
29412991211,0cyclictest0-21swapper/210:35:402
29412991210,0cyclictest0-21swapper/210:08:422
2941299120,0cyclictest0-21swapper/212:08:292
2941299120,0cyclictest0-21swapper/210:16:022
2941299120,0cyclictest0-21swapper/208:55:122
29411991211,0cyclictest0-21swapper/112:05:011
29411991211,0cyclictest0-21swapper/110:00:221
29411991210,0cyclictest6854-21sshd12:12:061
29411991210,0cyclictest0-21swapper/108:40:191
2941199120,0cyclictest0-21swapper/111:45:021
2941199120,0cyclictest0-21swapper/109:39:551
2941199120,0cyclictest0-21swapper/109:26:201
29410991212,0cyclictest0-21swapper/011:18:390
29410991212,0cyclictest0-21swapper/011:18:380
29410991212,0cyclictest0-21swapper/010:56:210
29410991212,0cyclictest0-21swapper/010:33:070
29410991212,0cyclictest0-21swapper/009:27:080
29410991211,0cyclictest1451-21nfsd10:14:390
29410991211,0cyclictest0-21swapper/009:56:100
29410991210,0cyclictest0-21swapper/009:36:540
2941099120,0cyclictest0-21swapper/012:37:170
2941099120,0cyclictest0-21swapper/012:26:570
271120,0ktimersoftd/20-21swapper/211:26:402
271120,0ktimersoftd/20-21swapper/209:15:162
110050120,0irq/25-eth06503-21sshd10:12:013
110050120,0irq/25-eth017381-21sshd11:11:211
110050120,0irq/25-eth00-21swapper/011:45:260
41110,0ktimersoftd/013846-21sshd11:25:370
41110,0ktimersoftd/00-21swapper/012:15:540
2941399119,0cyclictest0-21swapper/308:43:303
29413991111,0cyclictest0-21swapper/311:52:093
29413991111,0cyclictest0-21swapper/311:41:003
29413991111,0cyclictest0-21swapper/311:28:413
29413991111,0cyclictest0-21swapper/310:09:493
29413991111,0cyclictest0-21swapper/309:48:193
29413991110,0cyclictest2776-21sshd10:47:553
29413991110,0cyclictest2776-21sshd10:47:543
29413991110,0cyclictest0-21swapper/312:13:383
29413991110,0cyclictest0-21swapper/311:35:253
29413991110,0cyclictest0-21swapper/311:18:073
29413991110,0cyclictest0-21swapper/311:18:073
29413991110,0cyclictest0-21swapper/308:34:543
2941399110,0cyclictest0-21swapper/308:05:383
29412991111,0cyclictest0-21swapper/210:30:052
29412991111,0cyclictest0-21swapper/209:36:332
29412991110,0cyclictest11090-21ntp_states08:45:192
29412991110,0cyclictest0-21swapper/211:56:592
29412991110,0cyclictest0-21swapper/211:19:072
29412991110,0cyclictest0-21swapper/211:19:072
29412991110,0cyclictest0-21swapper/210:40:402
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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