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2025-12-20 - 19:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Dec 20, 2025 12:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750600,0irq/25-eth00-21swapper/207:05:302
120650590,0irq/26-eth1-rx-0-21swapper/107:06:371
112750590,0irq/25-eth00-21swapper/307:05:073
3131025421,0sleep00-21swapper/007:09:350
31414991511,0cyclictest0-21swapper/209:53:352
3141599140,0cyclictest0-21swapper/307:15:213
31412991413,0cyclictest1273-21diskstats11:35:150
3141299140,0cyclictest0-21swapper/011:59:100
31415991312,0cyclictest0-21swapper/309:44:343
31415991311,0cyclictest0-21swapper/309:48:043
3141599130,0cyclictest19047-21sshd09:55:163
3141599130,0cyclictest0-21swapper/312:31:303
3141599130,0cyclictest0-21swapper/310:00:153
31414991312,0cyclictest0-21swapper/212:26:422
31414991312,0cyclictest0-21swapper/212:24:582
31413991313,0cyclictest0-21swapper/109:23:291
31413991312,0cyclictest23322-21diskmemload11:26:301
31413991312,0cyclictest0-21swapper/111:58:261
31412991312,0cyclictest0-21swapper/011:26:590
31412991311,0cyclictest0-21swapper/010:14:030
31412991310,0cyclictest0-21swapper/011:41:590
31415991212,0cyclictest0-21swapper/310:10:293
31415991211,0cyclictest0-21swapper/312:39:593
31415991211,0cyclictest0-21swapper/312:29:463
31415991211,0cyclictest0-21swapper/312:21:173
31415991211,0cyclictest0-21swapper/311:09:583
31415991211,0cyclictest0-21swapper/310:05:153
3141599120,0cyclictest32403-21sshd10:27:403
3141599120,0cyclictest0-21swapper/311:42:013
3141599120,0cyclictest0-21swapper/311:37:023
3141599120,0cyclictest0-21swapper/311:24:003
3141599120,0cyclictest0-21swapper/311:19:153
31414991211,0cyclictest0-21swapper/212:05:132
31414991211,0cyclictest0-21swapper/211:43:292
31414991211,0cyclictest0-21swapper/211:03:252
31414991211,0cyclictest0-21swapper/211:03:252
31414991211,0cyclictest0-21swapper/210:35:392
31414991211,0cyclictest0-21swapper/210:22:592
31414991211,0cyclictest0-21swapper/210:19:292
31414991210,0cyclictest1572-21sshd11:15:442
3141499120,0cyclictest0-21swapper/211:45:142
3141499120,0cyclictest0-21swapper/209:05:302
31413991210,0cyclictest0-21swapper/110:54:181
3141399120,0cyclictest0-21swapper/112:32:561
3141399120,0cyclictest0-21swapper/112:09:281
3141399120,0cyclictest0-21swapper/112:04:431
3141399120,0cyclictest0-21swapper/111:34:441
31412991210,0cyclictest0-21swapper/012:10:130
31412991210,0cyclictest0-21swapper/010:35:250
31412991210,0cyclictest0-21swapper/010:31:410
41110,0ktimersoftd/00-21swapper/008:45:180
351110,0ktimersoftd/30-21swapper/309:21:073
31415991111,0cyclictest0-21swapper/312:13:023
31415991111,0cyclictest0-21swapper/311:02:253
31415991111,0cyclictest0-21swapper/311:02:243
31415991110,0cyclictest0-21swapper/311:45:153
31415991110,0cyclictest0-21swapper/310:31:103
3141599110,0cyclictest0-21swapper/312:00:293
3141599110,0cyclictest0-21swapper/308:55:553
3141599110,0cyclictest0-21swapper/308:39:523
31414991111,0cyclictest0-21swapper/209:58:502
31414991111,0cyclictest0-21swapper/209:37:552
31414991111,0cyclictest0-21swapper/209:21:322
31414991110,0cyclictest23322-21diskmemload09:34:122
31414991110,0cyclictest0-21swapper/211:25:152
31414991110,0cyclictest0-21swapper/210:31:562
3141499110,0cyclictest0-21swapper/212:13:142
3141499110,0cyclictest0-21swapper/212:03:422
3141499110,0cyclictest0-21swapper/209:00:512
3141499110,0cyclictest0-21swapper/208:49:292
3141499110,0cyclictest0-21swapper/208:19:582
3141499110,0cyclictest0-21swapper/207:35:282
31413991111,0cyclictest23322-21diskmemload09:36:081
31413991111,0cyclictest0-21swapper/112:19:141
31413991111,0cyclictest0-21swapper/110:43:021
31413991111,0cyclictest0-21swapper/110:37:211
31413991111,0cyclictest0-21swapper/110:22:571
31413991111,0cyclictest0-21swapper/109:15:481
31413991111,0cyclictest0-21swapper/108:45:021
31413991110,0cyclictest818-21sshd10:46:531
31413991110,0cyclictest0-21swapper/112:29:271
3141399110,0cyclictest0-21swapper/111:21:441
3141399110,0cyclictest0-21swapper/110:06:441
31412991111,0cyclictest0-21swapper/010:27:590
31412991111,0cyclictest0-21swapper/009:16:390
31412991110,0cyclictest15784-21sshd09:26:040
31412991110,0cyclictest0-21swapper/011:53:570
31412991110,0cyclictest0-21swapper/011:30:150
3141299110,0cyclictest23322-21diskmemload12:25:260
3141299110,0cyclictest0-21swapper/011:06:260
3141299110,0cyclictest0-21swapper/009:38:580
112750110,0irq/25-eth023322-21diskmemload12:21:110
112750110,0irq/25-eth00-21swapper/309:52:493
112750110,0irq/25-eth00-21swapper/309:10:533
351100,0ktimersoftd/30-21swapper/310:22:043
3141599109,0cyclictest0-21swapper/308:05:443
31415991010,0cyclictest0-21swapper/312:08:163
31415991010,0cyclictest0-21swapper/311:33:463
31415991010,0cyclictest0-21swapper/310:41:443
31415991010,0cyclictest0-21swapper/310:18:573
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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