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2025-11-23 - 15:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Nov 23, 2025 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950650,0irq/26-eth1-rx-0-21swapper/107:08:381
110050640,0irq/25-eth00-21swapper/307:05:183
110050550,0irq/25-eth00-21swapper/207:05:102
110050490,0irq/25-eth00-21swapper/007:08:370
271180,0ktimersoftd/232151-21sshd11:53:292
271180,0ktimersoftd/215606-21sshd09:55:502
9176991612,0cyclictest0-21swapper/312:08:323
917699160,0cyclictest5715-21hddtemp_smartct10:40:153
917599160,0cyclictest0-21swapper/212:20:132
9174991613,0cyclictest0-21swapper/111:33:221
917599150,0cyclictest0-21swapper/210:25:172
9174991512,0cyclictest0-21swapper/112:21:001
9173991512,0cyclictest19375-21cp10:21:030
110050150,0irq/25-eth00-21swapper/212:31:352
110050150,0irq/25-eth00-21swapper/212:31:342
917499140,0cyclictest16372-21sshd12:15:391
917499140,0cyclictest1080-21diskmemload10:23:541
9173991413,0cyclictest0-21swapper/011:37:220
9173991412,0cyclictest0-21swapper/009:39:350
9173991410,0cyclictest0-21swapper/009:53:100
917399140,0cyclictest0-21swapper/008:20:220
9176991312,0cyclictest31784-21sshd11:07:533
9176991312,0cyclictest0-21swapper/312:11:133
9176991312,0cyclictest0-21swapper/311:51:563
9176991312,0cyclictest0-21swapper/310:45:493
9176991312,0cyclictest0-21swapper/310:08:113
9176991312,0cyclictest0-21swapper/309:59:003
9176991311,0cyclictest0-21swapper/311:15:333
9176991310,0cyclictest0-21swapper/311:22:393
917699130,0cyclictest1080-21diskmemload12:03:113
917699130,0cyclictest0-21swapper/309:39:293
9175991311,0cyclictest13728-21sshd12:35:102
9175991311,0cyclictest0-21swapper/210:33:402
917599130,0cyclictest0-21swapper/211:19:192
9174991312,0cyclictest1080-21diskmemload12:03:351
9174991312,0cyclictest0-21swapper/111:05:011
917499130,0cyclictest27825-21sshd09:35:061
917499130,0cyclictest0-21swapper/112:06:141
9173991311,0cyclictest0-21swapper/012:31:370
9173991311,0cyclictest0-21swapper/012:31:370
9173991310,0cyclictest0-21swapper/010:43:210
917399130,0cyclictest1111-21bash10:15:210
917399130,0cyclictest0-21swapper/011:17:510
917399130,0cyclictest0-21swapper/010:37:470
351130,0ktimersoftd/30-21swapper/310:51:383
110050130,0irq/25-eth013890-21sshd11:34:023
110050130,0irq/25-eth00-21swapper/010:49:170
9176991212,0cyclictest0-21swapper/310:34:403
9176991211,0cyclictest31397-21bash11:04:043
9176991211,0cyclictest0-21swapper/311:36:143
9176991211,0cyclictest0-21swapper/311:29:453
9176991211,0cyclictest0-21swapper/310:16:473
9176991211,0cyclictest0-21swapper/310:02:153
9176991210,0cyclictest0-21swapper/312:30:443
9176991210,0cyclictest0-21swapper/312:30:433
9176991210,0cyclictest0-21swapper/309:32:243
9176991210,0cyclictest0-21swapper/307:25:193
917699120,0cyclictest8783-21sshd10:20:023
917699120,0cyclictest0-21swapper/309:11:303
9175991212,0cyclictest0-21swapper/210:57:282
9175991211,0cyclictest1080-21diskmemload12:14:082
9175991211,0cyclictest0-21swapper/212:01:222
9175991211,0cyclictest0-21swapper/211:38:502
9175991211,0cyclictest0-21swapper/211:01:532
9175991211,0cyclictest0-21swapper/210:09:302
9175991211,0cyclictest0-21swapper/209:23:372
9175991210,0cyclictest20600-21sshd10:17:312
917599120,0cyclictest0-21swapper/211:55:162
917599120,0cyclictest0-21swapper/211:55:162
917599120,0cyclictest0-21swapper/211:47:252
917599120,0cyclictest0-21swapper/210:48:392
917599120,0cyclictest0-21swapper/210:21:562
917599120,0cyclictest0-21swapper/207:30:152
9174991211,0cyclictest20150-21bash10:07:031
9174991211,0cyclictest0-21swapper/112:11:351
9174991211,0cyclictest0-21swapper/111:01:111
9174991211,0cyclictest0-21swapper/110:52:581
9174991210,0cyclictest0-21swapper/108:23:121
917499120,0cyclictest23615-21sshd09:23:161
917499120,0cyclictest0-21swapper/112:28:271
917499120,0cyclictest0-21swapper/110:15:221
917499120,0cyclictest0-21swapper/109:18:091
917499120,0cyclictest0-21swapper/107:18:441
917499120,0cyclictest0-21swapper/107:10:231
9173991211,0cyclictest4467-21bash12:07:550
9173991211,0cyclictest26597-21sshd12:36:230
9173991211,0cyclictest0-21swapper/012:26:520
9173991210,0cyclictest26386-21sshd11:49:130
9173991210,0cyclictest0-21swapper/011:30:520
917399120,0cyclictest31364-21sshd11:00:260
917399120,0cyclictest2674-21sshd11:57:150
917399120,0cyclictest2674-21sshd11:57:140
917399120,0cyclictest0-21swapper/011:54:340
917399120,0cyclictest0-21swapper/010:52:460
917399120,0cyclictest0-21swapper/010:05:570
917399120,0cyclictest0-21swapper/010:00:010
917399120,0cyclictest0-21swapper/009:15:460
110050120,0irq/25-eth06457-21sshd09:21:143
110050120,0irq/25-eth00-21swapper/109:58:351
9950110,0irq/24-0000:00:23875-21sshd12:23:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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