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2026-01-19 - 04:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Mon Jan 19, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750680,0irq/25-eth00-21swapper/119:06:321
112750650,0irq/25-eth00-21swapper/319:05:153
112750600,0irq/25-eth00-21swapper/219:07:152
2580824420,0sleep00-21swapper/019:08:090
26022991716,0cyclictest18950-21head20:00:173
26020991611,0cyclictest0-21swapper/100:08:581
26022991515,0cyclictest0-21swapper/300:20:023
26019991513,0cyclictest0-21swapper/021:19:170
26022991411,0cyclictest0-21swapper/322:24:343
2602299140,0cyclictest0-21swapper/323:17:173
26021991412,0cyclictest16652-21sshd23:12:002
26021991411,0cyclictest0-21swapper/223:40:552
2602099140,0cyclictest0-21swapper/100:39:381
26019991411,0cyclictest0-21swapper/021:31:500
112750140,0irq/25-eth00-21swapper/322:00:093
41130,0ktimersoftd/00-21swapper/022:36:190
26022991312,0cyclictest0-21swapper/323:39:233
26022991312,0cyclictest0-21swapper/321:27:313
26022991311,0cyclictest0-21swapper/322:13:173
2602299130,0cyclictest3557-21sshd22:53:013
26021991312,0cyclictest0-21swapper/223:27:402
26021991312,0cyclictest0-21swapper/221:12:132
26021991311,0cyclictest0-21swapper/222:20:462
2602199130,0cyclictest21040-21bash00:31:062
2602199130,0cyclictest0-21swapper/200:26:412
26020991311,0cyclictest0-21swapper/122:21:101
26020991311,0cyclictest0-21swapper/122:12:061
26020991311,0cyclictest0-21swapper/121:25:231
26020991311,0cyclictest0-21swapper/120:42:451
26019991312,0cyclictest0-21swapper/000:30:230
41120,0ktimersoftd/00-21swapper/022:45:090
26022991212,0cyclictest0-21swapper/321:53:323
26022991211,0cyclictest5955-21bash21:35:223
26022991211,0cyclictest22987-21sshd23:07:323
26022991211,0cyclictest0-21swapper/322:48:373
26022991211,0cyclictest0-21swapper/322:39:463
26022991210,0cyclictest0-21swapper/323:53:403
26022991210,0cyclictest0-21swapper/323:32:593
2602299120,0cyclictest0-21swapper/321:12:183
2602299120,0cyclictest0-21swapper/300:01:333
26021991212,0cyclictest0-21swapper/223:08:052
26021991211,0cyclictest0-21swapper/223:47:052
26021991211,0cyclictest0-21swapper/200:35:312
26021991211,0cyclictest0-21swapper/200:07:182
26021991210,0cyclictest2735-21bash22:58:312
26021991210,0cyclictest0-21swapper/223:16:242
26021991210,0cyclictest0-21swapper/200:22:172
2602199120,0cyclictest21504-21bash00:03:212
2602199120,0cyclictest0-21swapper/223:51:152
2602199120,0cyclictest0-21swapper/222:45:172
2602199120,0cyclictest0-21swapper/221:51:292
26020991211,0cyclictest3881-21bash23:32:151
26020991210,0cyclictest0-21swapper/119:40:501
2602099120,0cyclictest0-21swapper/123:20:591
26019991211,0cyclictest14788-21sshd23:56:280
26019991211,0cyclictest0-21swapper/023:15:140
26019991211,0cyclictest0-21swapper/021:47:250
26019991210,0cyclictest0-21swapper/023:54:300
26019991210,0cyclictest0-21swapper/021:25:330
26019991210,0cyclictest0-21swapper/021:10:070
2601999120,0cyclictest0-21swapper/023:10:490
2601999120,0cyclictest0-21swapper/023:06:230
2601999120,0cyclictest0-21swapper/021:57:370
2601999120,0cyclictest0-21swapper/000:21:330
112750120,0irq/25-eth00-21swapper/023:20:160
41110,0ktimersoftd/00-21swapper/000:27:160
2602299119,0cyclictest0-21swapper/319:36:283
26022991111,0cyclictest0-21swapper/322:15:293
26022991111,0cyclictest0-21swapper/320:45:213
26022991111,0cyclictest0-21swapper/319:25:123
26022991110,0cyclictest9557-21sshd21:47:113
26022991110,0cyclictest5411-21sshd23:04:373
26022991110,0cyclictest31927-21sshd00:10:363
26022991110,0cyclictest29620-21sshd22:07:143
26022991110,0cyclictest22481-21cp00:37:003
26022991110,0cyclictest22203-21sshd23:13:013
26022991110,0cyclictest19515-21sshd21:15:303
26022991110,0cyclictest18172-21sshd23:23:353
26022991110,0cyclictest17858-21sshd22:44:233
26022991110,0cyclictest0-21swapper/323:28:073
26022991110,0cyclictest0-21swapper/321:33:343
2602299110,0cyclictest0-21swapper/323:45:323
2602299110,0cyclictest0-21swapper/320:52:333
2602299110,0cyclictest0-21swapper/319:21:223
26021991111,0cyclictest0-21swapper/221:27:402
26021991111,0cyclictest0-21swapper/220:35:172
26021991110,0cyclictest0-21swapper/220:14:432
26021991110,0cyclictest0-21swapper/200:15:392
2602199110,0cyclictest0-21swapper/220:47:012
2602099119,0cyclictest0-21swapper/122:16:301
2602099119,0cyclictest0-21swapper/120:12:191
2602099118,0cyclictest4255-21sshd21:13:041
2602099118,0cyclictest0-21swapper/122:49:511
26020991110,0cyclictest30740-21sshd22:52:031
26020991110,0cyclictest112750irq/25-eth021:47:011
26020991110,0cyclictest0-21swapper/123:42:481
26020991110,0cyclictest0-21swapper/122:04:461
26020991110,0cyclictest0-21swapper/120:16:231
26020991110,0cyclictest0-21swapper/119:18:041
2602099110,0cyclictest0-21swapper/121:42:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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