You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-23 - 16:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Fri Jan 23, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750650,0irq/25-eth00-21swapper/307:07:343
120650640,0irq/26-eth1-rx-0-21swapper/107:07:341
112750550,0irq/25-eth00-21swapper/207:07:102
2610224928,0sleep00-21swapper/007:08:480
2626399330,0cyclictest120650irq/26-eth1-rx-12:27:340
26266993127,0cyclictest0-21swapper/312:26:273
2626499226,0cyclictest0-21swapper/112:28:301
26263992120,0cyclictest17641-21kworker/0:112:23:170
26265992020,0cyclictest112750irq/25-eth012:27:292
26265991717,0cyclictest112750irq/25-eth012:23:162
2626699160,0cyclictest0-21swapper/312:23:173
26266991514,0cyclictest0-21swapper/312:09:223
26264991515,0cyclictest112750irq/25-eth012:23:171
2626699140,0cyclictest18296-21diskmemload11:15:123
2626699140,0cyclictest0-21swapper/311:45:123
2626599140,0cyclictest0-21swapper/208:35:162
2626599140,0cyclictest0-21swapper/207:40:202
26264991413,0cyclictest18296-21diskmemload10:15:011
26264991411,0cyclictest0-21swapper/109:54:551
2626499140,0cyclictest0-21swapper/108:35:151
2626499140,0cyclictest0-21swapper/108:00:171
26265991311,0cyclictest0-21swapper/209:18:562
2626599130,0cyclictest0-21swapper/211:15:152
2626599130,0cyclictest0-21swapper/209:49:082
2626499130,0cyclictest0-21swapper/111:18:051
2626399130,0cyclictest9078-21sshd12:17:540
2626399130,0cyclictest0-21swapper/010:30:130
271120,0ktimersoftd/20-21swapper/212:09:272
26266991211,0cyclictest11686-21sshd09:53:193
26266991211,0cyclictest0-21swapper/309:45:323
26266991210,0cyclictest0-21swapper/311:57:033
26266991210,0cyclictest0-21swapper/310:34:553
26266991210,0cyclictest0-21swapper/309:56:003
26266991210,0cyclictest0-21swapper/309:10:413
2626699120,0cyclictest0-21swapper/312:03:113
2626699120,0cyclictest0-21swapper/311:35:333
2626699120,0cyclictest0-21swapper/311:24:253
2626699120,0cyclictest0-21swapper/310:17:363
2626699120,0cyclictest0-21swapper/310:04:153
2626699120,0cyclictest0-21swapper/309:43:063
2626699120,0cyclictest0-21swapper/309:31:083
26265991211,0cyclictest26271-21sshd09:11:092
26265991211,0cyclictest0-21swapper/209:59:492
26265991211,0cyclictest0-21swapper/209:36:282
26265991210,0cyclictest0-21swapper/212:33:032
26265991210,0cyclictest0-21swapper/210:31:532
2626599120,0cyclictest0-21swapper/211:38:362
2626599120,0cyclictest0-21swapper/210:50:212
2626599120,0cyclictest0-21swapper/210:09:212
2626599120,0cyclictest0-21swapper/209:31:492
26264991211,0cyclictest0-21swapper/111:46:201
26264991211,0cyclictest0-21swapper/109:49:341
26264991210,0cyclictest0-21swapper/109:44:281
2626499120,0cyclictest18296-21diskmemload09:22:021
2626499120,0cyclictest0-21swapper/111:30:591
2626499120,0cyclictest0-21swapper/110:20:421
2626499120,0cyclictest0-21swapper/110:03:101
2626499120,0cyclictest0-21swapper/108:20:171
26263991211,0cyclictest0-21swapper/009:41:390
26263991211,0cyclictest0-21swapper/009:26:470
2626399120,0cyclictest19578-21sshd10:11:240
2626399120,0cyclictest0-21swapper/010:03:020
2626399120,0cyclictest0-21swapper/009:57:270
191120,0ktimersoftd/10-21swapper/112:36:241
191120,0ktimersoftd/10-21swapper/111:14:021
26266991111,0cyclictest0-21swapper/310:21:193
26266991111,0cyclictest0-21swapper/310:06:413
26266991111,0cyclictest0-21swapper/308:53:363
26265991111,0cyclictest0-21swapper/212:35:152
26265991111,0cyclictest0-21swapper/211:54:282
26265991110,0cyclictest538-21sshd09:29:082
26265991110,0cyclictest0-21swapper/210:29:542
26265991110,0cyclictest0-21swapper/210:16:292
2626599110,0cyclictest0-21swapper/211:40:392
2626599110,0cyclictest0-21swapper/211:25:192
2626599110,0cyclictest0-21swapper/211:05:412
2626599110,0cyclictest0-21swapper/210:35:512
2626599110,0cyclictest0-21swapper/208:22:562
2626599110,0cyclictest0-21swapper/207:23:352
2626499119,0cyclictest0-21swapper/112:19:321
26264991111,0cyclictest0-21swapper/110:40:131
26264991111,0cyclictest0-21swapper/109:32:161
26264991110,0cyclictest18296-21diskmemload11:52:141
26264991110,0cyclictest0-21swapper/110:11:181
26264991110,0cyclictest0-21swapper/109:14:291
2626499110,0cyclictest0-21swapper/112:02:361
2626499110,0cyclictest0-21swapper/110:07:491
2626499110,0cyclictest0-21swapper/107:37:021
2626399119,0cyclictest0-21swapper/010:52:390
2626399116,0cyclictest28430-21kworker/0:011:40:420
26263991111,0cyclictest0-21swapper/012:13:300
26263991111,0cyclictest0-21swapper/011:21:400
26263991111,0cyclictest0-21swapper/010:59:010
26263991111,0cyclictest0-21swapper/009:46:460
26263991111,0cyclictest0-21swapper/009:34:200
26263991110,0cyclictest19105-21sshd10:22:330
26263991110,0cyclictest0-21swapper/011:34:480
26263991110,0cyclictest0-21swapper/011:25:240
26263991110,0cyclictest0-21swapper/010:28:140
2626399110,0cyclictest0-21swapper/011:52:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional