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2026-01-28 - 13:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed Jan 28, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650620,0irq/26-eth1-rx-0-21swapper/319:06:313
120650600,0irq/26-eth1-rx-0-21swapper/119:07:511
112750600,0irq/25-eth00-21swapper/219:05:462
112750440,0irq/25-eth00-21swapper/019:05:300
41190,0ktimersoftd/00-21swapper/023:22:280
351180,0ktimersoftd/326904-21bash21:49:413
351180,0ktimersoftd/326494-21bash23:22:283
2939499180,0cyclictest13473-21expr23:40:103
271180,0ktimersoftd/26258-21sshd22:55:002
271180,0ktimersoftd/226493-21sshd23:22:282
29392991612,0cyclictest0-21swapper/121:10:171
29394991514,0cyclictest0-21swapper/323:35:123
2939299140,0cyclictest0-21swapper/122:46:341
29391991413,0cyclictest0-21swapper/023:02:480
29394991311,0cyclictest0-21swapper/322:22:283
2939499130,0cyclictest0-21swapper/323:29:583
2939499130,0cyclictest0-21swapper/321:41:343
29393991312,0cyclictest7210-21sshd21:17:272
29393991312,0cyclictest0-21swapper/223:50:062
29393991310,0cyclictest19604-21sshd22:17:522
2939399130,0cyclictest2422-21sshd21:40:552
29392991312,0cyclictest21423-21diskmemload21:25:021
29392991312,0cyclictest0-21swapper/121:16:041
2939299130,0cyclictest23919-21sshd23:17:081
2939299130,0cyclictest0-21swapper/123:45:001
2939299130,0cyclictest0-21swapper/100:30:131
29391991312,0cyclictest0-21swapper/021:58:150
29391991311,0cyclictest0-21swapper/022:31:470
112750130,0irq/25-eth021140-21sshd23:26:321
41120,0ktimersoftd/00-21swapper/000:35:020
29394991211,0cyclictest0-21swapper/323:12:463
29394991210,0cyclictest0-21swapper/321:12:333
29394991210,0cyclictest0-21swapper/319:20:193
29394991210,0cyclictest0-21swapper/300:18:593
2939499120,0cyclictest0-21swapper/323:55:193
2939499120,0cyclictest0-21swapper/323:33:263
2939499120,0cyclictest0-21swapper/322:31:463
2939499120,0cyclictest0-21swapper/322:27:073
2939499120,0cyclictest0-21swapper/322:04:353
2939499120,0cyclictest0-21swapper/321:53:323
29393991211,0cyclictest0-21swapper/223:58:492
29393991210,0cyclictest0-21swapper/223:30:422
2939399120,0cyclictest0-21swapper/223:02:492
2939399120,0cyclictest0-21swapper/221:32:262
2939399120,0cyclictest0-21swapper/200:20:252
2939399120,0cyclictest0-21swapper/200:11:142
29392991211,0cyclictest0-21swapper/122:41:071
29392991211,0cyclictest0-21swapper/122:16:291
29392991210,0cyclictest0-21swapper/121:31:031
2939299120,0cyclictest0-21swapper/122:37:191
2939299120,0cyclictest0-21swapper/121:37:071
2939199129,0cyclictest0-21swapper/022:57:070
29391991211,0cyclictest3029-21sshd22:49:400
29391991211,0cyclictest0-21swapper/022:20:030
29391991211,0cyclictest0-21swapper/021:11:240
29391991211,0cyclictest0-21swapper/000:28:050
29391991211,0cyclictest0-21swapper/000:28:040
29391991210,0cyclictest0-21swapper/022:35:170
2939199120,0cyclictest18358-21sshd00:30:030
2939199120,0cyclictest0-21swapper/023:36:090
112750120,0irq/25-eth00-21swapper/300:04:073
112750120,0irq/25-eth00-21swapper/123:37:131
112750120,0irq/25-eth00-21swapper/100:17:181
351110,0ktimersoftd/30-21swapper/319:10:473
2939499119,0cyclictest27165-21sshd21:15:263
2939499119,0cyclictest0-21swapper/300:34:053
29394991111,0cyclictest0-21swapper/322:13:253
29394991111,0cyclictest0-21swapper/300:13:323
29394991110,0cyclictest19415-21sshd22:17:493
29394991110,0cyclictest0-21swapper/322:52:553
29394991110,0cyclictest0-21swapper/322:47:273
29394991110,0cyclictest0-21swapper/321:30:113
29394991110,0cyclictest0-21swapper/300:28:243
29394991110,0cyclictest0-21swapper/300:28:243
29394991110,0cyclictest0-21swapper/300:23:003
2939499110,0cyclictest0-21swapper/323:47:233
2939499110,0cyclictest0-21swapper/323:47:233
2939499110,0cyclictest0-21swapper/323:06:013
2939499110,0cyclictest0-21swapper/320:44:393
2939499110,0cyclictest0-21swapper/320:20:163
2939499110,0cyclictest0-21swapper/319:55:043
2939499110,0cyclictest0-21swapper/319:41:273
2939399119,0cyclictest0-21swapper/219:54:092
29393991111,0cyclictest0-21swapper/223:44:522
29393991111,0cyclictest0-21swapper/223:39:392
29393991111,0cyclictest0-21swapper/223:18:302
29393991111,0cyclictest0-21swapper/223:10:012
29393991111,0cyclictest0-21swapper/222:22:312
29393991111,0cyclictest0-21swapper/221:26:242
29393991110,0cyclictest0-21swapper/223:46:372
29393991110,0cyclictest0-21swapper/223:46:372
29393991110,0cyclictest0-21swapper/200:18:272
2939399110,0cyclictest0-21swapper/222:53:252
2939399110,0cyclictest0-21swapper/200:26:072
2939399110,0cyclictest0-21swapper/200:26:072
29392991110,0cyclictest0-21swapper/123:32:351
29392991110,0cyclictest0-21swapper/119:30:011
29392991110,0cyclictest0-21swapper/100:35:261
2939299110,0cyclictest21423-21diskmemload22:21:071
2939299110,0cyclictest11658-21sshd00:09:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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