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2026-01-14 - 22:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed Jan 14, 2026 12:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650660,0irq/26-eth1-rx-0-21swapper/107:09:101
112750600,0irq/25-eth00-21swapper/307:09:313
112750560,0irq/25-eth00-21swapper/207:05:542
2827624530,0sleep00-21swapper/007:10:000
28346991513,0cyclictest0-21swapper/309:26:153
28345991512,0cyclictest0-21swapper/211:21:042
28344991512,0cyclictest0-21swapper/112:02:201
28346991413,0cyclictest0-21swapper/311:28:563
28346991411,0cyclictest0-21swapper/310:40:353
2834699140,0cyclictest0-21swapper/311:15:333
2834699140,0cyclictest0-21swapper/310:22:073
28345991412,0cyclictest0-21swapper/210:50:172
28345991412,0cyclictest0-21swapper/210:50:172
2834599140,0cyclictest0-21swapper/209:50:072
28344991413,0cyclictest0-21swapper/109:43:101
28343991413,0cyclictest0-21swapper/010:32:500
28343991410,0cyclictest12633-21sshd11:16:380
112750140,0irq/25-eth00-21swapper/311:02:253
351130,0ktimersoftd/30-21swapper/311:06:513
351130,0ktimersoftd/30-21swapper/311:06:503
28346991312,0cyclictest2134-21sshd12:05:023
28346991312,0cyclictest0-21swapper/309:37:593
2834699130,0cyclictest1480-21nfsd12:20:143
2834699130,0cyclictest0-21swapper/311:45:193
2834699130,0cyclictest0-21swapper/310:11:193
2834699130,0cyclictest0-21swapper/309:16:573
28345991312,0cyclictest1539-21sshd11:11:262
28345991312,0cyclictest0-21swapper/211:48:012
28345991312,0cyclictest0-21swapper/209:43:302
2834599130,0cyclictest0-21swapper/212:03:352
28344991312,0cyclictest0-21swapper/112:10:011
2834399130,0cyclictest0-21swapper/012:14:430
112750130,0irq/25-eth00-21swapper/110:36:501
9950120,0irq/24-0000:00:0-21swapper/012:35:460
41120,0ktimersoftd/00-21swapper/011:29:380
28346991211,0cyclictest0-21swapper/312:14:413
28346991211,0cyclictest0-21swapper/311:55:243
28346991211,0cyclictest0-21swapper/311:13:353
2834699120,0cyclictest0-21swapper/311:38:193
2834699120,0cyclictest0-21swapper/309:40:253
28345991211,0cyclictest0-21swapper/211:55:412
28345991210,0cyclictest0-21swapper/210:37:452
28345991210,0cyclictest0-21swapper/209:21:592
2834599120,0cyclictest0-21swapper/211:32:412
2834599120,0cyclictest0-21swapper/211:07:152
2834599120,0cyclictest0-21swapper/211:07:152
28344991211,0cyclictest0-21swapper/110:33:001
28344991211,0cyclictest0-21swapper/109:24:061
28344991211,0cyclictest0-21swapper/109:14:481
28344991210,0cyclictest0-21swapper/111:33:381
28344991210,0cyclictest0-21swapper/111:27:571
28344991210,0cyclictest0-21swapper/110:55:531
2834499120,0cyclictest20561-21sshd09:26:331
2834499120,0cyclictest0-21swapper/111:12:371
2834499120,0cyclictest0-21swapper/109:33:381
28343991212,0cyclictest0-21swapper/012:26:330
28343991211,0cyclictest2792-21sshd09:35:120
28343991211,0cyclictest20366-21diskmemload10:41:120
28343991211,0cyclictest0-21swapper/011:00:080
28343991211,0cyclictest0-21swapper/010:53:450
28343991211,0cyclictest0-21swapper/010:53:450
28343991211,0cyclictest0-21swapper/009:23:140
2834399120,0cyclictest0-21swapper/010:00:110
2834399120,0cyclictest0-21swapper/009:25:420
271120,0ktimersoftd/220366-21diskmemload12:14:022
271120,0ktimersoftd/20-21swapper/212:23:552
112750120,0irq/25-eth024398-21sshd10:12:120
112750120,0irq/25-eth00-21swapper/211:52:272
112750120,0irq/25-eth00-21swapper/209:26:322
112750120,0irq/25-eth00-21swapper/111:00:111
112750120,0irq/25-eth00-21swapper/109:59:191
41110,0ktimersoftd/024943-21sshd11:40:550
2834699119,0cyclictest0-21swapper/308:50:073
28346991111,0cyclictest0-21swapper/311:32:383
28346991111,0cyclictest0-21swapper/310:46:453
28346991111,0cyclictest0-21swapper/309:49:143
2834699110,0cyclictest0-21swapper/312:35:103
2834699110,0cyclictest0-21swapper/311:44:013
2834699110,0cyclictest0-21swapper/311:20:103
2834699110,0cyclictest0-21swapper/309:21:353
2834699110,0cyclictest0-21swapper/308:21:113
28345991111,0cyclictest0-21swapper/210:33:342
28345991110,0cyclictest30163-21sshd10:18:492
28345991110,0cyclictest0-21swapper/212:17:122
2834599110,0cyclictest0-21swapper/211:00:522
2834599110,0cyclictest0-21swapper/210:03:222
2834599110,0cyclictest0-21swapper/208:49:352
2834599110,0cyclictest0-21swapper/207:25:502
28344991111,0cyclictest0-21swapper/110:16:161
28344991111,0cyclictest0-21swapper/108:12:531
28344991110,0cyclictest23884-21sshd10:28:491
28344991110,0cyclictest0-21swapper/111:23:461
28344991110,0cyclictest0-21swapper/109:19:281
2834499110,0cyclictest20366-21diskmemload12:11:581
2834499110,0cyclictest0-21swapper/109:45:211
2834399112,0cyclictest0-21swapper/007:25:160
28343991111,0cyclictest0-21swapper/011:45:330
28343991111,0cyclictest0-21swapper/010:28:380
28343991111,0cyclictest0-21swapper/010:24:280
28343991110,0cyclictest9902-21df_inode11:55:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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