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2026-02-04 - 23:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed Feb 04, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/107:05:261
112750610,0irq/25-eth00-21swapper/307:09:093
112750460,0irq/25-eth00-21swapper/207:07:392
112750440,0irq/25-eth00-21swapper/007:09:360
2771999180,0cyclictest26-21rcuc/209:17:552
2771799180,0cyclictest19736-21diskmemload12:27:340
2772099170,0cyclictest0-21swapper/309:46:193
2772099160,0cyclictest0-21swapper/309:21:503
27720991513,0cyclictest0-21swapper/311:17:533
27720991512,0cyclictest6747-21sshd12:20:363
27719991512,0cyclictest4989-21sshd10:51:542
27718991514,0cyclictest27237-21rm11:54:251
2771899150,0cyclictest0-21swapper/109:34:461
2771799150,0cyclictest0-21swapper/011:49:230
27720991413,0cyclictest0-21swapper/308:05:163
27720991413,0cyclictest0-21swapper/308:05:163
27720991411,0cyclictest9696-21sshd09:52:293
27720991411,0cyclictest0-21swapper/310:09:263
27720991410,0cyclictest3566-21sshd12:34:593
2772099140,0cyclictest0-21swapper/310:33:363
2771899140,0cyclictest0-21swapper/112:15:541
2771799140,0cyclictest0-21swapper/012:22:360
2771799140,0cyclictest0-21swapper/010:05:110
112750140,0irq/25-eth0930-21sshd11:50:180
2772099138,0cyclictest0-21swapper/309:11:093
27720991312,0cyclictest0-21swapper/309:56:403
27720991311,0cyclictest6379-21sshd11:26:283
27720991311,0cyclictest18728-21sshd12:32:203
27720991311,0cyclictest0-21swapper/310:23:303
27720991310,0cyclictest0-21swapper/309:44:073
27720991310,0cyclictest0-21swapper/309:34:013
2772099130,0cyclictest0-21swapper/311:35:043
27719991312,0cyclictest0-21swapper/210:03:562
2771999130,0cyclictest1452-21sshd10:16:432
27718991312,0cyclictest32281-21sshd10:55:591
2771899130,0cyclictest4292-21sshd10:51:481
2771899130,0cyclictest0-21swapper/112:06:231
2771899130,0cyclictest0-21swapper/112:03:551
27717991312,0cyclictest9804-21bash10:37:550
27717991312,0cyclictest0-21swapper/010:42:070
27717991312,0cyclictest0-21swapper/010:11:330
27717991310,0cyclictest0-21swapper/010:25:370
2772099129,0cyclictest0-21swapper/309:29:503
27720991212,0cyclictest0-21swapper/312:13:303
27720991211,0cyclictest21437-21sshd11:09:173
27720991211,0cyclictest0-21swapper/310:00:523
27720991211,0cyclictest0-21swapper/309:19:433
27720991210,0cyclictest0-21swapper/310:48:073
27720991210,0cyclictest0-21swapper/308:02:083
2772099120,0cyclictest0-21swapper/310:17:343
27719991212,0cyclictest0-21swapper/211:39:312
27719991211,0cyclictest24442-21sshd09:30:142
27719991211,0cyclictest0-21swapper/209:13:302
27719991210,0cyclictest0-21swapper/212:21:212
27719991210,0cyclictest0-21swapper/210:45:302
27719991210,0cyclictest0-21swapper/210:06:072
2771999120,0cyclictest0-21swapper/212:39:072
2771999120,0cyclictest0-21swapper/210:41:202
2771999120,0cyclictest0-21swapper/209:51:092
27718991212,0cyclictest112750irq/25-eth009:36:451
27718991212,0cyclictest0-21swapper/112:13:281
27718991212,0cyclictest0-21swapper/111:32:341
27718991211,0cyclictest1539-21sshd10:26:421
27718991211,0cyclictest0-21swapper/111:17:211
27718991211,0cyclictest0-21swapper/111:08:461
27718991211,0cyclictest0-21swapper/109:11:531
27718991210,0cyclictest25955-21sshd09:20:291
27718991210,0cyclictest0-21swapper/111:56:371
2771899120,0cyclictest19736-21diskmemload10:47:361
2771899120,0cyclictest0-21swapper/111:10:571
2771899120,0cyclictest0-21swapper/110:20:461
27717991212,0cyclictest0-21swapper/010:00:450
2771799120,0cyclictest0-21swapper/011:31:430
2771799120,0cyclictest0-21swapper/011:16:290
2771799120,0cyclictest0-21swapper/011:05:420
2771799120,0cyclictest0-21swapper/009:54:220
2771799120,0cyclictest0-21swapper/009:10:200
191120,0ktimersoftd/127302-21bash10:35:311
112750120,0irq/25-eth032286-21sshd11:00:530
112750120,0irq/25-eth028877-21sshd11:59:350
41110,0ktimersoftd/06564-21sshd09:17:420
2772099119,0cyclictest0-21swapper/310:52:193
2772099118,0cyclictest0-21swapper/312:06:123
27720991111,0cyclictest0-21swapper/311:45:513
27720991110,0cyclictest0-21swapper/311:32:513
27720991110,0cyclictest0-21swapper/310:39:473
27720991110,0cyclictest0-21swapper/310:25:293
27720991110,0cyclictest0-21swapper/307:30:323
2772099110,0cyclictest0-21swapper/308:36:313
2772099110,0cyclictest0-21swapper/308:31:243
2772099110,0cyclictest0-21swapper/307:40:243
27719991111,0cyclictest8860-21sshd11:41:442
27719991111,0cyclictest29182-21sshd09:55:192
27719991111,0cyclictest0-21swapper/212:30:532
27719991110,0cyclictest31514-21sshd11:15:292
27719991110,0cyclictest24977-21bash12:18:382
27719991110,0cyclictest0-21swapper/211:57:112
27719991110,0cyclictest0-21swapper/211:46:082
27719991110,0cyclictest0-21swapper/209:36:232
2771999110,0cyclictest0-21swapper/212:06:572
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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