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2025-11-30 - 03:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Nov 30, 2025 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950690,0irq/26-eth1-rx-0-21swapper/119:05:251
110050660,0irq/25-eth00-21swapper/319:06:583
110050550,0irq/25-eth00-21swapper/219:09:062
9950470,0irq/24-0000:00:0-21swapper/019:05:350
31103991611,0cyclictest20564-21sshd22:21:553
31103991513,0cyclictest0-21swapper/321:53:553
31103991512,0cyclictest25480-21bash22:59:473
31103991512,0cyclictest25480-21bash22:59:463
31103991512,0cyclictest0-21swapper/321:35:343
31103991511,0cyclictest14681-21sshd00:12:313
3110299150,0cyclictest0-21swapper/221:55:142
31100991512,0cyclictest0-21swapper/022:08:300
110050150,0irq/25-eth012886-21bash23:01:463
110050150,0irq/25-eth00-21swapper/221:47:572
31103991413,0cyclictest0-21swapper/323:57:173
31103991412,0cyclictest0-21swapper/323:46:433
31103991411,0cyclictest0-21swapper/323:51:213
31103991411,0cyclictest0-21swapper/322:09:223
31103991410,0cyclictest0-21swapper/322:36:063
3110399140,0cyclictest0-21swapper/323:24:253
3110399140,0cyclictest0-21swapper/300:07:373
31102991411,0cyclictest28577-21sshd22:56:432
31102991411,0cyclictest28577-21sshd22:56:422
31100991413,0cyclictest0-21swapper/021:17:450
31100991413,0cyclictest0-21swapper/000:35:280
3110099140,0cyclictest16924-21sshd23:52:430
110050140,0irq/25-eth00-21swapper/222:41:362
3110399139,0cyclictest0-21swapper/322:30:173
31103991311,0cyclictest0-21swapper/300:02:103
31103991310,0cyclictest0-21swapper/300:39:483
3110399130,0cyclictest0-21swapper/323:25:353
3110399130,0cyclictest0-21swapper/319:35:483
31102991312,0cyclictest14644-21sshd21:25:452
31102991312,0cyclictest0-21swapper/223:53:312
31102991312,0cyclictest0-21swapper/223:35:592
31102991312,0cyclictest0-21swapper/223:30:022
31102991312,0cyclictest0-21swapper/222:53:142
31102991312,0cyclictest0-21swapper/222:53:132
31102991312,0cyclictest0-21swapper/220:50:122
31102991311,0cyclictest0-21swapper/223:59:262
31102991311,0cyclictest0-21swapper/222:13:162
3110299130,0cyclictest0-21swapper/221:44:062
3110299130,0cyclictest0-21swapper/219:50:132
3110299130,0cyclictest0-21swapper/219:50:122
3110299130,0cyclictest0-21swapper/200:37:402
31101991312,0cyclictest2412-21bash23:10:511
31101991312,0cyclictest17633-21bash23:52:471
31101991311,0cyclictest0-21swapper/100:03:521
3110199130,0cyclictest23930-21sshd21:20:011
3110199130,0cyclictest23009-21diskmemload22:07:321
3110099139,0cyclictest0-21swapper/023:16:140
31100991312,0cyclictest1453-21nfsd23:28:150
31100991312,0cyclictest0-21swapper/021:45:440
3110099130,0cyclictest0-21swapper/000:16:460
31103991211,0cyclictest6925-21id23:18:083
31103991211,0cyclictest0-21swapper/300:23:263
3110399121,0cyclictest0-21swapper/321:20:203
31103991210,0cyclictest0-21swapper/320:05:253
3110399120,0cyclictest0-21swapper/321:34:243
3110399120,0cyclictest0-21swapper/319:50:163
3110399120,0cyclictest0-21swapper/319:50:153
3110299129,0cyclictest24443-21sshd00:06:362
31102991211,0cyclictest2474-21bash00:04:192
31102991211,0cyclictest23009-21diskmemload22:00:092
31102991211,0cyclictest10529-21sshd21:53:072
31102991211,0cyclictest0-21swapper/223:43:102
31102991211,0cyclictest0-21swapper/223:28:532
31102991211,0cyclictest0-21swapper/219:55:222
31102991211,0cyclictest0-21swapper/200:26:102
3110299120,0cyclictest0-21swapper/221:13:062
3110299120,0cyclictest0-21swapper/200:31:362
31101991212,0cyclictest0-21swapper/123:40:081
31101991211,0cyclictest12966-21sshd21:39:331
31101991211,0cyclictest0-21swapper/121:55:341
31101991211,0cyclictest0-21swapper/121:40:071
31101991211,0cyclictest0-21swapper/100:30:531
31101991210,0cyclictest15649-21sshd23:45:521
31101991210,0cyclictest0-21swapper/123:58:421
31101991210,0cyclictest0-21swapper/122:22:241
31101991210,0cyclictest0-21swapper/121:55:001
3110199120,0cyclictest6460-21sshd00:15:061
3110199120,0cyclictest0-21swapper/122:36:361
3110199120,0cyclictest0-21swapper/119:45:141
3110199120,0cyclictest0-21swapper/119:40:151
31100991212,0cyclictest0-21swapper/023:37:430
31100991212,0cyclictest0-21swapper/021:10:190
31100991211,0cyclictest0-21swapper/023:59:120
31100991211,0cyclictest0-21swapper/021:32:020
31100991211,0cyclictest0-21swapper/020:00:170
31100991211,0cyclictest0-21swapper/000:22:470
3110099120,0cyclictest23009-21diskmemload22:10:040
3110099120,0cyclictest0-21swapper/023:46:190
9950110,0irq/24-0000:00:0-21swapper/123:37:551
41110,0ktimersoftd/032520-21sshd22:23:140
41110,0ktimersoftd/023009-21diskmemload22:25:470
3110399115,0cyclictest798-21bash21:41:403
3110399115,0cyclictest28852-21bash22:01:593
3110399115,0cyclictest18932-21sshd23:39:333
3110399114,0cyclictest25001-21rm22:53:063
3110399114,0cyclictest25001-21rm22:53:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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