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2026-01-25 - 19:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Jan 25, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750610,0irq/25-eth00-21swapper/107:07:071
120650600,0irq/26-eth1-rx-0-21swapper/307:07:493
112750550,0irq/25-eth00-21swapper/207:09:052
112750510,0irq/25-eth041ktimersoftd/007:05:090
2492799180,0cyclictest2375-21sshd11:24:483
24925991615,0cyclictest0-21swapper/109:36:471
24925991613,0cyclictest0-21swapper/111:19:581
2492599160,0cyclictest0-21swapper/112:31:041
2492599160,0cyclictest0-21swapper/110:54:241
2492799150,0cyclictest0-21swapper/309:33:503
24926991513,0cyclictest0-21swapper/211:10:342
2492699150,0cyclictest10257-21sshd09:42:592
2492599150,0cyclictest2986-21sshd11:10:071
2492599150,0cyclictest10996-21sshd10:46:371
24927991413,0cyclictest5025-21sshd09:27:343
24927991413,0cyclictest0-21swapper/311:41:103
24927991411,0cyclictest0-21swapper/309:43:153
2492799140,0cyclictest8699-21sshd10:21:493
2492799140,0cyclictest0-21swapper/309:15:293
24926991413,0cyclictest17231-21sshd10:57:272
24925991411,0cyclictest0-21swapper/109:46:271
2492599140,0cyclictest1539-21sshd12:23:171
2492599140,0cyclictest0-21swapper/111:55:131
2492599140,0cyclictest0-21swapper/110:56:511
2492599140,0cyclictest0-21swapper/110:27:421
2492599140,0cyclictest0-21swapper/109:52:011
2492599140,0cyclictest0-21swapper/109:15:051
24927991312,0cyclictest0-21swapper/312:13:483
2492799130,0cyclictest0-21swapper/311:16:473
24926991312,0cyclictest32329-21cp09:36:292
24926991312,0cyclictest0-21swapper/209:26:512
24926991311,0cyclictest0-21swapper/210:00:112
2492699130,0cyclictest0-21swapper/212:14:212
2492699130,0cyclictest0-21swapper/211:33:152
24925991312,0cyclictest9475-21sshd10:41:321
24925991312,0cyclictest9475-21sshd10:41:311
24925991310,0cyclictest6294-21sshd10:16:321
24925991310,0cyclictest0-21swapper/110:38:501
2492599130,0cyclictest0-21swapper/111:47:521
2492599130,0cyclictest0-21swapper/111:32:101
2492599130,0cyclictest0-21swapper/109:43:191
24924991312,0cyclictest0-21swapper/009:36:270
112750130,0irq/25-eth00-21swapper/310:54:423
41120,0ktimersoftd/020411-21sshd09:54:210
351120,0ktimersoftd/30-21swapper/312:36:273
351120,0ktimersoftd/30-21swapper/309:11:393
24927991212,0cyclictest0-21swapper/312:29:223
24927991212,0cyclictest0-21swapper/312:21:353
24927991211,0cyclictest0-21swapper/310:30:053
24927991211,0cyclictest0-21swapper/310:30:043
2492799120,0cyclictest0-21swapper/311:58:423
2492799120,0cyclictest0-21swapper/310:58:453
2492799120,0cyclictest0-21swapper/309:51:583
2492799120,0cyclictest0-21swapper/309:36:593
24926991212,0cyclictest0-21swapper/210:11:062
24926991211,0cyclictest29461-21sshd12:37:562
24926991211,0cyclictest25912-21id10:39:132
24926991211,0cyclictest0-21swapper/212:01:132
24926991211,0cyclictest0-21swapper/209:46:082
24926991210,0cyclictest0-21swapper/212:22:092
24926991210,0cyclictest0-21swapper/211:48:202
24926991210,0cyclictest0-21swapper/209:51:562
2492699120,0cyclictest10950-21sshd09:33:212
2492599129,0cyclictest1480-21nfsd11:52:081
24925991212,0cyclictest0-21swapper/109:24:161
24925991212,0cyclictest0-21swapper/109:11:561
24925991211,0cyclictest15841-21sshd10:08:171
24925991210,0cyclictest2628-21sshd11:24:501
24925991210,0cyclictest0-21swapper/112:36:101
2492599120,0cyclictest0-21swapper/112:12:491
2492599120,0cyclictest0-21swapper/111:04:381
2492599120,0cyclictest0-21swapper/110:24:281
2492599120,0cyclictest0-21swapper/109:30:321
2492599120,0cyclictest0-21swapper/108:02:221
2492599120,0cyclictest0-21swapper/107:36:501
24924991211,0cyclictest0-21swapper/012:14:060
24924991211,0cyclictest0-21swapper/010:36:310
24924991211,0cyclictest0-21swapper/010:13:590
24924991211,0cyclictest0-21swapper/009:23:410
24924991210,0cyclictest0-21swapper/012:24:340
24924991210,0cyclictest0-21swapper/011:48:190
24924991210,0cyclictest0-21swapper/011:10:330
2492499120,0cyclictest0-21swapper/012:01:120
112750120,0irq/25-eth00-21swapper/311:01:463
112750120,0irq/25-eth00-21swapper/310:41:273
112750120,0irq/25-eth00-21swapper/310:41:273
112750120,0irq/25-eth00-21swapper/211:16:312
112750120,0irq/25-eth00-21swapper/111:25:111
41110,0ktimersoftd/05640-21sshd12:29:260
351110,0ktimersoftd/30-21swapper/311:10:073
24927991111,0cyclictest0-21swapper/312:01:083
24927991111,0cyclictest0-21swapper/311:53:363
24927991111,0cyclictest0-21swapper/309:57:183
24927991111,0cyclictest0-21swapper/309:46:233
24927991111,0cyclictest0-21swapper/307:51:513
24927991110,0cyclictest0-21swapper/312:32:083
24927991110,0cyclictest0-21swapper/310:38:193
2492799110,0cyclictest0-21swapper/309:06:053
2492799110,0cyclictest0-21swapper/308:15:193
24926991111,0cyclictest24584-21sshd11:28:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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