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2025-12-16 - 12:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Tue Dec 16, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/319:05:063
112750660,0irq/25-eth00-21swapper/119:05:131
112750550,0irq/25-eth00-21swapper/219:07:112
2417524824,0sleep00-21swapper/019:07:540
2440899170,0cyclictest0-21swapper/120:30:131
24410991413,0cyclictest0-21swapper/322:10:223
24408991413,0cyclictest0-21swapper/123:32:481
24410991312,0cyclictest0-21swapper/321:44:353
2441099130,0cyclictest0-21swapper/300:14:263
2440999130,0cyclictest0-21swapper/223:11:052
2440899130,0cyclictest0-21swapper/123:52:541
24410991211,0cyclictest0-21swapper/323:17:113
24410991211,0cyclictest0-21swapper/322:50:283
24410991210,0cyclictest0-21swapper/323:25:463
2441099120,0cyclictest0-21swapper/323:47:433
2441099120,0cyclictest0-21swapper/321:26:283
24409991212,0cyclictest0-21swapper/222:47:102
24409991211,0cyclictest17739-21seq21:31:322
24409991211,0cyclictest0-21swapper/200:31:282
24409991210,0cyclictest0-21swapper/223:32:072
24409991210,0cyclictest0-21swapper/219:40:142
2440999120,0cyclictest0-21swapper/223:07:152
2440999120,0cyclictest0-21swapper/200:39:092
24408991212,0cyclictest0-21swapper/123:07:571
24408991211,0cyclictest0-21swapper/121:13:101
24408991211,0cyclictest0-21swapper/120:25:111
24408991210,0cyclictest0-21swapper/123:45:131
24408991210,0cyclictest0-21swapper/119:41:031
2440899120,0cyclictest16354-21diskmemload00:01:291
2440899120,0cyclictest0-21swapper/122:58:311
2440899120,0cyclictest0-21swapper/122:01:011
2440899120,0cyclictest0-21swapper/121:17:001
24407991211,0cyclictest16354-21diskmemload22:56:340
24407991211,0cyclictest0-21swapper/021:51:020
24407991210,0cyclictest0-21swapper/023:55:200
24407991210,0cyclictest0-21swapper/022:03:350
2440799120,0cyclictest0-21swapper/021:23:020
2440799120,0cyclictest0-21swapper/020:55:160
191120,0ktimersoftd/10-21swapper/123:17:211
41110,0ktimersoftd/016496-21if_err_eth100:10:120
2441099119,0cyclictest0-21swapper/319:24:363
24410991111,0cyclictest0-21swapper/323:52:303
24410991111,0cyclictest0-21swapper/323:43:533
24410991111,0cyclictest0-21swapper/323:30:313
24410991111,0cyclictest0-21swapper/321:35:593
24410991111,0cyclictest0-21swapper/320:26:033
24410991111,0cyclictest0-21swapper/320:01:053
24410991111,0cyclictest0-21swapper/319:42:503
24410991111,0cyclictest0-21swapper/300:33:293
24410991110,0cyclictest27195-21sshd23:57:143
2441099110,0cyclictest0-21swapper/323:39:083
2441099110,0cyclictest0-21swapper/323:12:243
2441099110,0cyclictest0-21swapper/322:40:553
2441099110,0cyclictest0-21swapper/322:23:443
2441099110,0cyclictest0-21swapper/321:53:123
2441099110,0cyclictest0-21swapper/321:31:133
2441099110,0cyclictest0-21swapper/320:40:283
2441099110,0cyclictest0-21swapper/319:35:113
2441099110,0cyclictest0-21swapper/300:19:133
2441099110,0cyclictest0-21swapper/300:01:053
24409991111,0cyclictest0-21swapper/223:19:422
24409991111,0cyclictest0-21swapper/222:35:402
24409991111,0cyclictest0-21swapper/222:23:142
24409991110,0cyclictest0-21swapper/223:44:342
24409991110,0cyclictest0-21swapper/221:55:282
2440999110,0cyclictest0-21swapper/223:35:112
2440999110,0cyclictest0-21swapper/223:23:312
2440999110,0cyclictest0-21swapper/222:27:042
2440999110,0cyclictest0-21swapper/221:43:032
2440999110,0cyclictest0-21swapper/221:11:272
2440999110,0cyclictest0-21swapper/219:51:522
24408991111,0cyclictest16354-21diskmemload00:34:571
24408991111,0cyclictest0-21swapper/122:43:051
24408991111,0cyclictest0-21swapper/122:22:031
24408991111,0cyclictest0-21swapper/121:33:151
24408991110,0cyclictest3942-21taskset19:30:271
24408991110,0cyclictest0-21swapper/123:57:391
24408991110,0cyclictest0-21swapper/123:28:571
2440899110,0cyclictest0-21swapper/120:35:451
2440899110,0cyclictest0-21swapper/119:59:171
2440899110,0cyclictest0-21swapper/100:38:461
2440899110,0cyclictest0-21swapper/100:22:301
24407991111,0cyclictest0-21swapper/023:13:510
24407991111,0cyclictest0-21swapper/021:57:460
24407991110,0cyclictest0-21swapper/022:16:070
24407991110,0cyclictest0-21swapper/021:15:150
2440799110,0cyclictest28756-21sshd23:19:410
2440799110,0cyclictest0-21swapper/023:45:410
2440799110,0cyclictest0-21swapper/022:45:590
191110,0ktimersoftd/10-21swapper/122:48:391
191110,0ktimersoftd/10-21swapper/121:22:341
41100,0ktimersoftd/00-21swapper/021:35:570
41100,0ktimersoftd/00-21swapper/020:15:260
351100,0ktimersoftd/30-21swapper/300:27:523
2441099109,0cyclictest0-21swapper/322:19:553
2441099109,0cyclictest0-21swapper/321:13:063
24410991010,0cyclictest0-21swapper/323:02:123
24410991010,0cyclictest0-21swapper/322:45:413
24410991010,0cyclictest0-21swapper/319:57:153
2441099100,0cyclictest0-21swapper/320:57:463
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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