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2026-01-20 - 15:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Tue Jan 20, 2026 12:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650620,0irq/26-eth1-rx-0-21swapper/307:05:163
120650610,0irq/26-eth1-rx-0-21swapper/107:07:351
112750560,0irq/25-eth00-21swapper/207:05:382
3085924622,0sleep00-21swapper/007:09:290
3097999180,0cyclictest4536-21sshd10:07:150
30981991512,0cyclictest0-21swapper/212:35:522
3098199150,0cyclictest0-21swapper/212:15:222
3098199150,0cyclictest0-21swapper/208:45:122
30982991413,0cyclictest0-21swapper/311:14:243
30982991413,0cyclictest0-21swapper/307:15:123
30982991411,0cyclictest0-21swapper/310:01:483
30982991411,0cyclictest0-21swapper/310:01:483
3098299140,0cyclictest0-21swapper/308:35:153
30980991413,0cyclictest22994-21diskmemload09:14:301
3098099141,0cyclictest0-21swapper/109:46:421
3098099140,0cyclictest22994-21diskmemload10:30:181
3098099140,0cyclictest22502-21sshd12:29:201
3098099140,0cyclictest0-21swapper/107:25:231
30979991411,0cyclictest0-21swapper/009:18:560
30982991312,0cyclictest6470-21sshd12:32:013
30982991311,0cyclictest0-21swapper/311:37:103
30982991311,0cyclictest0-21swapper/310:19:553
30982991311,0cyclictest0-21swapper/310:19:553
30982991311,0cyclictest0-21swapper/309:18:283
3098299130,0cyclictest0-21swapper/312:26:393
3098299130,0cyclictest0-21swapper/311:50:593
30981991312,0cyclictest18477-21sshd11:05:142
30981991311,0cyclictest0-21swapper/210:29:552
3098199130,0cyclictest0-21swapper/211:42:452
30980991312,0cyclictest0-21swapper/110:15:101
30980991312,0cyclictest0-21swapper/110:15:101
3098099130,0cyclictest6641-21sshd11:47:381
3098099130,0cyclictest0-21swapper/109:59:291
30979991312,0cyclictest0-21swapper/012:33:580
30979991312,0cyclictest0-21swapper/009:47:170
30982991211,0cyclictest30349-21sshd10:22:493
30982991211,0cyclictest0-21swapper/312:10:183
30982991211,0cyclictest0-21swapper/312:01:553
30982991211,0cyclictest0-21swapper/310:57:403
30982991211,0cyclictest0-21swapper/309:33:203
3098299120,0cyclictest24604-21sshd11:17:183
3098299120,0cyclictest0-21swapper/312:15:123
3098299120,0cyclictest0-21swapper/311:42:453
3098299120,0cyclictest0-21swapper/311:25:473
3098299120,0cyclictest0-21swapper/310:14:073
3098299120,0cyclictest0-21swapper/310:14:073
3098299120,0cyclictest0-21swapper/309:46:073
3098299120,0cyclictest0-21swapper/309:42:593
30981991212,0cyclictest0-21swapper/212:14:012
30981991211,0cyclictest16709-21sshd10:48:172
30981991211,0cyclictest0-21swapper/211:16:372
30981991211,0cyclictest0-21swapper/210:53:512
30981991211,0cyclictest0-21swapper/209:32:462
30981991210,0cyclictest0-21swapper/212:27:362
30981991210,0cyclictest0-21swapper/211:48:212
30981991210,0cyclictest0-21swapper/211:25:202
30981991210,0cyclictest0-21swapper/209:28:562
3098199120,0cyclictest0-21swapper/210:33:042
3098199120,0cyclictest0-21swapper/209:42:532
30980991211,0cyclictest22994-21diskmemload09:29:511
30980991211,0cyclictest22924-21sshd11:50:181
30980991211,0cyclictest0-21swapper/112:32:001
3098099120,0cyclictest0-21swapper/109:40:261
30979991211,0cyclictest22994-21diskmemload10:40:080
30979991211,0cyclictest0-21swapper/012:20:090
30979991211,0cyclictest0-21swapper/012:09:000
30979991211,0cyclictest0-21swapper/011:49:090
30979991211,0cyclictest0-21swapper/011:40:390
30979991211,0cyclictest0-21swapper/010:57:340
30979991211,0cyclictest0-21swapper/009:30:260
30979991210,0cyclictest0-21swapper/010:46:260
30979991210,0cyclictest0-21swapper/009:22:460
3097999120,0cyclictest0-21swapper/011:11:520
3097999120,0cyclictest0-21swapper/011:00:280
3097999120,0cyclictest0-21swapper/009:44:090
271120,0ktimersoftd/25588-21sshd11:58:342
191120,0ktimersoftd/122994-21diskmemload10:14:281
191120,0ktimersoftd/122994-21diskmemload10:14:281
191120,0ktimersoftd/10-21swapper/111:12:331
351110,0ktimersoftd/30-21swapper/310:47:063
351110,0ktimersoftd/30-21swapper/309:26:293
3098299119,0cyclictest0-21swapper/308:15:583
3098299119,0cyclictest0-21swapper/307:46:203
30982991111,0cyclictest0-21swapper/309:39:513
30982991111,0cyclictest0-21swapper/308:25:443
30982991111,0cyclictest0-21swapper/307:37:043
30982991110,0cyclictest9217-21sshd11:48:053
30982991110,0cyclictest29348-21sshd11:23:453
30982991110,0cyclictest0-21swapper/312:07:303
30982991110,0cyclictest0-21swapper/311:56:213
30982991110,0cyclictest0-21swapper/311:03:153
30982991110,0cyclictest0-21swapper/309:22:033
30982991110,0cyclictest0-21swapper/307:32:033
3098299110,0cyclictest0-21swapper/310:40:433
3098299110,0cyclictest0-21swapper/309:55:323
3098299110,0cyclictest0-21swapper/309:06:583
3098299110,0cyclictest0-21swapper/308:54:053
3098299110,0cyclictest0-21swapper/308:49:193
3098299110,0cyclictest0-21swapper/307:52:033
30981991111,0cyclictest0-21swapper/211:39:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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