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2026-02-04 - 11:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed Feb 04, 2026 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650690,0irq/26-eth1-rx-0-21swapper/319:05:183
112750580,0irq/25-eth00-21swapper/119:05:191
120650480,0irq/26-eth1-rx-0-21swapper/219:05:362
120650430,0irq/26-eth1-rx-0-21swapper/019:06:160
1693499211,0cyclictest6821-21sshd23:07:010
1693499211,0cyclictest6821-21sshd23:07:010
41180,0ktimersoftd/08956-21diskmemload23:10:360
351180,0ktimersoftd/32297-21sshd23:06:183
351180,0ktimersoftd/32297-21sshd23:06:183
112750180,0irq/25-eth00-21swapper/021:56:150
1693499160,0cyclictest0-21swapper/021:36:290
1693599150,0cyclictest0-21swapper/122:55:131
16937991413,0cyclictest0-21swapper/323:24:413
16937991413,0cyclictest0-21swapper/322:21:093
16936991413,0cyclictest0-21swapper/221:54:082
16936991413,0cyclictest0-21swapper/200:02:362
1693599140,0cyclictest0-21swapper/122:54:561
112750140,0irq/25-eth00-21swapper/100:05:121
16937991311,0cyclictest0-21swapper/322:08:573
1693799130,0cyclictest0-21swapper/322:55:163
1693799130,0cyclictest0-21swapper/300:30:143
16936991312,0cyclictest0-21swapper/223:52:312
16936991312,0cyclictest0-21swapper/200:17:082
16936991312,0cyclictest0-21swapper/200:10:332
1693699131,0cyclictest0-21swapper/220:20:122
1693699130,0cyclictest0-21swapper/222:14:062
1693599130,0cyclictest0-21swapper/123:28:031
1693599130,0cyclictest0-21swapper/121:58:071
16934991312,0cyclictest0-21swapper/023:23:170
1693499130,0cyclictest9757-21bash22:33:120
112750130,0irq/25-eth00-21swapper/020:55:200
16937991211,0cyclictest0-21swapper/323:47:413
16937991211,0cyclictest0-21swapper/322:54:573
16937991211,0cyclictest0-21swapper/322:04:463
16937991210,0cyclictest0-21swapper/321:52:413
1693799120,0cyclictest0-21swapper/300:38:203
1693799120,0cyclictest0-21swapper/300:18:143
16936991212,0cyclictest0-21swapper/222:02:152
16936991211,0cyclictest8563-21sshd23:12:112
16936991211,0cyclictest27397-21bash22:55:212
16936991211,0cyclictest112750irq/25-eth023:08:492
16936991211,0cyclictest112750irq/25-eth023:08:492
16936991211,0cyclictest10674-21sshd21:15:062
16936991211,0cyclictest0-21swapper/223:15:542
16936991211,0cyclictest0-21swapper/222:40:292
16936991211,0cyclictest0-21swapper/222:35:012
16936991211,0cyclictest0-21swapper/221:56:052
1693699121,0cyclictest0-21swapper/223:55:172
16936991210,0cyclictest9804-21sshd22:47:542
16936991210,0cyclictest0-21swapper/200:35:152
1693699120,0cyclictest0-21swapper/219:55:182
16935991212,0cyclictest29116-21bash22:31:071
16935991212,0cyclictest0-21swapper/122:43:471
16935991212,0cyclictest0-21swapper/121:17:211
16935991212,0cyclictest0-21swapper/100:25:041
16935991211,0cyclictest0-21swapper/123:45:411
16935991211,0cyclictest0-21swapper/123:02:221
16935991211,0cyclictest0-21swapper/122:06:151
16935991210,0cyclictest0-21swapper/121:38:231
1693599120,0cyclictest1539-21sshd23:20:571
1693599120,0cyclictest0-21swapper/122:47:301
1693599120,0cyclictest0-21swapper/121:28:441
16934991212,0cyclictest0-21swapper/023:19:320
16934991211,0cyclictest0-21swapper/021:50:060
16934991211,0cyclictest0-21swapper/021:46:080
16934991210,0cyclictest0-21swapper/023:28:570
16934991210,0cyclictest0-21swapper/020:36:120
1693499120,0cyclictest27975-21sshd23:49:310
1693499120,0cyclictest13288-21sshd22:19:030
1693499120,0cyclictest0-21swapper/023:34:390
1693499120,0cyclictest0-21swapper/022:44:070
1693499120,0cyclictest0-21swapper/022:04:230
1693499120,0cyclictest0-21swapper/000:02:310
1599120,0watchdog/022160-21sshd23:43:420
112750120,0irq/25-eth08-21rcu_preempt23:59:253
112750120,0irq/25-eth00-21swapper/223:45:252
112750120,0irq/25-eth00-21swapper/223:30:262
112750120,0irq/25-eth00-21swapper/222:09:492
41110,0ktimersoftd/09950-21sshd23:36:510
41110,0ktimersoftd/09950-21sshd23:36:510
191110,0ktimersoftd/10-21swapper/123:55:201
16937991111,0cyclictest481-21jbd2/dm-0-821:56:373
16937991111,0cyclictest0-21swapper/323:53:373
16937991111,0cyclictest0-21swapper/323:28:243
16937991111,0cyclictest0-21swapper/323:04:213
16937991111,0cyclictest0-21swapper/322:38:343
16937991111,0cyclictest0-21swapper/300:07:403
16937991110,0cyclictest112750irq/25-eth022:11:443
16937991110,0cyclictest0-21swapper/322:19:243
16937991110,0cyclictest0-21swapper/321:44:473
16937991110,0cyclictest0-21swapper/300:22:393
1693799110,0cyclictest19811-21bash22:49:293
1693799110,0cyclictest10060-21sshd23:41:463
1693799110,0cyclictest0-21swapper/321:33:233
16936991111,0cyclictest0-21swapper/223:29:022
16936991111,0cyclictest0-21swapper/222:51:382
16936991111,0cyclictest0-21swapper/221:26:432
1693699111,0cyclictest0-21swapper/219:40:152
16936991110,0cyclictest0-21swapper/223:01:022
16936991110,0cyclictest0-21swapper/222:33:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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