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2025-07-04 - 02:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Thu Jul 03, 2025 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050660,0irq/25-eth00-21swapper/107:05:161
110050640,0irq/25-eth00-21swapper/307:07:333
110050620,0irq/25-eth00-21swapper/007:05:150
110050570,0irq/25-eth00-21swapper/207:07:082
3523991712,0cyclictest0-21swapper/310:48:053
3523991511,0cyclictest0-21swapper/310:17:313
352399150,0cyclictest0-21swapper/312:35:123
3522991514,0cyclictest0-21swapper/211:19:492
352199150,0cyclictest0-21swapper/109:30:191
3523991411,0cyclictest28175-21sshd10:41:203
3523991411,0cyclictest0-21swapper/310:02:193
3523991411,0cyclictest0-21swapper/309:22:423
352299140,0cyclictest0-21swapper/209:58:092
352299140,0cyclictest0-21swapper/209:40:382
352099140,0cyclictest8176-21cp10:57:480
352099140,0cyclictest0-21swapper/011:11:180
352099140,0cyclictest0-21swapper/010:43:180
3523991312,0cyclictest11870-21bash10:54:423
3523991312,0cyclictest0-21swapper/311:24:203
3523991312,0cyclictest0-21swapper/311:24:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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