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2025-09-18 - 05:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Thu Sep 18, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950680,0irq/26-eth1-rx-0-21swapper/119:07:521
110050610,0irq/25-eth00-21swapper/319:05:463
110050600,0irq/25-eth00-21swapper/019:06:380
110050590,0irq/25-eth00-21swapper/219:05:582
2741299221,0cyclictest20210-21sshd23:48:010
27413991917,0cyclictest21455-21sshd23:41:401
2741499180,0cyclictest0-21swapper/221:30:082
2741399180,0cyclictest0-21swapper/121:23:121
27414991713,0cyclictest357-21bash22:41:282
27413991715,0cyclictest28091-21bash21:49:421
27414991613,0cyclictest0-21swapper/222:09:242
2741499160,0cyclictest0-21swapper/222:26:282
27413991614,0cyclictest9950irq/24-0000:00:22:11:021
27412991611,0cyclictest0-21swapper/000:01:380
27415991514,0cyclictest22735-21sshd23:06:023
2741599150,0cyclictest0-21swapper/321:52:033
27414991514,0cyclictest0-21swapper/222:47:232
27415991413,0cyclictest25377-21sshd21:30:063
27415991411,0cyclictest31265-21sshd22:28:233
27414991413,0cyclictest29012-21sshd22:34:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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