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2025-05-03 - 02:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Fri May 02, 2025 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950600,0irq/26-eth1-rx-0-21swapper/307:05:373
117950580,0irq/26-eth1-rx-0-21swapper/107:07:271
110050550,0irq/25-eth00-21swapper/207:05:092
2386324420,0sleep00-21swapper/007:07:300
24133991918,0cyclictest0-21swapper/109:24:281
24135991716,0cyclictest0-21swapper/311:07:323
24132991716,0cyclictest0-21swapper/012:17:240
110050170,0irq/25-eth00-21swapper/011:50:130
24134991515,0cyclictest0-21swapper/210:29:142
24132991514,0cyclictest8170-21sshd12:30:120
41140,0ktimersoftd/08585-21df09:20:180
41140,0ktimersoftd/027651-21bash12:25:560
24135991413,0cyclictest15867-21diskmemload12:33:513
24135991413,0cyclictest0-21swapper/311:26:563
24135991413,0cyclictest0-21swapper/311:20:043
24135991411,0cyclictest0-21swapper/311:43:523
24135991411,0cyclictest0-21swapper/310:33:263
24134991411,0cyclictest0-21swapper/211:59:302
24134991411,0cyclictest0-21swapper/210:00:022
24132991413,0cyclictest0-21swapper/009:28:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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