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2025-09-10 - 08:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Wed Sep 10, 2025 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950640,0irq/26-eth1-rx-0-21swapper/119:08:551
110050620,0irq/25-eth00-21swapper/319:05:433
117950600,0irq/26-eth1-rx-0-21swapper/219:08:312
110050520,0irq/25-eth00-21swapper/019:05:140
271180,0ktimersoftd/215379-21ls00:00:162
1579099180,0cyclictest28915-21sshd22:01:313
1579099180,0cyclictest11610-21smartctl22:45:163
1579099180,0cyclictest0-21swapper/323:10:283
110050180,0irq/25-eth04125-21sshd00:05:382
15790991612,0cyclictest0-21swapper/300:15:183
1579099150,0cyclictest32060-21sshd22:21:203
1579099150,0cyclictest32060-21sshd22:21:203
15789991514,0cyclictest0-21swapper/223:51:062
15788991512,0cyclictest0-21swapper/123:45:591
15787991512,0cyclictest7700-21diskmemload22:45:080
110050150,0irq/25-eth018096-21sshd23:21:421
15790991413,0cyclictest29562-21sshd21:12:123
15790991412,0cyclictest0-21swapper/321:31:303
15789991411,0cyclictest0-21swapper/223:36:502
15788991412,0cyclictest0-21swapper/122:48:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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