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2025-12-29 - 01:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Sun Dec 28, 2025 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750650,0irq/25-eth00-21swapper/107:05:211
112750640,0irq/25-eth00-21swapper/307:05:153
112750530,0irq/25-eth00-21swapper/207:09:032
2214524520,0sleep00-21swapper/007:08:400
2232699160,0cyclictest0-21swapper/208:10:192
2232699150,0cyclictest0-21swapper/210:35:232
2232699150,0cyclictest0-21swapper/210:34:582
2232499150,0cyclictest0-21swapper/009:05:180
112750150,0irq/25-eth00-21swapper/312:26:163
2232799141,0cyclictest11940-21cp09:57:343
22324991413,0cyclictest0-21swapper/012:15:490
2232499140,0cyclictest14229-21diskmemload11:25:180
2232499140,0cyclictest0-21swapper/010:10:190
22327991312,0cyclictest0-21swapper/311:01:143
2232799130,0cyclictest0-21swapper/310:00:153
22326991312,0cyclictest17734-21sshd12:17:302
22326991312,0cyclictest14229-21diskmemload11:56:282
22326991312,0cyclictest0-21swapper/212:00:112
22326991312,0cyclictest0-21swapper/211:52:592
2232699130,0cyclictest0-21swapper/209:05:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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