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2024-04-26 - 16:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Fri Apr 26, 2024 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050660,0irq/25-eth00-21swapper/107:05:191
117950590,0irq/26-eth1-rx-0-21swapper/207:07:412
110050590,0irq/25-eth00-21swapper/307:07:423
117950500,0irq/26-eth1-rx-0-21swapper/007:09:580
881999202,0cyclictest16435-21sshd10:49:073
881999160,0cyclictest28807-21sshd10:50:303
881999151,0cyclictest0-21swapper/309:10:193
881899150,0cyclictest0-21swapper/209:35:312
8817991514,0cyclictest0-21swapper/112:17:441
881699150,0cyclictest0-21swapper/011:20:370
881699150,0cyclictest0-21swapper/010:12:110
8819991413,0cyclictest8606-21sshd11:56:543
8819991413,0cyclictest0-21swapper/311:33:473
8818991413,0cyclictest9792-21sshd12:10:292
881899140,0cyclictest0-21swapper/211:25:462
881799140,0cyclictest0-21swapper/112:28:061
881799140,0cyclictest0-21swapper/111:17:141
8816991413,0cyclictest0-21swapper/012:27:180
8816991411,0cyclictest0-21swapper/011:34:200
881699140,0cyclictest0-21swapper/012:10:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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