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2025-12-02 - 13:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Tue Dec 02, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050660,0irq/25-eth00-21swapper/119:05:181
117950620,0irq/26-eth1-rx-0-21swapper/319:05:143
117950550,0irq/26-eth1-rx-0-21swapper/219:09:042
117950470,0irq/26-eth1-rx-0-21swapper/019:05:160
1768499180,0cyclictest28233-21id23:49:053
17681991817,0cyclictest3-21ksoftirqd/000:16:070
1768499170,0cyclictest0-21swapper/300:29:103
17682991512,0cyclictest0-21swapper/123:10:501
17684991412,0cyclictest0-21swapper/323:35:513
17684991411,0cyclictest0-21swapper/300:09:053
1768499140,0cyclictest0-21swapper/321:10:183
17683991413,0cyclictest0-21swapper/219:30:232
17683991411,0cyclictest0-21swapper/222:21:302
17683991411,0cyclictest0-21swapper/221:23:392
1768399140,0cyclictest0-21swapper/200:31:152
17682991411,0cyclictest0-21swapper/100:22:171
17681991413,0cyclictest21874-21sshd21:43:220
17681991411,0cyclictest0-21swapper/021:39:520
110050140,0irq/25-eth00-21swapper/323:12:023
17684991312,0cyclictest0-21swapper/323:19:083
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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