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2025-11-11 - 05:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Tue Nov 11, 2025 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950650,0irq/26-eth1-rx-0-21swapper/319:09:583
117950650,0irq/26-eth1-rx-0-21swapper/119:07:231
110050600,0irq/25-eth00-21swapper/219:07:322
9950520,0irq/24-0000:00:0-21swapper/019:05:060
1324199210,0cyclictest10857-21sshd23:51:560
351180,0ktimersoftd/322991-21bash21:31:143
271180,0ktimersoftd/23732-21sshd22:14:172
1324499150,0cyclictest28367-21sshd23:27:443
1324499150,0cyclictest12380-21sshd21:43:043
1324199150,0cyclictest0-21swapper/000:10:230
110050150,0irq/25-eth06627-21sshd22:14:350
13244991413,0cyclictest2395-21sshd21:29:153
13244991413,0cyclictest0-21swapper/322:06:323
13244991411,0cyclictest24669-21bash00:06:253
13243991413,0cyclictest0-21swapper/222:57:482
13243991412,0cyclictest28298-21diskstats23:05:142
13243991411,0cyclictest0-21swapper/223:48:132
13243991411,0cyclictest0-21swapper/222:50:572
13242991413,0cyclictest16989-21sshd23:23:241
13242991413,0cyclictest0-21swapper/121:25:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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