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2025-11-18 - 14:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Tue Nov 18, 2025 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050640,0irq/25-eth00-21swapper/307:05:223
110050610,0irq/25-eth00-21swapper/107:05:241
9950560,0irq/24-0000:00:0-21swapper/007:05:410
110050550,0irq/25-eth00-21swapper/207:09:582
20816991615,0cyclictest0-21swapper/112:14:341
2081599160,0cyclictest0-21swapper/009:14:340
2081799150,0cyclictest32653-21sshd11:28:422
2081799150,0cyclictest0-21swapper/207:10:242
2081699150,0cyclictest0-21swapper/107:10:161
110050150,0irq/25-eth012062-21bash10:01:191
41140,0ktimersoftd/00-21swapper/012:10:470
20818991413,0cyclictest0-21swapper/310:02:003
20818991413,0cyclictest0-21swapper/309:51:113
20818991411,0cyclictest0-21swapper/311:52:143
20818991411,0cyclictest0-21swapper/309:40:173
2081899140,0cyclictest12719-21diskmemload10:35:343
2081799140,0cyclictest0-21swapper/211:34:522
2081699140,0cyclictest9950irq/24-0000:00:10:56:301
20815991413,0cyclictest3060-21munin-run07:40:010
20815991413,0cyclictest19402-21sshd11:23:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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