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2026-03-14 - 05:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Sat Mar 14, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/319:05:143
120650570,0irq/26-eth1-rx-0-21swapper/119:06:521
112750550,0irq/25-eth00-21swapper/219:06:582
120650440,0irq/26-eth1-rx-0-21swapper/019:06:230
1822099160,0cyclictest0-21swapper/300:33:353
1822099160,0cyclictest0-21swapper/300:15:113
1821999160,0cyclictest0-21swapper/200:15:172
18220991514,0cyclictest0-21swapper/300:13:103
1821899150,0cyclictest0-21swapper/121:25:151
1821899150,0cyclictest0-21swapper/119:20:121
18220991413,0cyclictest2337-21sshd21:17:243
18220991413,0cyclictest11903-21bash22:36:163
18220991413,0cyclictest0-21swapper/322:50:123
18220991413,0cyclictest0-21swapper/322:11:383
1822099140,0cyclictest3082-21sshd23:35:463
1822099140,0cyclictest0-21swapper/321:55:303
18219991411,0cyclictest0-21swapper/223:29:182
1821799140,0cyclictest13945-21sshd23:20:010
112750140,0irq/25-eth00-21swapper/200:31:402
18220991312,0cyclictest0-21swapper/322:06:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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