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2026-01-28 - 01:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Tue Jan 27, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650600,0irq/26-eth1-rx-0-21swapper/207:06:562
120650590,0irq/26-eth1-rx-0-21swapper/107:06:101
112750590,0irq/25-eth00-21swapper/307:05:503
120650440,0irq/26-eth1-rx-0-21swapper/007:06:460
7603992019,0cyclictest4498-21id10:03:582
7602991513,0cyclictest32039-21diskmemload10:40:591
7604991413,0cyclictest0-21swapper/311:07:443
760499140,0cyclictest0-21swapper/312:39:033
760399141,0cyclictest10972-21sshd11:47:272
760299141,0cyclictest0-21swapper/110:16:221
7601991413,0cyclictest112750irq/25-eth011:27:280
7601991413,0cyclictest0-21swapper/010:11:580
7601991411,0cyclictest0-21swapper/010:02:270
112750140,0irq/25-eth023178-21sshd09:52:070
7604991313,0cyclictest0-21swapper/310:25:273
7604991312,0cyclictest0-21swapper/311:27:583
7604991312,0cyclictest0-21swapper/310:21:303
7604991312,0cyclictest0-21swapper/310:04:193
7604991312,0cyclictest0-21swapper/309:31:543
7604991312,0cyclictest0-21swapper/309:18:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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