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2026-09-28 - 02:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Mon Sep 28, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/319:05:213
112750630,0irq/25-eth00-21swapper/119:07:251
112750560,0irq/25-eth00-21swapper/219:09:222
120650430,0irq/26-eth1-rx-0-21swapper/019:05:260
58499190,0cyclictest29780-21bash21:48:223
584991811,0cyclictest17903-21bash22:39:503
583991817,0cyclictest0-21swapper/222:47:542
58499170,0cyclictest0-21swapper/323:50:143
583991715,0cyclictest10954-21sshd00:39:462
271170,0ktimersoftd/212299-21sshd21:31:052
584991615,0cyclictest24953-21diskmemload22:14:583
584991613,0cyclictest15711-21sshd23:09:483
584991512,0cyclictest32420-21bash21:10:443
584991511,0cyclictest0-21swapper/300:08:423
583991514,0cyclictest5944-21bash22:38:262
58399150,0cyclictest0-21swapper/221:21:492
58299150,0cyclictest0-21swapper/122:07:381
58199150,0cyclictest0-21swapper/021:35:190
1499150,0migration/030095-21sshd23:34:000
112750150,0irq/25-eth00-21swapper/123:29:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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