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2025-07-19 - 06:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Sat Jul 19, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950650,0irq/26-eth1-rx-0-21swapper/119:05:201
110050610,0irq/25-eth00-21swapper/319:05:403
110050560,0irq/25-eth00-21swapper/219:07:262
2328424522,0sleep00-21swapper/019:07:110
2357799210,0cyclictest32151-21sshd21:35:142
23577991918,0cyclictest0-21swapper/222:41:562
271170,0ktimersoftd/225716-21sshd21:49:272
23575991716,0cyclictest2918-21sshd22:52:460
23577991615,0cyclictest19010-21sshd23:50:422
2357799161,0cyclictest0-21swapper/222:21:282
2357599160,0cyclictest0-21swapper/023:46:470
191160,0ktimersoftd/128083-21sshd23:36:421
191160,0ktimersoftd/128083-21sshd23:36:411
2357899150,0cyclictest0-21swapper/322:55:573
2357799150,0cyclictest0-21swapper/222:07:042
23575991512,0cyclictest0-21swapper/022:44:180
41140,0ktimersoftd/018225-21id21:30:530
271140,0ktimersoftd/21453-21nfsd00:38:492
23578991413,0cyclictest0-21swapper/321:45:133
23578991411,0cyclictest26086-21sshd00:20:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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