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2026-03-29 - 08:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Sun Mar 29, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750630,0irq/25-eth00-21swapper/119:09:371
120650590,0irq/26-eth1-rx-0-21swapper/319:09:443
120650450,0irq/26-eth1-rx-0-21swapper/219:07:462
2421923924,0sleep00-21swapper/019:06:240
24581991615,0cyclictest0-21swapper/300:39:093
2458199160,0cyclictest0-21swapper/320:10:233
24579991615,0cyclictest16093-21sshd21:47:431
2458199150,0cyclictest0-21swapper/300:20:133
24580991514,0cyclictest0-21swapper/223:25:332
24579991514,0cyclictest0-21swapper/121:23:121
24579991514,0cyclictest0-21swapper/100:31:591
2457999150,0cyclictest16728-21munin-run00:30:001
2458199144,0cyclictest0-21swapper/322:25:153
24581991413,0cyclictest27626-21sshd22:31:363
24580991413,0cyclictest0-21swapper/200:33:522
2457999140,0cyclictest0-21swapper/121:10:141
24578991412,0cyclictest0-21swapper/000:14:260
24578991411,0cyclictest25905-21cp00:01:050
24581991312,0cyclictest19667-21sshd22:22:053
24581991312,0cyclictest0-21swapper/321:41:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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