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2026-06-27 - 10:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Sat Jun 27, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750660,0irq/25-eth00-21swapper/319:05:223
112750620,0irq/25-eth00-21swapper/219:09:092
120650610,0irq/26-eth1-rx-0-21swapper/119:07:491
2707124821,0sleep00-21swapper/019:06:480
27392991916,0cyclictest1842-21sshd21:57:592
2739199191,0cyclictest6611-21sshd23:43:171
112750190,0irq/25-eth00-21swapper/123:33:471
27392991614,0cyclictest7062-21bash21:50:482
27392991614,0cyclictest27401-21sshd22:43:382
2739299160,0cyclictest0-21swapper/222:25:122
27391991615,0cyclictest0-21swapper/123:04:461
27390991611,0cyclictest0-21swapper/000:13:420
2739299152,0cyclictest0-21swapper/222:19:372
2739299150,0cyclictest0-21swapper/223:55:112
27391991514,0cyclictest19292-21diskmemload23:17:531
2739199150,0cyclictest1304-21sshd22:21:041
2739199150,0cyclictest0-21swapper/122:25:201
2739199150,0cyclictest0-21swapper/120:00:201
27393991413,0cyclictest0-21swapper/323:11:353
27392991413,0cyclictest0-21swapper/221:39:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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