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2026-08-11 - 17:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Tue Aug 11, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750650,0irq/25-eth00-21swapper/307:09:113
112750640,0irq/25-eth03-21ksoftirqd/007:10:000
112750610,0irq/25-eth00-21swapper/107:05:011
112750560,0irq/25-eth00-21swapper/207:05:162
3267699200,0cyclictest0-21swapper/109:17:181
351180,0ktimersoftd/318489-21sshd12:27:443
3267799160,0cyclictest0-21swapper/211:55:242
32677991514,0cyclictest28-21ksoftirqd/212:27:452
32678991413,0cyclictest0-21swapper/310:14:533
32678991413,0cyclictest0-21swapper/310:14:523
32678991413,0cyclictest0-21swapper/309:25:303
32677991413,0cyclictest0-21swapper/211:12:122
32675991413,0cyclictest0-21swapper/011:41:010
32678991312,0cyclictest24610-21diskmemload10:09:253
32678991312,0cyclictest24610-21diskmemload10:00:493
32678991312,0cyclictest0-21swapper/310:31:003
32678991312,0cyclictest0-21swapper/309:51:593
32678991311,0cyclictest24610-21diskmemload09:19:493
32678991311,0cyclictest0-21swapper/312:30:543
3267899130,0cyclictest10759-21sshd11:24:493
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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