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2025-10-28 - 04:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Tue Oct 28, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950640,0irq/26-eth1-rx-0-21swapper/119:07:421
110050630,0irq/25-eth00-21swapper/319:07:423
117950610,0irq/26-eth1-rx-0-21swapper/019:05:010
117950480,0irq/26-eth1-rx-0-21swapper/219:08:342
351180,0ktimersoftd/319664-21sshd22:33:283
754099170,0cyclictest0-21swapper/123:06:311
110050170,0irq/25-eth04617-21bash22:14:563
7542991615,0cyclictest4013-1kworker/3:2H23:25:063
7540991614,0cyclictest24853-21munin-run23:45:001
7539991615,0cyclictest0-21swapper/021:28:590
7542991514,0cyclictest0-21swapper/322:53:583
7542991514,0cyclictest0-21swapper/322:53:583
7542991413,0cyclictest5081-21id22:28:323
7541991413,0cyclictest0-21swapper/222:57:312
7541991413,0cyclictest0-21swapper/221:34:332
754199140,0cyclictest11838-21sshd22:32:382
7540991413,0cyclictest14439-21bash23:30:201
7540991413,0cyclictest0-21swapper/123:50:461
7540991412,0cyclictest7305-21sshd23:16:021
7539991413,0cyclictest0-21swapper/021:10:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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