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2025-08-30 - 08:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot0.osadl.org (updated Sat Aug 30, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050680,0irq/25-eth00-21swapper/119:05:221
110050580,0irq/25-eth00-21swapper/319:05:353
110050570,0irq/25-eth00-21swapper/219:07:172
117950470,0irq/26-eth1-rx-0-21swapper/019:05:240
488299231,0cyclictest450-21sshd00:12:350
488399213,0cyclictest0-21swapper/123:38:451
4883991917,0cyclictest21939-21sshd21:25:301
4883991917,0cyclictest21939-21sshd21:25:301
271180,0ktimersoftd/229961-21sshd21:39:172
271180,0ktimersoftd/229961-21sshd21:39:172
4884991514,0cyclictest0-21swapper/221:56:072
488399150,0cyclictest0-21swapper/123:13:291
4885991413,0cyclictest0-21swapper/300:27:213
4885991411,0cyclictest0-21swapper/323:12:253
488599140,0cyclictest29231-21diskmemload23:01:373
4884991413,0cyclictest0-21swapper/222:02:242
4884991412,0cyclictest0-21swapper/200:16:342
488499140,0cyclictest0-21swapper/222:28:532
4883991413,0cyclictest11268-21sshd22:06:361
4883991413,0cyclictest0-21swapper/100:00:121
4883991412,0cyclictest11532-21sshd00:17:181
4882991413,0cyclictest0-21swapper/023:13:270
488299140,0cyclictest0-21swapper/022:56:230
110050140,0irq/25-eth00-21swapper/300:19:413
110050140,0irq/25-eth00-21swapper/123:24:121
4885991313,0cyclictest0-21swapper/321:47:153
4884991312,0cyclictest0-21swapper/223:56:002
4884991312,0cyclictest0-21swapper/222:14:142
4884991311,0cyclictest0-21swapper/221:25:072
4884991311,0cyclictest0-21swapper/221:25:062
4884991310,0cyclictest0-21swapper/222:42:142
488499130,0cyclictest25065-21sshd22:46:592
488499130,0cyclictest18034-21id23:05:562
488499130,0cyclictest0-21swapper/222:09:152
488499130,0cyclictest0-21swapper/221:21:572
4883991312,0cyclictest0-21swapper/121:56:501
488299130,0cyclictest29231-21diskmemload21:11:290
488299130,0cyclictest24476-21sshd21:25:470
488299130,0cyclictest24476-21sshd21:25:470
110050130,0irq/25-eth01323-21sshd22:57:463
110050130,0irq/25-eth00-21swapper/122:20:521
110050130,0irq/25-eth00-21swapper/023:44:080
4885991212,0cyclictest0-21swapper/300:13:033
4885991211,0cyclictest25542-21id23:06:443
4885991211,0cyclictest0-21swapper/323:49:223
4885991211,0cyclictest0-21swapper/322:50:493
4885991211,0cyclictest0-21swapper/321:35:123
4885991211,0cyclictest0-21swapper/321:35:113
4885991210,0cyclictest23473-21sshd21:12:393
4885991210,0cyclictest0-21swapper/300:01:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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