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2025-12-30 - 10:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot0.osadl.org (updated Tue Dec 30, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750690,0irq/25-eth00-21swapper/119:05:241
120650670,0irq/26-eth1-rx-0-21swapper/319:05:243
112750570,0irq/25-eth00-21swapper/219:08:422
2423324925,0sleep00-21swapper/019:06:050
2462199160,0cyclictest0-21swapper/223:50:192
2462199160,0cyclictest0-21swapper/223:25:092
2462099160,0cyclictest887-21sshd23:30:211
2462199150,0cyclictest0-21swapper/221:27:312
24622991412,0cyclictest0-21swapper/322:29:333
2462299140,0cyclictest0-21swapper/322:40:173
2462199140,0cyclictest0-21swapper/222:08:242
24622991312,0cyclictest0-21swapper/321:36:353
24622991312,0cyclictest0-21swapper/321:24:303
2462299130,0cyclictest0-21swapper/300:12:213
24621991312,0cyclictest0-21swapper/221:12:182
24621991311,0cyclictest0-21swapper/200:01:332
2462199130,0cyclictest0-21swapper/219:40:122
24620991312,0cyclictest0-21swapper/121:50:071
24620991311,0cyclictest0-21swapper/122:52:441
24619991312,0cyclictest13886-21sshd23:54:170
120650130,0irq/26-eth1-rx-0-21swapper/200:25:082
24622991211,0cyclictest0-21swapper/300:23:113
24622991210,0cyclictest32701-21bash22:02:433
24622991210,0cyclictest23996-21sshd23:57:093
24622991210,0cyclictest0-21swapper/322:05:113
2462299120,0cyclictest112750irq/25-eth000:25:233
2462299120,0cyclictest0-21swapper/323:50:203
2462299120,0cyclictest0-21swapper/323:05:243
2462299120,0cyclictest0-21swapper/321:15:343
24621991211,0cyclictest0-21swapper/223:57:092
24621991211,0cyclictest0-21swapper/222:50:342
24621991211,0cyclictest0-21swapper/222:00:512
24621991210,0cyclictest0-21swapper/222:35:282
24621991210,0cyclictest0-21swapper/200:08:112
2462199120,0cyclictest0-21swapper/222:45:282
2462199120,0cyclictest0-21swapper/222:28:092
2462199120,0cyclictest0-21swapper/221:18:342
2462199120,0cyclictest0-21swapper/200:23:382
24620991211,0cyclictest19326-21sshd22:27:521
24620991211,0cyclictest0-21swapper/123:49:471
24620991211,0cyclictest0-21swapper/121:56:111
24620991211,0cyclictest0-21swapper/100:09:111
24620991210,0cyclictest0-21swapper/100:11:231
2462099120,0cyclictest2948-21sshd23:21:061
2462099120,0cyclictest0-21swapper/123:50:201
2462099120,0cyclictest0-21swapper/122:05:551
2462099120,0cyclictest0-21swapper/121:31:041
24619991212,0cyclictest0-21swapper/021:17:280
24619991212,0cyclictest0-21swapper/000:20:470
24619991211,0cyclictest0-21swapper/021:23:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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