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2026-03-31 - 00:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot0.osadl.org (updated Mon Mar 30, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750630,0irq/25-eth00-21swapper/107:09:011
112750570,0irq/25-eth00-21swapper/307:07:183
120650430,0irq/26-eth1-rx-0-21swapper/207:05:042
120650400,0irq/26-eth1-rx-0-21swapper/007:09:090
1381699191,0cyclictest17222-21expr07:15:133
13815991916,0cyclictest5257-21sshd11:43:392
351180,0ktimersoftd/328765-21sshd11:12:283
1381699150,0cyclictest0-21swapper/311:50:203
13814991512,0cyclictest8634-21sshd11:35:221
13816991413,0cyclictest0-21swapper/309:50:493
1381699140,0cyclictest0-21swapper/309:40:123
13815991413,0cyclictest0-21swapper/210:23:572
1381599140,0cyclictest0-21swapper/211:00:392
13814991413,0cyclictest0-21swapper/111:00:311
13814991413,0cyclictest0-21swapper/110:26:151
13814991411,0cyclictest8442-21sshd09:40:011
13814991411,0cyclictest0-21swapper/112:08:571
1381499140,0cyclictest5015-21sshd11:13:391
112750140,0irq/25-eth09498-21sshd11:01:160
41130,0ktimersoftd/00-21swapper/012:30:170
351130,0ktimersoftd/319056-21sshd10:36:563
13816991312,0cyclictest4419-21rm09:56:233
13816991312,0cyclictest29244-21sshd10:29:513
13816991311,0cyclictest0-21swapper/312:39:083
13816991311,0cyclictest0-21swapper/312:11:363
13816991311,0cyclictest0-21swapper/310:52:443
1381699130,0cyclictest2981-21cp11:09:073
1381699130,0cyclictest2981-21cp11:09:063
1381699130,0cyclictest0-21swapper/312:07:393
1381699130,0cyclictest0-21swapper/308:45:193
1381699130,0cyclictest0-21swapper/307:30:173
13815991312,0cyclictest5715-21diskmemload12:05:222
13815991312,0cyclictest0-21swapper/209:12:222
1381599130,0cyclictest0-21swapper/210:02:132
1381599130,0cyclictest0-21swapper/207:35:212
13814991312,0cyclictest0-21swapper/112:19:171
13814991312,0cyclictest0-21swapper/110:53:191
13814991311,0cyclictest16937-21sshd12:32:041
1381499131,0cyclictest0-21swapper/107:10:161
13813991312,0cyclictest0-21swapper/010:55:290
1381399130,0cyclictest7996-21sshd09:39:590
1381399130,0cyclictest0-21swapper/011:55:480
1381399130,0cyclictest0-21swapper/010:11:560
13816991212,0cyclictest28817-21sshd10:34:013
13816991212,0cyclictest0-21swapper/309:19:483
13816991211,0cyclictest6231-21sshd09:22:423
13816991211,0cyclictest12446-21sshd11:40:143
13816991211,0cyclictest0-21swapper/312:21:563
13816991211,0cyclictest0-21swapper/311:36:173
13816991210,0cyclictest20190-21sshd12:32:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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