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2026-07-14 - 04:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot0.osadl.org (updated Tue Jul 14, 2026 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650680,0irq/26-eth1-rx-0-21swapper/319:05:273
120650670,0irq/26-eth1-rx-0-21swapper/119:05:201
112750480,0irq/25-eth00-21swapper/019:08:560
885524319,0sleep20-21swapper/219:05:262
9443991713,0cyclictest0-21swapper/322:15:443
9443991713,0cyclictest0-21swapper/322:15:433
9440991615,0cyclictest0-21swapper/023:57:530
9443991513,0cyclictest0-21swapper/323:01:083
9443991512,0cyclictest0-21swapper/323:26:553
944399150,0cyclictest0-21swapper/322:37:263
944199151,0cyclictest0-21swapper/122:53:351
9443991410,0cyclictest0-21swapper/323:17:383
944399140,0cyclictest0-21swapper/322:50:133
9441991411,0cyclictest0-21swapper/123:41:411
9440991413,0cyclictest0-21swapper/000:09:510
9443991312,0cyclictest31436-21sshd00:19:063
9443991312,0cyclictest0-21swapper/323:21:223
9443991312,0cyclictest0-21swapper/322:06:113
9443991312,0cyclictest0-21swapper/322:06:113
9443991311,0cyclictest0-21swapper/323:34:223
9443991311,0cyclictest0-21swapper/321:42:303
9443991310,0cyclictest0-21swapper/323:51:413
9443991310,0cyclictest0-21swapper/323:44:283
944399130,0cyclictest0-21swapper/321:55:513
9442991312,0cyclictest0-21swapper/221:57:002
9442991312,0cyclictest0-21swapper/221:47:502
9442991311,0cyclictest0-21swapper/223:43:392
9442991311,0cyclictest0-21swapper/221:30:172
944299130,0cyclictest0-21swapper/222:48:082
944299130,0cyclictest0-21swapper/221:20:042
9441991313,0cyclictest0-21swapper/122:43:291
9441991312,0cyclictest15153-21sshd23:37:581
9441991312,0cyclictest1314-21diskmemload22:09:341
9441991312,0cyclictest1314-21diskmemload22:09:331
9441991312,0cyclictest0-21swapper/123:50:091
9441991312,0cyclictest0-21swapper/123:10:061
9441991312,0cyclictest0-21swapper/122:58:071
9441991312,0cyclictest0-21swapper/121:31:411
9441991312,0cyclictest0-21swapper/121:15:121
9441991312,0cyclictest0-21swapper/100:22:411
9440991313,0cyclictest0-21swapper/000:32:300
9440991312,0cyclictest4207-21grep21:10:150
9440991312,0cyclictest0-21swapper/023:49:380
9440991312,0cyclictest0-21swapper/021:37:110
944399126,0cyclictest4064-21sshd00:36:593
9443991211,0cyclictest0-21swapper/322:41:593
9443991211,0cyclictest0-21swapper/322:31:043
9443991211,0cyclictest0-21swapper/322:23:233
9443991211,0cyclictest0-21swapper/322:23:233
9443991211,0cyclictest0-21swapper/321:31:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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