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2026-02-16 - 18:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Mon Feb 16, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/107:05:131
120650610,0irq/26-eth1-rx-0-21swapper/307:06:333
120650440,0irq/26-eth1-rx-0-21swapper/007:05:250
1850924122,0sleep20-21swapper/207:08:402
1869299221,0cyclictest23949-21sshd11:59:570
1869599190,0cyclictest0-21swapper/310:52:243
1869599180,0cyclictest660-21sed08:45:223
1869599180,0cyclictest5107-21id11:11:373
18695991515,0cyclictest112750irq/25-eth011:06:513
1869499150,0cyclictest0-21swapper/209:40:152
18693991514,0cyclictest0-21swapper/110:05:401
1869399150,0cyclictest0-21swapper/109:40:161
18692991511,0cyclictest0-21swapper/009:15:390
1869299150,0cyclictest0-21swapper/009:40:130
271140,0ktimersoftd/20-21swapper/211:09:062
18695991411,0cyclictest0-21swapper/310:41:593
1869599140,0cyclictest0-21swapper/309:43:483
18694991413,0cyclictest0-21swapper/210:57:152
1869499140,0cyclictest0-21swapper/212:00:182
18692991413,0cyclictest29345-21bash10:25:140
18692991413,0cyclictest0-21swapper/011:20:110
1869299140,0cyclictest22602-21rm12:33:080
18695991313,0cyclictest112750irq/25-eth010:08:253
18695991312,0cyclictest31981-21sshd12:01:073
18695991312,0cyclictest11494-21sshd10:10:523
18695991312,0cyclictest0-21swapper/312:10:023
18694991312,0cyclictest12532-21sshd10:27:592
18694991312,0cyclictest0-21swapper/209:52:402
18693991312,0cyclictest0-21swapper/109:29:451
1869399130,0cyclictest11365-21sshd10:27:451
18692991312,0cyclictest0-21swapper/009:13:410
18692991311,0cyclictest0-21swapper/011:16:420
1869299130,0cyclictest0-21swapper/011:34:210
1869299130,0cyclictest0-21swapper/009:53:240
1869299130,0cyclictest0-21swapper/009:29:420
191120,0ktimersoftd/127341-21sshd09:18:161
191120,0ktimersoftd/10-21swapper/108:20:171
18695991212,0cyclictest0-21swapper/309:57:583
18695991211,0cyclictest27559-21bash09:23:523
18695991211,0cyclictest27559-21bash09:23:523
18695991211,0cyclictest0-21swapper/311:44:573
18695991211,0cyclictest0-21swapper/310:34:473
18695991211,0cyclictest0-21swapper/310:15:233
18695991211,0cyclictest0-21swapper/310:01:263
18695991211,0cyclictest0-21swapper/309:54:293
1869599120,0cyclictest0-21swapper/310:46:563
1869599120,0cyclictest0-21swapper/310:22:353
18694991211,0cyclictest28266-21sshd12:39:502
18694991211,0cyclictest0-21swapper/211:26:252
18694991211,0cyclictest0-21swapper/209:30:572
18694991210,0cyclictest0-21swapper/210:53:322
18694991210,0cyclictest0-21swapper/210:13:492
18694991210,0cyclictest0-21swapper/209:35:072
1869499120,0cyclictest32291-21munin-node11:50:112
1869499120,0cyclictest0-21swapper/211:22:562
18693991212,0cyclictest0-21swapper/111:46:221
18693991211,0cyclictest4555-21sshd12:18:551
18693991211,0cyclictest0-21swapper/112:35:581
18693991211,0cyclictest0-21swapper/112:00:471
18693991211,0cyclictest0-21swapper/110:37:291
18693991210,0cyclictest0-21swapper/111:33:571
18693991210,0cyclictest0-21swapper/110:46:401
1869399120,0cyclictest0-21swapper/111:44:381
1869399120,0cyclictest0-21swapper/110:50:231
1869399120,0cyclictest0-21swapper/110:23:191
1869299122,0cyclictest0-21swapper/009:35:050
18692991211,0cyclictest16968-21sshd11:36:060
18692991211,0cyclictest10720-21diskmemload12:06:530
18692991211,0cyclictest10720-21diskmemload10:23:300
18692991211,0cyclictest10720-21diskmemload10:00:230
18692991211,0cyclictest0-21swapper/010:59:440
18692991211,0cyclictest0-21swapper/009:46:260
18692991210,0cyclictest0-21swapper/012:29:110
18692991210,0cyclictest0-21swapper/008:00:160
1869299120,0cyclictest0-21swapper/010:45:060
1869299120,0cyclictest0-21swapper/010:12:490
1869299120,0cyclictest0-21swapper/009:58:380
112750120,0irq/25-eth022757-21sshd09:23:000
112750120,0irq/25-eth022757-21sshd09:22:590
112750120,0irq/25-eth00-21swapper/109:36:351
112750120,0irq/25-eth00-21swapper/012:18:400
112750120,0irq/25-eth00-21swapper/010:19:290
18695991111,0cyclictest112750irq/25-eth012:28:253
18695991111,0cyclictest0-21swapper/312:38:033
18695991111,0cyclictest0-21swapper/312:15:303
18695991110,0cyclictest7217-21sshd10:27:003
18695991110,0cyclictest2393-21bash11:22:273
18695991110,0cyclictest1539-21sshd11:00:533
1869599110,0cyclictest0-21swapper/307:45:113
1869599110,0cyclictest0-21swapper/307:15:053
18694991111,0cyclictest0-21swapper/211:58:422
18694991111,0cyclictest0-21swapper/211:37:062
18694991111,0cyclictest0-21swapper/210:36:562
18694991111,0cyclictest0-21swapper/207:55:212
18694991110,0cyclictest9657-21sshd11:12:282
18694991110,0cyclictest3520-21bash12:24:212
18694991110,0cyclictest31077-21sshd10:42:232
18694991110,0cyclictest0-21swapper/210:15:332
18694991110,0cyclictest0-21swapper/209:56:092
1869499110,0cyclictest0-21swapper/211:19:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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