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2026-01-31 - 13:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Jan 31, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650650,0irq/26-eth1-rx-0-21swapper/319:08:413
112750610,0irq/25-eth00-21swapper/119:05:131
120650430,0irq/26-eth1-rx-0-21swapper/219:08:002
120650420,0irq/26-eth1-rx-0-21swapper/019:06:270
271180,0ktimersoftd/22189-21bash21:25:112
191180,0ktimersoftd/130021-21diskmemload21:25:111
5576991615,0cyclictest26712-21sshd22:46:562
557699160,0cyclictest0-21swapper/223:05:162
557799150,0cyclictest0-21swapper/322:35:163
557599150,0cyclictest0-21swapper/122:55:581
5574991514,0cyclictest23451-21sshd22:17:010
5574991512,0cyclictest0-21swapper/022:34:120
557499151,0cyclictest0-21swapper/019:55:180
557799140,0cyclictest0-21swapper/300:28:123
557699140,0cyclictest0-21swapper/222:35:142
557599140,0cyclictest0-21swapper/123:03:521
5574991412,0cyclictest18359-21sshd22:06:250
271140,0ktimersoftd/20-21swapper/221:49:182
112750140,0irq/25-eth00-21swapper/321:31:313
5577991312,0cyclictest0-21swapper/323:58:273
5577991312,0cyclictest0-21swapper/322:46:053
5577991312,0cyclictest0-21swapper/322:21:283
557799130,0cyclictest0-21swapper/300:21:343
5576991312,0cyclictest28799-21sshd22:17:522
5576991312,0cyclictest0-21swapper/200:08:362
5576991311,0cyclictest0-21swapper/221:54:032
5576991311,0cyclictest0-21swapper/200:28:132
5576991310,0cyclictest18852-21id21:17:552
557699130,0cyclictest0-21swapper/223:23:102
5575991313,0cyclictest0-21swapper/100:26:281
5575991311,0cyclictest0-21swapper/122:27:381
557599130,0cyclictest0-21swapper/122:48:041
5574991312,0cyclictest0-21swapper/023:26:280
5574991312,0cyclictest0-21swapper/023:10:130
5574991312,0cyclictest0-21swapper/021:11:160
5574991311,0cyclictest30021-21diskmemload00:16:320
191130,0ktimersoftd/10-21swapper/123:12:211
191130,0ktimersoftd/10-21swapper/122:21:491
112750130,0irq/25-eth030021-21diskmemload23:55:181
112750130,0irq/25-eth030021-21diskmemload21:37:320
5577991212,0cyclictest0-21swapper/323:33:293
5577991212,0cyclictest0-21swapper/321:56:083
5577991212,0cyclictest0-21swapper/300:00:263
5577991211,0cyclictest5598-21sshd21:15:503
5577991211,0cyclictest0-21swapper/323:39:103
5577991211,0cyclictest0-21swapper/321:26:023
5577991211,0cyclictest0-21swapper/321:20:563
557799120,0cyclictest0-21swapper/322:34:143
5576991212,0cyclictest0-21swapper/200:17:112
5576991211,0cyclictest7312-21sshd23:33:022
5576991211,0cyclictest4895-21sshd21:20:372
5576991211,0cyclictest28265-21sshd22:03:072
5576991211,0cyclictest15562-21sshd21:12:362
5576991211,0cyclictest0-21swapper/223:18:592
5576991211,0cyclictest0-21swapper/221:44:322
5576991210,0cyclictest15282-21sshd23:04:552
5576991210,0cyclictest0-21swapper/223:42:412
5576991210,0cyclictest0-21swapper/200:30:262
557699120,0cyclictest0-21swapper/223:45:212
557699120,0cyclictest0-21swapper/222:55:032
557699120,0cyclictest0-21swapper/200:10:472
5575991211,0cyclictest24234-21sshd00:39:221
5575991211,0cyclictest0-21swapper/123:33:431
5575991211,0cyclictest0-21swapper/121:41:161
5575991211,0cyclictest0-21swapper/100:13:271
5575991210,0cyclictest0-21swapper/100:02:531
557599120,0cyclictest14139-21sshd22:50:031
557599120,0cyclictest0-21swapper/121:05:571
557599120,0cyclictest0-21swapper/100:30:111
5574991211,0cyclictest30021-21diskmemload21:50:310
5574991211,0cyclictest0-21swapper/022:23:240
5574991210,0cyclictest0-21swapper/023:32:240
557499120,0cyclictest0-21swapper/023:37:100
557499120,0cyclictest0-21swapper/023:18:210
351120,0ktimersoftd/30-21swapper/300:37:083
112750120,0irq/25-eth017365-21sshd23:59:060
112750120,0irq/25-eth00-21swapper/021:16:320
5577991111,0cyclictest0-21swapper/323:46:503
5577991111,0cyclictest0-21swapper/322:42:083
5577991111,0cyclictest0-21swapper/322:00:463
5577991111,0cyclictest0-21swapper/321:44:243
5577991111,0cyclictest0-21swapper/321:05:083
5577991111,0cyclictest0-21swapper/300:12:583
5577991110,0cyclictest9549-21sshd23:23:363
5577991110,0cyclictest21548-21sshd00:19:223
5577991110,0cyclictest0-21swapper/322:50:013
5576991111,0cyclictest0-21swapper/222:07:182
5576991110,0cyclictest19403-21bash23:25:082
5576991110,0cyclictest0-21swapper/222:26:272
5576991110,0cyclictest0-21swapper/221:32:482
557699110,0cyclictest0-21swapper/221:39:542
557699110,0cyclictest0-21swapper/200:23:482
5575991111,0cyclictest0-21swapper/123:54:591
5575991111,0cyclictest0-21swapper/121:50:471
5575991111,0cyclictest0-21swapper/121:36:381
5575991111,0cyclictest0-21swapper/121:11:461
5575991111,0cyclictest0-21swapper/100:22:031
5575991110,0cyclictest0-21swapper/123:23:511
5575991110,0cyclictest0-21swapper/122:14:511
5575991110,0cyclictest0-21swapper/121:48:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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