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2026-02-15 - 08:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Feb 15, 2026 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650600,0irq/26-eth1-rx-0-21swapper/319:06:253
112750590,0irq/25-eth00-21swapper/119:09:061
434024722,0sleep20-21swapper/219:05:012
112750390,0irq/25-eth00-21swapper/019:05:190
674499160,0cyclictest0-21swapper/223:03:282
674499160,0cyclictest0-21swapper/223:03:282
674599150,0cyclictest0-21swapper/322:49:103
674499150,0cyclictest0-21swapper/222:32:422
6742991514,0cyclictest31179-21diskmemload23:40:440
6742991514,0cyclictest29198-21sshd21:24:280
6745991411,0cyclictest17970-21sshd23:09:433
674599140,0cyclictest0-21swapper/321:00:193
6744991412,0cyclictest0-21swapper/221:17:252
674499140,0cyclictest21265-21sshd21:23:132
6743991413,0cyclictest0-21swapper/120:00:131
112750140,0irq/25-eth023236-21sshd22:48:070
674599130,0cyclictest25129-21sshd22:23:223
674599130,0cyclictest0-21swapper/321:26:063
6744991312,0cyclictest0-21swapper/222:17:012
6744991312,0cyclictest0-21swapper/222:13:172
674499130,0cyclictest0-21swapper/200:38:582
674499130,0cyclictest0-21swapper/200:07:422
6743991312,0cyclictest0-21swapper/123:40:421
6743991312,0cyclictest0-21swapper/123:09:521
6743991312,0cyclictest0-21swapper/100:15:131
6743991312,0cyclictest0-21swapper/100:02:261
6743991311,0cyclictest0-21swapper/122:39:151
6743991311,0cyclictest0-21swapper/122:39:151
6743991310,0cyclictest0-21swapper/123:25:441
6742991312,0cyclictest31179-21diskmemload22:52:040
6742991312,0cyclictest31179-21diskmemload00:18:440
6742991312,0cyclictest0-21swapper/023:34:140
6742991312,0cyclictest0-21swapper/023:16:060
6742991312,0cyclictest0-21swapper/022:19:250
6742991312,0cyclictest0-21swapper/020:50:200
674299130,0cyclictest0-21swapper/000:35:280
112750130,0irq/25-eth025724-21sshd22:43:201
112750130,0irq/25-eth00-21swapper/223:22:112
112750130,0irq/25-eth00-21swapper/100:25:191
6745991212,0cyclictest0-21swapper/321:23:123
6745991211,0cyclictest0-21swapper/300:25:353
6745991210,0cyclictest0-21swapper/323:04:173
6745991210,0cyclictest0-21swapper/323:04:163
674599120,0cyclictest0-21swapper/300:19:043
6744991211,0cyclictest26831-21bash22:43:302
6744991211,0cyclictest25867-21bash00:24:042
6744991211,0cyclictest0-21swapper/223:42:302
6744991211,0cyclictest0-21swapper/223:12:402
6744991211,0cyclictest0-21swapper/221:45:252
6744991211,0cyclictest0-21swapper/221:38:052
6744991210,0cyclictest0-21swapper/223:34:292
674499120,0cyclictest0-21swapper/222:00:312
674499120,0cyclictest0-21swapper/221:52:582
674499120,0cyclictest0-21swapper/220:00:172
674499120,0cyclictest0-21swapper/219:40:182
6743991212,0cyclictest0-21swapper/121:29:121
6743991212,0cyclictest0-21swapper/100:33:261
6743991211,0cyclictest0-21swapper/123:37:281
6743991211,0cyclictest0-21swapper/122:34:501
6743991211,0cyclictest0-21swapper/122:09:171
6743991210,0cyclictest31179-21diskmemload21:10:021
6743991210,0cyclictest0-21swapper/123:48:581
674399120,0cyclictest31179-21diskmemload21:18:311
674399120,0cyclictest12219-21sshd21:31:381
674399120,0cyclictest0-21swapper/123:16:181
674399120,0cyclictest0-21swapper/120:40:181
674399120,0cyclictest0-21swapper/119:47:541
674399120,0cyclictest0-21swapper/100:21:431
6742991211,0cyclictest17432-21sshd21:47:230
6742991211,0cyclictest0-21swapper/023:21:480
6742991211,0cyclictest0-21swapper/000:10:430
6742991210,0cyclictest0-21swapper/022:25:490
6742991210,0cyclictest0-21swapper/021:57:210
6742991210,0cyclictest0-21swapper/021:30:170
6742991210,0cyclictest0-21swapper/021:19:360
674299120,0cyclictest0-21swapper/022:59:310
674299120,0cyclictest0-21swapper/022:10:510
674299120,0cyclictest0-21swapper/000:00:580
271120,0ktimersoftd/20-21swapper/200:26:332
271120,0ktimersoftd/20-21swapper/200:00:312
1799120,0migration/123234-21proc_pri23:55:201
112750120,0irq/25-eth00-21swapper/122:28:341
112750120,0irq/25-eth00-21swapper/121:39:321
6745991111,0cyclictest0-21swapper/323:46:203
6745991111,0cyclictest0-21swapper/322:10:363
6745991110,0cyclictest6323-21bash21:35:363
6745991110,0cyclictest32455-21sshd00:36:193
6745991110,0cyclictest2781-21pmu-power21:15:193
6745991110,0cyclictest23083-21bash00:06:323
6745991110,0cyclictest12676-21bash23:25:233
6745991110,0cyclictest0-21swapper/323:56:193
6745991110,0cyclictest0-21swapper/321:45:093
6745991110,0cyclictest0-21swapper/321:33:123
6745991110,0cyclictest0-21swapper/320:30:003
6745991110,0cyclictest0-21swapper/300:30:353
6745991110,0cyclictest0-21swapper/300:04:483
674599110,0cyclictest0-21swapper/323:15:153
674599110,0cyclictest0-21swapper/321:57:353
674599110,0cyclictest0-21swapper/300:14:193
6744991111,0cyclictest0-21swapper/223:55:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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