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2026-06-24 - 05:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed Jun 24, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650640,0irq/26-eth1-rx-0-21swapper/319:05:223
112750620,0irq/25-eth00-21swapper/119:05:211
120650520,0irq/26-eth1-rx-0-21swapper/219:05:392
120650450,0irq/26-eth1-rx-0-21swapper/019:09:250
11996991717,0cyclictest0-21swapper/022:30:120
1199999150,0cyclictest0-21swapper/319:25:203
11998991514,0cyclictest4644-21sshd22:56:282
11997991514,0cyclictest4419-21sshd23:43:391
1199799150,0cyclictest0-21swapper/100:00:201
1199899140,0cyclictest0-21swapper/200:20:182
11997991413,0cyclictest0-21swapper/100:32:331
1199699140,0cyclictest1614-21id22:51:480
1199699140,0cyclictest0-21swapper/023:38:580
1199699140,0cyclictest0-21swapper/023:38:580
1199699140,0cyclictest0-21swapper/023:27:080
112750140,0irq/25-eth00-21swapper/322:27:253
11999991312,0cyclictest23587-21sshd23:37:363
11999991312,0cyclictest23587-21sshd23:37:353
11999991312,0cyclictest0-21swapper/322:34:103
11999991311,0cyclictest0-21swapper/323:08:113
1199999130,0cyclictest0-21swapper/323:20:223
1199999130,0cyclictest0-21swapper/321:30:183
11998991312,0cyclictest31582-21sshd23:30:092
11998991312,0cyclictest0-21swapper/223:24:142
1199899130,0cyclictest0-21swapper/221:25:152
11997991312,0cyclictest0-21swapper/123:38:341
11997991312,0cyclictest0-21swapper/123:38:331
11997991312,0cyclictest0-21swapper/121:25:181
1199799130,0cyclictest0-21swapper/123:31:481
1199799130,0cyclictest0-21swapper/123:20:121
1199799130,0cyclictest0-21swapper/123:04:031
1199799130,0cyclictest0-21swapper/100:13:311
11996991312,0cyclictest4404-21sshd21:26:530
11996991312,0cyclictest0-21swapper/023:33:510
11996991310,0cyclictest0-21swapper/000:08:490
1199699130,0cyclictest22761-21sshd00:20:200
1199699130,0cyclictest112750irq/25-eth000:35:130
1199699130,0cyclictest0-21swapper/023:48:230
1199699130,0cyclictest0-21swapper/022:29:230
1199699130,0cyclictest0-21swapper/022:08:490
1199699130,0cyclictest0-21swapper/021:43:230
271120,0ktimersoftd/223844-21sshd23:16:062
11999991212,0cyclictest112750irq/25-eth000:06:243
11999991211,0cyclictest0-21swapper/323:43:313
11999991210,0cyclictest0-21swapper/300:30:343
1199999120,0cyclictest0-21swapper/321:39:263
1199999120,0cyclictest0-21swapper/321:25:143
11998991211,0cyclictest26283-21sshd22:46:292
11998991211,0cyclictest0-21swapper/223:27:222
11998991211,0cyclictest0-21swapper/220:00:282
11998991210,0cyclictest0-21swapper/221:33:112
1199899120,0cyclictest12745-21sshd23:36:062
1199899120,0cyclictest12745-21sshd23:36:052
1199899120,0cyclictest0-21swapper/223:40:232
1199899120,0cyclictest0-21swapper/223:04:012
1199899120,0cyclictest0-21swapper/222:20:482
11997991211,0cyclictest19472-21sshd21:45:521
1199799120,0cyclictest6026-21sshd21:44:141
1199799120,0cyclictest0-21swapper/123:25:051
1199799120,0cyclictest0-21swapper/123:18:201
1199799120,0cyclictest0-21swapper/122:43:151
1199799120,0cyclictest0-21swapper/122:30:491
11996991211,0cyclictest0-21swapper/000:16:360
11996991210,0cyclictest26104-21sshd00:03:430
11996991210,0cyclictest0-21swapper/023:44:050
11996991210,0cyclictest0-21swapper/022:42:380
11996991210,0cyclictest0-21swapper/000:27:040
11996991210,0cyclictest0-21swapper/000:13:080
1199699120,0cyclictest3949-21diskmemload22:12:050
1199699120,0cyclictest0-21swapper/021:17:080
112750120,0irq/25-eth00-21swapper/123:45:321
41110,0ktimersoftd/00-21swapper/023:15:440
11999991111,0cyclictest0-21swapper/300:19:173
11999991110,0cyclictest15456-21sshd23:49:253
11999991110,0cyclictest0-21swapper/323:16:333
11999991110,0cyclictest0-21swapper/321:40:143
1199999110,0cyclictest383-21sshd22:47:243
11998991111,0cyclictest0-21swapper/223:10:462
11998991111,0cyclictest0-21swapper/221:46:252
11998991110,0cyclictest0-21swapper/219:36:392
11998991110,0cyclictest0-21swapper/200:01:382
1199899110,0cyclictest8751-21sshd23:09:572
1199899110,0cyclictest0-21swapper/223:45:292
1199899110,0cyclictest0-21swapper/221:00:462
1199899110,0cyclictest0-21swapper/220:40:202
11997991111,0cyclictest0-21swapper/120:40:201
11997991110,0cyclictest3949-21diskmemload21:17:101
11997991110,0cyclictest20511-21sshd21:20:261
1199799110,0cyclictest0-21swapper/121:11:121
1199699116,0cyclictest0-21swapper/020:46:000
11996991111,0cyclictest0-21swapper/023:21:120
11996991111,0cyclictest0-21swapper/023:14:270
11996991111,0cyclictest0-21swapper/020:55:450
11996991111,0cyclictest0-21swapper/020:51:420
11996991110,0cyclictest1714-21sshd00:34:500
11996991110,0cyclictest0-21swapper/023:58:360
11996991110,0cyclictest0-21swapper/023:02:370
11996991110,0cyclictest0-21swapper/021:12:360
1199699110,0cyclictest25946-21sshd21:21:110
1199699110,0cyclictest0-21swapper/020:15:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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