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2026-04-17 - 19:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Fri Apr 17, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650640,0irq/26-eth1-rx-0-21swapper/307:05:593
112750630,0irq/25-eth00-21swapper/107:07:461
112750550,0irq/25-eth00-21swapper/207:05:392
1438624421,0sleep00-21swapper/007:06:540
1470699160,0cyclictest0-21swapper/211:53:052
1470899153,0cyclictest36-21ksoftirqd/310:28:533
14706991512,0cyclictest0-21swapper/212:12:082
1470699150,0cyclictest0-21swapper/210:10:132
14704991511,0cyclictest0-21swapper/012:14:260
1470499150,0cyclictest0-21swapper/008:05:220
14708991413,0cyclictest0-21swapper/311:52:453
14708991413,0cyclictest0-21swapper/310:13:263
14708991412,0cyclictest0-21swapper/310:46:253
1470699140,0cyclictest0-21swapper/211:57:512
1470699140,0cyclictest0-21swapper/211:15:122
1470699140,0cyclictest0-21swapper/208:05:132
14705991413,0cyclictest6644-21diskmemload12:08:131
14705991413,0cyclictest0-21swapper/110:07:101
1470599140,0cyclictest6644-21diskmemload11:21:381
14704991413,0cyclictest0-21swapper/009:50:450
112750140,0irq/25-eth00-21swapper/312:04:573
14708991313,0cyclictest0-21swapper/310:04:583
14708991312,0cyclictest0-21swapper/312:28:543
14708991312,0cyclictest0-21swapper/311:12:263
14708991312,0cyclictest0-21swapper/310:56:113
14708991312,0cyclictest0-21swapper/309:26:243
14706991312,0cyclictest18227-21sshd11:46:352
14706991312,0cyclictest17808-21bash12:16:542
14706991312,0cyclictest0-21swapper/210:02:232
14706991311,0cyclictest0-21swapper/210:23:032
14705991312,0cyclictest0-21swapper/112:39:481
14705991312,0cyclictest0-21swapper/111:49:101
14705991312,0cyclictest0-21swapper/111:16:381
14705991312,0cyclictest0-21swapper/109:37:181
1470599130,0cyclictest0-21swapper/108:25:201
14704991312,0cyclictest0-21swapper/010:51:370
14704991311,0cyclictest0-21swapper/012:30:140
112750130,0irq/25-eth023192-21sshd10:16:332
112750130,0irq/25-eth00-21swapper/309:37:113
14708991212,0cyclictest36-21ksoftirqd/312:39:553
14708991211,0cyclictest28561-21sshd11:09:123
14708991211,0cyclictest12507-21sshd11:02:423
14708991211,0cyclictest11218-21sshd10:23:393
14708991211,0cyclictest0-21swapper/311:59:023
14708991210,0cyclictest0-21swapper/312:33:393
14708991210,0cyclictest0-21swapper/310:52:563
1470899120,0cyclictest0-21swapper/311:41:433
1470899120,0cyclictest0-21swapper/311:25:283
1470899120,0cyclictest0-21swapper/311:22:123
1470899120,0cyclictest0-21swapper/311:18:573
1470899120,0cyclictest0-21swapper/309:24:383
14706991211,0cyclictest6136-21sshd12:32:422
14706991211,0cyclictest29618-21bash10:34:482
14706991211,0cyclictest0-21swapper/212:23:102
14706991211,0cyclictest0-21swapper/209:55:382
14706991210,0cyclictest0-21swapper/210:05:512
1470699120,0cyclictest0-21swapper/212:02:372
1470699120,0cyclictest0-21swapper/209:53:542
1470699120,0cyclictest0-21swapper/209:14:102
14705991211,0cyclictest0-21swapper/112:03:271
14705991211,0cyclictest0-21swapper/110:48:521
14705991211,0cyclictest0-21swapper/110:20:521
1470599120,0cyclictest0-21swapper/112:28:461
1470599120,0cyclictest0-21swapper/112:24:011
1470599120,0cyclictest0-21swapper/112:12:581
1470599120,0cyclictest0-21swapper/110:26:061
1470599120,0cyclictest0-21swapper/109:46:151
14704991212,0cyclictest0-21swapper/011:35:520
14704991211,0cyclictest6644-21diskmemload11:03:060
14704991211,0cyclictest2141-21sshd11:48:530
14704991211,0cyclictest0-21swapper/012:25:280
14704991211,0cyclictest0-21swapper/009:59:090
14704991211,0cyclictest0-21swapper/009:23:550
14704991210,0cyclictest0-21swapper/011:21:070
14704991210,0cyclictest0-21swapper/010:35:200
14704991210,0cyclictest0-21swapper/009:48:590
1470499120,0cyclictest0-21swapper/012:23:580
1470499120,0cyclictest0-21swapper/011:40:520
1470499120,0cyclictest0-21swapper/011:32:370
1470499120,0cyclictest0-21swapper/010:20:080
112750120,0irq/25-eth08367-21sshd09:31:280
112750120,0irq/25-eth00-21swapper/110:30:521
112750120,0irq/25-eth00-21swapper/007:15:000
41110,0ktimersoftd/00-21swapper/012:39:530
14708991111,0cyclictest351ktimersoftd/309:53:003
14708991111,0cyclictest0-21swapper/312:05:183
14708991111,0cyclictest0-21swapper/308:50:153
14708991111,0cyclictest0-21swapper/308:15:173
14708991110,0cyclictest342-21df10:35:103
14708991110,0cyclictest25176-21fschecks_time11:30:133
14708991110,0cyclictest0-21swapper/310:09:043
14708991110,0cyclictest0-21swapper/309:56:283
14706991111,0cyclictest0-21swapper/212:27:562
14706991111,0cyclictest0-21swapper/207:31:562
14706991110,0cyclictest14830-21sshd11:41:492
14706991110,0cyclictest0-21swapper/211:25:192
14706991110,0cyclictest0-21swapper/211:02:562
14706991110,0cyclictest0-21swapper/210:52:342
14706991110,0cyclictest0-21swapper/209:41:152
14706991110,0cyclictest0-21swapper/209:41:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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