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2026-07-10 - 04:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Fri Jul 10, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650610,0irq/26-eth1-rx-0-21swapper/119:06:331
120650600,0irq/26-eth1-rx-0-21swapper/319:06:213
120650460,0irq/26-eth1-rx-0-21swapper/219:07:502
112750410,0irq/25-eth00-21swapper/019:08:460
351180,0ktimersoftd/31829-21sshd00:34:333
271180,0ktimersoftd/215741-21sshd23:22:502
560799170,0cyclictest2393-21bash21:32:191
5608991413,0cyclictest0-21swapper/221:17:312
5606991411,0cyclictest0-21swapper/000:16:450
5606991410,0cyclictest3152-21sshd21:28:040
112750140,0irq/25-eth00-21swapper/300:12:373
5609991312,0cyclictest2232-21sshd23:34:033
560999130,0cyclictest32157-21bash23:46:363
560999130,0cyclictest0-21swapper/323:41:163
560999130,0cyclictest0-21swapper/323:07:063
560999130,0cyclictest0-21swapper/321:15:083
5608991312,0cyclictest8099-21sshd00:00:372
5608991312,0cyclictest24095-21sshd00:28:502
5608991312,0cyclictest0-21swapper/222:25:572
5608991312,0cyclictest0-21swapper/222:16:532
5608991312,0cyclictest0-21swapper/222:16:532
5608991312,0cyclictest0-21swapper/200:22:282
5608991310,0cyclictest8684-21rm23:43:322
5608991310,0cyclictest26564-21bash00:16:042
560899130,0cyclictest0-21swapper/223:01:572
560799132,0cyclictest0-21swapper/121:55:171
5607991312,0cyclictest0-21swapper/123:52:171
5607991312,0cyclictest0-21swapper/100:25:521
5607991311,0cyclictest0-21swapper/122:40:161
5607991311,0cyclictest0-21swapper/121:38:411
560799130,0cyclictest0-21swapper/123:59:311
5606991313,0cyclictest0-21swapper/000:31:230
5606991312,0cyclictest6016-21sshd21:19:500
5606991312,0cyclictest0-21swapper/023:21:340
560699130,0cyclictest12862-21sshd00:01:180
5609991212,0cyclictest34-21rcuc/321:49:443
5609991212,0cyclictest0-21swapper/322:10:323
5609991212,0cyclictest0-21swapper/322:10:313
5609991211,0cyclictest0-21swapper/323:51:573
5609991211,0cyclictest0-21swapper/322:06:003
5609991211,0cyclictest0-21swapper/321:05:223
5609991210,0cyclictest0-21swapper/323:24:113
5609991210,0cyclictest0-21swapper/300:09:023
560999120,0cyclictest0-21swapper/323:17:003
560999120,0cyclictest0-21swapper/321:38:493
560999120,0cyclictest0-21swapper/321:10:363
5608991212,0cyclictest0-21swapper/223:46:132
5608991211,0cyclictest0-21swapper/223:27:172
5608991211,0cyclictest0-21swapper/222:04:062
5608991211,0cyclictest0-21swapper/200:10:282
5608991210,0cyclictest0-21swapper/223:53:252
5608991210,0cyclictest0-21swapper/222:43:012
5608991210,0cyclictest0-21swapper/221:25:462
560899120,0cyclictest0-21swapper/221:35:532
560899120,0cyclictest0-21swapper/200:09:402
5607991211,0cyclictest0-21swapper/123:35:131
5607991211,0cyclictest0-21swapper/123:28:011
5607991210,0cyclictest0-21swapper/123:11:451
5607991210,0cyclictest0-21swapper/121:11:161
560799120,0cyclictest14118-21sshd21:46:571
560799120,0cyclictest0-21swapper/123:16:171
560799120,0cyclictest0-21swapper/123:00:011
560799120,0cyclictest0-21swapper/122:37:361
560799120,0cyclictest0-21swapper/100:38:391
560699129,0cyclictest32515-21sshd21:36:190
5606991211,0cyclictest0-21swapper/023:32:300
5606991211,0cyclictest0-21swapper/022:54:240
5606991211,0cyclictest0-21swapper/022:30:070
5606991211,0cyclictest0-21swapper/021:01:140
5606991211,0cyclictest0-21swapper/000:37:480
5606991210,0cyclictest0-21swapper/022:44:310
560699120,0cyclictest29911-21diskmemload22:14:410
560699120,0cyclictest29911-21diskmemload22:14:410
560699120,0cyclictest0-21swapper/023:44:140
351120,0ktimersoftd/30-21swapper/323:56:163
112750120,0irq/25-eth00-21swapper/100:14:021
112750120,0irq/25-eth00-21swapper/023:51:050
112750120,0irq/25-eth00-21swapper/022:29:040
112750120,0irq/25-eth00-21swapper/000:08:400
5609991111,0cyclictest0-21swapper/322:59:543
5609991111,0cyclictest0-21swapper/322:50:023
5609991111,0cyclictest0-21swapper/322:21:273
5609991111,0cyclictest0-21swapper/300:24:293
5609991110,0cyclictest0-21swapper/322:32:093
5609991110,0cyclictest0-21swapper/321:56:573
5609991110,0cyclictest0-21swapper/300:35:233
5608991111,0cyclictest112750irq/25-eth023:09:092
5608991110,0cyclictest936-21sshd22:33:092
5608991110,0cyclictest0-21swapper/221:53:112
5608991110,0cyclictest0-21swapper/219:15:182
560899110,0cyclictest6748-21bash00:30:432
560899110,0cyclictest0-21swapper/220:15:302
560899110,0cyclictest0-21swapper/219:59:482
5607991111,0cyclictest9793-21sshd21:15:491
5607991111,0cyclictest0-21swapper/123:23:291
5607991111,0cyclictest0-21swapper/123:07:141
5607991110,0cyclictest0-21swapper/121:28:361
560799110,0cyclictest0-21swapper/123:42:251
560799110,0cyclictest0-21swapper/121:40:341
560799110,0cyclictest0-21swapper/121:09:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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