You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-26 - 22:59
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Tue May 26, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650580,0irq/26-eth1-rx-0-21swapper/307:05:123
120650580,0irq/26-eth1-rx-0-21swapper/107:05:521
112750460,0irq/25-eth00-21swapper/007:05:170
112750390,0irq/25-eth00-21swapper/207:05:372
271170,0ktimersoftd/27162-21cp11:53:352
1280899160,0cyclictest0-21swapper/207:35:162
12808991514,0cyclictest0-21swapper/210:34:042
1280799150,0cyclictest1539-21sshd10:34:221
12806991514,0cyclictest112750irq/25-eth012:00:060
1280699150,0cyclictest0-21swapper/012:10:130
12808991414,0cyclictest0-21swapper/212:09:552
12808991413,0cyclictest0-21swapper/212:19:542
1280699140,0cyclictest0-21swapper/012:07:040
112750140,0irq/25-eth00-21swapper/009:25:320
351130,0ktimersoftd/30-21swapper/310:38:003
12809991312,0cyclictest20699-21sshd10:24:593
12809991312,0cyclictest15716-21sshd12:11:593
1280999130,0cyclictest30108-21sshd11:13:333
12808991312,0cyclictest31127-21sshd10:17:412
12808991312,0cyclictest28-21ksoftirqd/209:50:232
12808991312,0cyclictest10794-21sshd12:11:172
12808991312,0cyclictest0-21swapper/212:37:332
12808991312,0cyclictest0-21swapper/212:02:562
1280899130,0cyclictest26-21rcuc/211:13:132
1280899130,0cyclictest26-21rcuc/210:52:252
1280899130,0cyclictest17251-21sshd09:45:442
1280899130,0cyclictest0-21swapper/211:49:552
12807991312,0cyclictest0-21swapper/110:41:271
12807991311,0cyclictest21352-21sshd12:12:451
12807991311,0cyclictest0-21swapper/110:11:151
1280799130,0cyclictest0-21swapper/111:00:231
12806991312,0cyclictest0-21swapper/009:51:220
12806991312,0cyclictest0-21swapper/009:21:180
12806991312,0cyclictest0-21swapper/007:10:150
12806991311,0cyclictest0-21swapper/010:05:480
1280699130,0cyclictest0-21swapper/011:05:020
1280699130,0cyclictest0-21swapper/011:05:020
112750130,0irq/25-eth013900-21sshd12:33:232
112750130,0irq/25-eth00-21swapper/209:44:212
41120,0ktimersoftd/00-21swapper/011:36:240
351120,0ktimersoftd/30-21swapper/312:24:243
12809991211,0cyclictest0-21swapper/312:18:233
12809991211,0cyclictest0-21swapper/310:41:433
12809991210,0cyclictest0-21swapper/312:35:123
1280999120,0cyclictest0-21swapper/309:23:043
12808991211,0cyclictest7241-21sshd10:23:092
12808991211,0cyclictest29351-21sshd10:43:142
12808991211,0cyclictest0-21swapper/211:01:092
12808991211,0cyclictest0-21swapper/210:45:202
12808991211,0cyclictest0-21swapper/210:12:002
12808991210,0cyclictest0-21swapper/211:55:502
12808991210,0cyclictest0-21swapper/211:06:072
12808991210,0cyclictest0-21swapper/211:06:072
1280899120,0cyclictest0-21swapper/209:15:242
12807991211,0cyclictest12687-21users11:15:221
12807991211,0cyclictest0-21swapper/110:39:221
1280799121,0cyclictest0-21swapper/110:29:241
12807991210,0cyclictest0-21swapper/109:22:211
1280799120,0cyclictest30671-21sshd11:09:201
1280799120,0cyclictest30671-21sshd11:09:201
1280799120,0cyclictest0-21swapper/112:36:481
1280799120,0cyclictest0-21swapper/109:39:181
1280799120,0cyclictest0-21swapper/109:12:271
1280799120,0cyclictest0-21swapper/107:20:151
12806991211,0cyclictest0-21swapper/011:10:020
12806991211,0cyclictest0-21swapper/009:11:260
12806991210,0cyclictest0-21swapper/010:51:200
12806991210,0cyclictest0-21swapper/010:28:340
12806991210,0cyclictest0-21swapper/009:32:410
1280699120,0cyclictest14642-21sshd11:28:440
112750120,0irq/25-eth07451-21sshd10:27:262
112750120,0irq/25-eth04712-21diskmemload11:45:100
112750120,0irq/25-eth00-21swapper/012:16:420
112750120,0irq/25-eth00-21swapper/011:50:130
41110,0ktimersoftd/010228-21sshd12:32:520
12809991111,0cyclictest0-21swapper/311:02:313
12809991111,0cyclictest0-21swapper/310:19:323
12809991111,0cyclictest0-21swapper/309:51:253
12809991110,0cyclictest17164-21sshd09:28:393
12809991110,0cyclictest0-21swapper/310:34:383
12809991110,0cyclictest0-21swapper/309:35:433
12809991110,0cyclictest0-21swapper/308:52:323
1280999110,0cyclictest7197-21sshd09:57:213
12808991111,0cyclictest0-21swapper/209:14:292
12808991110,0cyclictest3115-21sshd11:27:092
12808991110,0cyclictest0-21swapper/209:59:552
12807991111,0cyclictest0-21swapper/111:56:441
12807991111,0cyclictest0-21swapper/110:15:541
12807991111,0cyclictest0-21swapper/109:15:161
12807991111,0cyclictest0-21swapper/107:59:251
12807991111,0cyclictest0-21swapper/107:59:241
12807991110,0cyclictest0-21swapper/111:28:511
1280799110,0cyclictest6862-21sshd12:32:241
12806991111,0cyclictest0-21swapper/012:36:070
12806991111,0cyclictest0-21swapper/011:00:030
1280699110,0cyclictest4712-21diskmemload10:55:100
1280699110,0cyclictest4712-21diskmemload10:55:100
1280699110,0cyclictest0-21swapper/010:00:080
112750110,0irq/25-eth01803-21sshd09:43:490
112750110,0irq/25-eth00-21swapper/009:45:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional