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2026-06-01 - 09:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Mon Jun 01, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750660,0irq/25-eth00-21swapper/119:06:071
120650600,0irq/26-eth1-rx-0-21swapper/319:07:313
112750600,0irq/25-eth00-21swapper/219:09:232
2723824421,0sleep00-21swapper/019:06:210
2760299170,0cyclictest0-21swapper/100:15:141
2760599150,0cyclictest0-21swapper/323:50:183
2760599150,0cyclictest0-21swapper/323:50:173
27602991514,0cyclictest0-21swapper/122:51:181
2760299150,0cyclictest0-21swapper/123:25:231
2760599140,0cyclictest0-21swapper/323:38:223
27603991413,0cyclictest0-21swapper/222:02:342
27603991413,0cyclictest0-21swapper/200:14:342
27603991411,0cyclictest0-21swapper/221:27:162
27602991413,0cyclictest20480-21sshd23:06:311
27602991413,0cyclictest0-21swapper/100:03:561
27601991413,0cyclictest18522-21sshd22:53:210
27601991413,0cyclictest0-21swapper/023:17:020
27601991412,0cyclictest0-21swapper/023:56:390
27601991410,0cyclictest0-21swapper/000:01:190
2760199140,0cyclictest9037-21sshd22:30:180
27605991312,0cyclictest20308-21sshd22:18:553
27605991312,0cyclictest0-21swapper/323:05:573
27605991312,0cyclictest0-21swapper/321:22:553
2760599130,0cyclictest0-21swapper/321:26:513
2760599130,0cyclictest0-21swapper/300:01:503
27603991312,0cyclictest11551-21bash22:17:412
27603991311,0cyclictest0-21swapper/200:29:182
2760399130,0cyclictest0-21swapper/223:55:232
2760399130,0cyclictest0-21swapper/222:21:522
27602991312,0cyclictest0-21swapper/121:30:541
2760299130,0cyclictest0-21swapper/123:35:201
2760299130,0cyclictest0-21swapper/122:59:331
2760199130,0cyclictest2596-21sshd21:46:120
2760199130,0cyclictest0-21swapper/021:11:420
112750130,0irq/25-eth00-21swapper/300:21:573
351120,0ktimersoftd/310266-21sshd22:21:493
351120,0ktimersoftd/30-21swapper/323:44:043
351120,0ktimersoftd/30-21swapper/300:37:173
27605991211,0cyclictest8-21rcu_preempt22:32:163
27605991211,0cyclictest19534-21diskmemload00:07:103
27605991211,0cyclictest0-21swapper/321:47:263
2760599120,0cyclictest34-21rcuc/322:54:203
2760599120,0cyclictest2656-21bash00:13:493
27603991211,0cyclictest0-21swapper/222:53:072
27603991211,0cyclictest0-21swapper/221:47:012
27603991211,0cyclictest0-21swapper/221:43:032
27603991211,0cyclictest0-21swapper/221:35:102
27603991210,0cyclictest0-21swapper/221:31:132
2760399120,0cyclictest0-21swapper/223:39:562
2760399120,0cyclictest0-21swapper/222:36:302
2760399120,0cyclictest0-21swapper/221:15:252
2760399120,0cyclictest0-21swapper/200:04:522
27602991211,0cyclictest28614-21sshd22:06:581
27602991211,0cyclictest22350-21sshd21:57:311
27602991211,0cyclictest0-21swapper/121:45:411
27602991210,0cyclictest0-21swapper/122:41:261
2760299120,0cyclictest0-21swapper/123:42:321
2760299120,0cyclictest0-21swapper/122:45:511
2760299120,0cyclictest0-21swapper/122:37:011
2760299120,0cyclictest0-21swapper/121:38:491
2760299120,0cyclictest0-21swapper/100:33:111
27601991211,0cyclictest32586-21sshd22:42:110
27601991211,0cyclictest0-21swapper/023:20:390
27601991211,0cyclictest0-21swapper/023:03:550
27601991210,0cyclictest24490-21sshd23:46:060
27601991210,0cyclictest24490-21sshd23:46:050
2760199120,0cyclictest0-21swapper/023:30:240
2760199120,0cyclictest0-21swapper/022:59:160
2760199120,0cyclictest0-21swapper/021:50:090
2760199120,0cyclictest0-21swapper/021:34:200
112750120,0irq/25-eth010544-21sshd22:13:150
112750120,0irq/25-eth00-21swapper/322:42:303
9950110,0irq/24-0000:00:5489-21sshd23:47:572
9950110,0irq/24-0000:00:5489-21sshd23:47:572
41110,0ktimersoftd/025440-21sshd00:29:550
41110,0ktimersoftd/016750-21sshd22:09:490
41110,0ktimersoftd/00-21swapper/000:13:270
351110,0ktimersoftd/30-21swapper/322:56:263
27605991111,0cyclictest15677-21sshd22:48:393
27605991111,0cyclictest0-21swapper/321:40:353
27605991111,0cyclictest0-21swapper/321:16:033
27605991110,0cyclictest0-21swapper/323:33:303
27605991110,0cyclictest0-21swapper/323:21:243
27605991110,0cyclictest0-21swapper/300:15:043
27603991111,0cyclictest0-21swapper/223:30:112
27603991111,0cyclictest0-21swapper/221:11:292
27603991110,0cyclictest28143-21users20:15:212
27603991110,0cyclictest22198-21sshd22:10:222
27603991110,0cyclictest16421-21sshd22:09:452
2760399110,0cyclictest11383-21sshd23:53:042
2760399110,0cyclictest11383-21sshd23:53:032
2760399110,0cyclictest0-21swapper/223:43:322
27602991111,0cyclictest5270-21sshd23:30:271
27602991111,0cyclictest0-21swapper/123:48:291
27602991111,0cyclictest0-21swapper/123:48:281
27602991111,0cyclictest0-21swapper/123:01:531
27602991111,0cyclictest0-21swapper/122:24:281
27602991111,0cyclictest0-21swapper/120:22:371
27602991111,0cyclictest0-21swapper/120:09:151
27602991110,0cyclictest0-21swapper/123:16:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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