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2026-02-15 - 14:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Feb 15, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750650,0irq/25-eth00-21swapper/307:05:113
120650640,0irq/26-eth1-rx-0-21swapper/107:05:111
112750540,0irq/25-eth00-21swapper/207:06:472
482324623,0sleep00-21swapper/007:09:270
493399190,0cyclictest6207-21cut07:10:171
493599160,0cyclictest0-21swapper/311:51:123
493599160,0cyclictest0-21swapper/309:59:543
4935991513,0cyclictest0-21swapper/309:10:523
493499150,0cyclictest0-21swapper/210:20:162
4933991512,0cyclictest0-21swapper/110:05:591
112750150,0irq/25-eth00-21swapper/311:27:303
4935991412,0cyclictest0-21swapper/311:31:203
4935991412,0cyclictest0-21swapper/311:08:063
4935991411,0cyclictest0-21swapper/312:36:303
493399140,0cyclictest28168-21sshd12:36:541
493399140,0cyclictest0-21swapper/109:39:431
4932991413,0cyclictest0-21swapper/010:39:500
4935991311,0cyclictest0-21swapper/310:50:263
4935991310,0cyclictest0-21swapper/311:55:373
4935991310,0cyclictest0-21swapper/311:10:183
493599130,0cyclictest0-21swapper/311:17:233
4934991312,0cyclictest29367-21diskmemload12:05:392
4934991312,0cyclictest1522-21snmpd08:02:112
4933991312,0cyclictest29367-21diskmemload09:26:371
4933991312,0cyclictest0-21swapper/111:12:261
4933991311,0cyclictest5205-21sshd10:18:041
493399130,0cyclictest0-21swapper/111:20:181
493399130,0cyclictest0-21swapper/110:31:261
4932991312,0cyclictest0-21swapper/012:24:240
4932991312,0cyclictest0-21swapper/009:37:070
4932991311,0cyclictest0-21swapper/011:54:330
4932991311,0cyclictest0-21swapper/010:24:160
493299130,0cyclictest0-21swapper/012:10:430
493599129,0cyclictest17349-21sshd10:48:143
4935991212,0cyclictest0-21swapper/310:28:013
4935991212,0cyclictest0-21swapper/309:43:253
4935991211,0cyclictest0-21swapper/310:24:183
4935991211,0cyclictest0-21swapper/309:51:263
4935991210,0cyclictest0-21swapper/310:41:513
4935991210,0cyclictest0-21swapper/309:22:013
493599120,0cyclictest17654-21sshd12:29:393
493599120,0cyclictest0-21swapper/311:22:023
493599120,0cyclictest0-21swapper/309:46:043
4934991211,0cyclictest12006-21sshd09:23:362
4934991211,0cyclictest0-21swapper/212:21:352
4934991211,0cyclictest0-21swapper/211:54:092
4934991211,0cyclictest0-21swapper/210:16:142
4934991211,0cyclictest0-21swapper/209:47:522
4934991210,0cyclictest20791-21sshd12:35:312
4934991210,0cyclictest0-21swapper/211:45:062
4934991210,0cyclictest0-21swapper/211:13:022
493499120,0cyclictest0-21swapper/211:42:532
493499120,0cyclictest0-21swapper/210:02:112
4933991211,0cyclictest4238-21sshd12:04:491
4933991211,0cyclictest2526-21bash10:11:551
4933991211,0cyclictest2526-21bash10:11:541
4933991211,0cyclictest0-21swapper/111:53:191
4933991211,0cyclictest0-21swapper/110:01:471
4933991211,0cyclictest0-21swapper/109:47:441
4933991210,0cyclictest22461-21bash10:43:311
493399120,0cyclictest0-21swapper/110:25:441
493399120,0cyclictest0-21swapper/110:20:201
493399120,0cyclictest0-21swapper/109:53:201
493399120,0cyclictest0-21swapper/109:20:121
4932991210,0cyclictest29367-21diskmemload11:22:430
4932991210,0cyclictest0-21swapper/009:15:030
493299120,0cyclictest0-21swapper/012:17:330
493299120,0cyclictest0-21swapper/011:45:290
493299120,0cyclictest0-21swapper/010:02:190
112750120,0irq/25-eth06029-21sshd09:50:150
4935991111,0cyclictest0-21swapper/310:35:413
4935991110,0cyclictest4310-21sshd10:57:073
4935991110,0cyclictest29367-21diskmemload12:13:443
4935991110,0cyclictest15496-21sshd11:38:323
4935991110,0cyclictest0-21swapper/312:25:013
493499116,0cyclictest0-21swapper/211:25:572
4934991111,0cyclictest7851-21sshd10:29:492
4934991111,0cyclictest0-21swapper/209:31:512
4934991110,0cyclictest0-21swapper/211:33:502
4934991110,0cyclictest0-21swapper/211:17:412
4934991110,0cyclictest0-21swapper/209:53:282
4934991110,0cyclictest0-21swapper/209:39:392
493499110,0cyclictest0-21swapper/207:39:032
493399119,0cyclictest0-21swapper/108:59:181
4933991111,0cyclictest0-21swapper/112:32:141
4933991111,0cyclictest0-21swapper/107:20:131
4933991110,0cyclictest17557-21bash11:33:141
493399110,0cyclictest0-21swapper/108:26:121
493399110,0cyclictest0-21swapper/107:49:221
493299119,0cyclictest0-21swapper/008:29:090
493299119,0cyclictest0-21swapper/007:37:560
4932991111,0cyclictest0-21swapper/011:15:380
4932991111,0cyclictest0-21swapper/010:14:250
4932991111,0cyclictest0-21swapper/010:14:250
4932991111,0cyclictest0-21swapper/009:42:280
4932991110,0cyclictest7812-21sshd09:45:080
4932991110,0cyclictest0-21swapper/009:34:270
493299110,0cyclictest8049-21cp10:18:360
493299110,0cyclictest0-21swapper/007:53:310
112750110,0irq/25-eth023661-21nfsd408:55:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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