You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-12 - 08:31
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed Aug 12, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750620,0irq/25-eth00-21swapper/119:05:521
112750610,0irq/25-eth00-21swapper/319:05:413
112750560,0irq/25-eth00-21swapper/219:07:542
120650470,0irq/26-eth1-rx-0-21swapper/019:05:390
2739799180,0cyclictest18115-21id22:23:443
2739499180,0cyclictest0-21swapper/022:35:200
2739699160,0cyclictest0-21swapper/222:35:142
2739799150,0cyclictest0-21swapper/300:00:193
2739699150,0cyclictest0-21swapper/222:10:182
2739699150,0cyclictest0-21swapper/222:10:182
27394991514,0cyclictest0-21swapper/000:34:370
27397991413,0cyclictest0-21swapper/323:01:123
27397991413,0cyclictest0-21swapper/322:35:173
27396991410,0cyclictest0-21swapper/223:35:142
2739699140,0cyclictest11728-21sshd00:22:192
27397991312,0cyclictest12416-21bash23:12:133
27397991312,0cyclictest0-21swapper/321:57:393
27397991312,0cyclictest0-21swapper/321:34:113
2739799130,0cyclictest19304-21diskmemload21:20:213
2739799130,0cyclictest0-21swapper/323:40:213
2739799130,0cyclictest0-21swapper/322:29:083
27396991312,0cyclictest24108-21sshd22:57:172
27396991312,0cyclictest0-21swapper/222:06:022
27396991312,0cyclictest0-21swapper/222:00:572
27396991312,0cyclictest0-21swapper/222:00:562
27396991312,0cyclictest0-21swapper/221:59:392
2739699130,0cyclictest31804-21bash21:52:462
2739699130,0cyclictest0-21swapper/220:40:182
27395991313,0cyclictest0-21swapper/122:26:511
27395991312,0cyclictest9905-21sshd00:34:311
27395991312,0cyclictest0-21swapper/123:06:351
27394991312,0cyclictest0-21swapper/023:45:160
27394991312,0cyclictest0-21swapper/021:59:530
2739499130,0cyclictest0-21swapper/023:38:040
120650130,0irq/26-eth1-rx-19304-21diskmemload23:36:233
27397991211,0cyclictest6630-21sshd22:42:443
27397991211,0cyclictest0-21swapper/323:24:183
27397991211,0cyclictest0-21swapper/300:18:063
27397991210,0cyclictest29653-21bash00:12:113
27397991210,0cyclictest0-21swapper/322:05:203
2739799120,0cyclictest0-21swapper/321:45:413
2739799120,0cyclictest0-21swapper/321:45:413
2739799120,0cyclictest0-21swapper/321:19:053
2739799120,0cyclictest0-21swapper/319:55:203
2739699129,0cyclictest18808-21sshd00:06:382
27396991212,0cyclictest0-21swapper/223:23:112
27396991212,0cyclictest0-21swapper/222:31:092
27396991211,0cyclictest0-21swapper/223:28:032
27396991211,0cyclictest0-21swapper/200:10:142
27396991210,0cyclictest0-21swapper/200:36:432
2739699120,0cyclictest19626-21sshd00:15:062
2739699120,0cyclictest0-21swapper/223:55:502
2739699120,0cyclictest0-21swapper/223:13:252
27395991212,0cyclictest0-21swapper/122:36:501
27395991211,0cyclictest19304-21diskmemload21:36:471
27395991211,0cyclictest0-21swapper/100:25:001
27395991210,0cyclictest7862-21sshd00:01:041
2739599120,0cyclictest28983-21sshd22:16:521
2739599120,0cyclictest0-21swapper/121:44:271
27394991211,0cyclictest7011-21sshd00:00:570
27394991211,0cyclictest17332-21sshd23:41:390
27394991211,0cyclictest0-21swapper/022:01:110
27394991211,0cyclictest0-21swapper/022:01:100
27394991211,0cyclictest0-21swapper/021:15:450
27394991210,0cyclictest31219-21sshd21:36:120
27394991210,0cyclictest0-21swapper/022:27:460
2739499120,0cyclictest0-21swapper/023:57:210
2739499120,0cyclictest0-21swapper/023:21:060
2739499120,0cyclictest0-21swapper/021:49:120
2739499120,0cyclictest0-21swapper/021:49:120
2739499120,0cyclictest0-21swapper/000:09:250
112750120,0irq/25-eth021023-21sshd23:17:283
112750120,0irq/25-eth012945-21bash00:05:501
112750120,0irq/25-eth00-21swapper/222:17:402
112750120,0irq/25-eth00-21swapper/000:27:070
112750120,0irq/25-eth00-21swapper/000:22:540
41110,0ktimersoftd/00-21swapper/000:36:290
2739799119,0cyclictest0-21swapper/322:16:363
2739799119,0cyclictest0-21swapper/320:52:223
27397991111,0cyclictest0-21swapper/323:31:313
27397991111,0cyclictest0-21swapper/323:07:213
27397991111,0cyclictest0-21swapper/321:51:013
27397991110,0cyclictest0-21swapper/323:27:123
27397991110,0cyclictest0-21swapper/322:04:033
27397991110,0cyclictest0-21swapper/322:04:023
27397991110,0cyclictest0-21swapper/321:41:383
27397991110,0cyclictest0-21swapper/320:33:053
27397991110,0cyclictest0-21swapper/300:20:253
2739799110,0cyclictest0-21swapper/321:35:273
2739799110,0cyclictest0-21swapper/320:55:093
2739799110,0cyclictest0-21swapper/320:42:363
2739799110,0cyclictest0-21swapper/320:36:413
2739799110,0cyclictest0-21swapper/320:29:293
2739799110,0cyclictest0-21swapper/319:17:003
27396991111,0cyclictest0-21swapper/223:47:212
27396991111,0cyclictest0-21swapper/221:37:142
27396991111,0cyclictest0-21swapper/220:30:192
27396991111,0cyclictest0-21swapper/220:20:202
27396991111,0cyclictest0-21swapper/200:33:072
27396991110,0cyclictest0-21swapper/221:11:402
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional