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2025-12-14 - 06:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Dec 14, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/319:05:153
112750600,0irq/25-eth00-21swapper/119:05:211
198724931,0sleep20-21swapper/219:05:082
399624622,0sleep00-21swapper/019:08:530
271180,0ktimersoftd/227560-21sshd00:23:462
4153991311,0cyclictest0-21swapper/323:40:153
415299130,0cyclictest0-21swapper/222:33:132
4151991311,0cyclictest0-21swapper/120:10:121
415099130,0cyclictest28460-21diskmemload22:28:590
415099130,0cyclictest0-21swapper/023:48:250
4153991212,0cyclictest0-21swapper/320:05:143
4153991211,0cyclictest0-21swapper/323:57:283
4153991211,0cyclictest0-21swapper/322:41:003
4153991211,0cyclictest0-21swapper/322:32:253
4153991210,0cyclictest0-21swapper/322:23:493
415399120,0cyclictest0-21swapper/321:13:113
415399120,0cyclictest0-21swapper/300:25:173
4152991211,0cyclictest22049-21sshd21:42:272
4152991210,0cyclictest0-21swapper/223:53:362
4152991210,0cyclictest0-21swapper/222:17:532
415299120,0cyclictest0-21swapper/221:22:212
4151991212,0cyclictest0-21swapper/100:28:411
4151991211,0cyclictest0-21swapper/122:07:111
4151991210,0cyclictest31418-21bash21:29:541
4151991210,0cyclictest0-21swapper/123:22:411
4151991210,0cyclictest0-21swapper/121:54:451
4151991210,0cyclictest0-21swapper/121:13:381
415199120,0cyclictest0-21swapper/123:55:131
415199120,0cyclictest0-21swapper/122:45:241
415199120,0cyclictest0-21swapper/122:32:581
415199120,0cyclictest0-21swapper/120:35:111
4150991210,0cyclictest0-21swapper/023:04:240
4150991210,0cyclictest0-21swapper/021:21:560
4150991210,0cyclictest0-21swapper/020:10:300
4150991210,0cyclictest0-21swapper/000:04:420
41120,0ktimersoftd/06007-21df_abs21:15:130
112750120,0irq/25-eth00-21swapper/300:20:073
415399119,0cyclictest0-21swapper/300:06:023
4153991111,0cyclictest0-21swapper/323:31:393
4153991111,0cyclictest0-21swapper/323:02:023
4153991111,0cyclictest0-21swapper/322:15:133
4153991111,0cyclictest0-21swapper/321:26:333
4153991111,0cyclictest0-21swapper/321:17:573
4153991110,0cyclictest0-21swapper/323:06:483
415399110,0cyclictest0-21swapper/322:53:263
415399110,0cyclictest0-21swapper/321:48:303
415399110,0cyclictest0-21swapper/321:39:553
415399110,0cyclictest0-21swapper/300:19:243
4152991111,0cyclictest0-21swapper/223:05:442
4152991111,0cyclictest0-21swapper/222:45:382
4152991111,0cyclictest0-21swapper/221:34:472
4152991111,0cyclictest0-21swapper/221:14:412
4152991111,0cyclictest0-21swapper/219:55:212
4152991110,0cyclictest0-21swapper/221:18:312
4152991110,0cyclictest0-21swapper/220:02:192
415299110,0cyclictest0-21swapper/221:57:472
415299110,0cyclictest0-21swapper/221:53:572
415299110,0cyclictest0-21swapper/221:25:132
415299110,0cyclictest0-21swapper/200:30:122
415199119,0cyclictest0-21swapper/123:06:251
415199119,0cyclictest0-21swapper/122:57:501
4151991111,0cyclictest0-21swapper/123:35:081
4151991111,0cyclictest0-21swapper/123:18:511
4151991111,0cyclictest0-21swapper/123:02:361
4151991111,0cyclictest0-21swapper/122:41:341
4151991111,0cyclictest0-21swapper/122:15:471
4151991111,0cyclictest0-21swapper/119:55:481
4151991111,0cyclictest0-21swapper/119:20:151
4151991110,0cyclictest0-21swapper/122:03:211
415199110,0cyclictest28460-21diskmemload22:20:121
415199110,0cyclictest0-21swapper/121:46:091
415199110,0cyclictest0-21swapper/121:33:441
415199110,0cyclictest0-21swapper/121:17:281
4150991111,0cyclictest0-21swapper/023:44:350
4150991111,0cyclictest0-21swapper/023:28:200
4150991111,0cyclictest0-21swapper/023:24:290
4150991110,0cyclictest0-21swapper/021:34:220
4150991110,0cyclictest0-21swapper/019:30:530
4150991110,0cyclictest0-21swapper/000:32:260
4150991110,0cyclictest0-21swapper/000:12:220
415099110,0cyclictest0-21swapper/023:08:130
415099110,0cyclictest0-21swapper/021:57:220
415099110,0cyclictest0-21swapper/020:22:070
415099110,0cyclictest0-21swapper/020:19:120
415099110,0cyclictest0-21swapper/019:15:160
415099110,0cyclictest0-21swapper/000:23:510
415099110,0cyclictest0-21swapper/000:16:120
415099110,0cyclictest0-21swapper/000:08:310
351110,0ktimersoftd/30-21swapper/323:16:333
351110,0ktimersoftd/30-21swapper/321:50:363
271110,0ktimersoftd/20-21swapper/221:47:062
191110,0ktimersoftd/10-21swapper/100:38:471
415399109,0cyclictest0-21swapper/323:45:153
415399109,0cyclictest0-21swapper/323:27:493
4153991010,0cyclictest0-21swapper/323:36:263
4153991010,0cyclictest0-21swapper/323:23:043
4153991010,0cyclictest0-21swapper/323:10:393
4153991010,0cyclictest0-21swapper/321:44:403
4153991010,0cyclictest0-21swapper/319:30:443
4153991010,0cyclictest0-21swapper/300:10:493
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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