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2026-02-07 - 10:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Feb 07, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750660,0irq/25-eth00-21swapper/119:05:121
112750600,0irq/25-eth00-21swapper/319:09:073
2451825921,0sleep00-21swapper/019:05:130
112750570,0irq/25-eth00-21swapper/219:09:122
26305991514,0cyclictest112750irq/25-eth023:39:483
26303991514,0cyclictest0-21swapper/123:05:211
2630299150,0cyclictest0-21swapper/021:29:230
26305991413,0cyclictest31089-21sshd23:15:023
26305991413,0cyclictest0-21swapper/322:30:473
26305991413,0cyclictest0-21swapper/322:02:263
26305991413,0cyclictest0-21swapper/300:19:103
2630599140,0cyclictest843-21sshd21:46:323
26305991312,0cyclictest11808-21sshd23:41:453
26305991312,0cyclictest0-21swapper/322:10:133
26305991312,0cyclictest0-21swapper/321:43:443
26305991310,0cyclictest18234-21sshd00:32:103
2630599130,0cyclictest8127-21sshd22:51:423
2630599130,0cyclictest1818-21sshd21:31:523
26304991312,0cyclictest27936-21bash23:54:082
26304991312,0cyclictest0-21swapper/223:11:392
26304991312,0cyclictest0-21swapper/222:33:382
26304991312,0cyclictest0-21swapper/221:58:342
26304991311,0cyclictest0-21swapper/223:58:052
26304991311,0cyclictest0-21swapper/223:24:172
2630499130,0cyclictest0-21swapper/200:38:182
26303991312,0cyclictest18054-21sshd22:18:461
26303991312,0cyclictest0-21swapper/123:19:461
26303991311,0cyclictest0-21swapper/122:07:441
2630399130,0cyclictest0-21swapper/122:52:421
2630399130,0cyclictest0-21swapper/120:20:211
2630299130,0cyclictest18325-21diskmemload22:35:430
2630299130,0cyclictest0-21swapper/020:20:150
41120,0ktimersoftd/00-21swapper/022:01:470
351120,0ktimersoftd/30-21swapper/322:36:353
2630599120,0cyclictest0-21swapper/323:31:533
2630599120,0cyclictest0-21swapper/323:04:213
26304991211,0cyclictest8689-21sshd22:27:082
26304991211,0cyclictest13605-21sshd00:31:262
26304991211,0cyclictest0-21swapper/223:42:182
26304991211,0cyclictest0-21swapper/200:29:142
26304991211,0cyclictest0-21swapper/200:11:202
26304991210,0cyclictest9724-21sshd22:22:222
26304991210,0cyclictest0-21swapper/223:48:132
26304991210,0cyclictest0-21swapper/223:38:222
2630499120,0cyclictest19531-21sshd23:28:142
2630499120,0cyclictest0-21swapper/222:51:322
2630499120,0cyclictest0-21swapper/222:44:202
2630499120,0cyclictest0-21swapper/221:49:572
2630499120,0cyclictest0-21swapper/200:20:242
26303991211,0cyclictest20121-21sshd22:43:451
26303991211,0cyclictest0-21swapper/123:12:331
26303991211,0cyclictest0-21swapper/122:59:541
26303991211,0cyclictest0-21swapper/121:36:571
26303991211,0cyclictest0-21swapper/100:25:451
26303991210,0cyclictest0-21swapper/100:23:321
2630399120,0cyclictest0-21swapper/123:47:101
2630399120,0cyclictest0-21swapper/119:38:031
2630399120,0cyclictest0-21swapper/100:30:091
2630399120,0cyclictest0-21swapper/100:19:081
2630399120,0cyclictest0-21swapper/100:10:171
26302991212,0cyclictest0-21swapper/023:54:150
26302991211,0cyclictest5899-21sshd21:57:090
26302991211,0cyclictest0-21swapper/022:22:280
26302991211,0cyclictest0-21swapper/021:30:540
26302991210,0cyclictest0-21swapper/023:58:110
26302991210,0cyclictest0-21swapper/023:46:200
26302991210,0cyclictest0-21swapper/021:47:160
26302991210,0cyclictest0-21swapper/021:05:000
26302991210,0cyclictest0-21swapper/020:40:220
2630299120,0cyclictest0-21swapper/023:30:190
2630299120,0cyclictest0-21swapper/023:11:430
2630299120,0cyclictest0-21swapper/022:48:090
2630299120,0cyclictest0-21swapper/021:20:050
2630299120,0cyclictest0-21swapper/000:00:100
191120,0ktimersoftd/10-21swapper/123:04:541
112750120,0irq/25-eth015753-21sshd23:27:390
112750120,0irq/25-eth010612-21sshd22:12:391
112750120,0irq/25-eth00-21swapper/321:38:383
9950110,0irq/24-0000:00:9944-21sshd00:25:550
26305991111,0cyclictest0-21swapper/323:45:433
26305991111,0cyclictest0-21swapper/300:36:363
26305991111,0cyclictest0-21swapper/300:01:173
26305991110,0cyclictest24355-21sshd21:10:453
26305991110,0cyclictest0-21swapper/323:57:193
26305991110,0cyclictest0-21swapper/323:06:063
26305991110,0cyclictest0-21swapper/321:52:063
26305991110,0cyclictest0-21swapper/320:45:183
2630599110,0cyclictest0-21swapper/320:11:513
2630599110,0cyclictest0-21swapper/300:21:223
2630599110,0cyclictest0-21swapper/300:10:213
2630499119,0cyclictest0-21swapper/221:35:342
26304991111,0cyclictest3005-21sshd23:00:422
26304991111,0cyclictest0-21swapper/223:17:052
26304991111,0cyclictest0-21swapper/223:06:102
26304991111,0cyclictest0-21swapper/222:04:502
26304991111,0cyclictest0-21swapper/200:02:172
26304991110,0cyclictest9119-21sshd21:52:452
26304991110,0cyclictest17712-21sshd21:19:442
26304991110,0cyclictest0-21swapper/222:06:212
2630499110,0cyclictest0-21swapper/219:25:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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