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2026-02-24 - 14:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Tue Feb 24, 2026 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650640,0irq/26-eth1-rx-0-21swapper/319:08:393
120650640,0irq/26-eth1-rx-0-21swapper/119:08:191
120650600,0irq/26-eth1-rx-0-21swapper/019:08:230
112750560,0irq/25-eth00-21swapper/219:06:362
17006991615,0cyclictest31097-21sshd23:11:173
17004991512,0cyclictest0-21swapper/121:16:561
1700399150,0cyclictest0-21swapper/022:33:130
17006991413,0cyclictest2645-21sshd22:27:433
1700699141,0cyclictest0-21swapper/323:30:143
17005991413,0cyclictest0-21swapper/221:58:362
17005991413,0cyclictest0-21swapper/220:15:202
17004991411,0cyclictest0-21swapper/123:33:171
1700499140,0cyclictest0-21swapper/100:24:391
17003991411,0cyclictest0-21swapper/023:32:060
9950130,0irq/24-0000:00:29658-21sshd22:31:441
17006991312,0cyclictest28003-21id00:09:563
17006991311,0cyclictest0-21swapper/323:40:403
17006991311,0cyclictest0-21swapper/323:40:403
17006991311,0cyclictest0-21swapper/321:49:363
17006991311,0cyclictest0-21swapper/300:21:053
17006991310,0cyclictest19952-21sshd22:00:393
1700699130,0cyclictest0-21swapper/322:18:253
17005991312,0cyclictest0-21swapper/222:35:252
17005991312,0cyclictest0-21swapper/222:16:592
17005991312,0cyclictest0-21swapper/222:11:362
17005991312,0cyclictest0-21swapper/200:28:492
1700599130,0cyclictest17940-21sshd00:37:522
1700599130,0cyclictest0-21swapper/222:50:112
1700599130,0cyclictest0-21swapper/221:34:472
1700599130,0cyclictest0-21swapper/220:35:222
17004991312,0cyclictest0-21swapper/100:11:301
17004991310,0cyclictest6813-21sshd23:42:011
17004991310,0cyclictest6813-21sshd23:42:011
17004991310,0cyclictest11304-21id22:14:181
17003991311,0cyclictest0-21swapper/021:23:020
112750130,0irq/25-eth031401-21sshd21:38:003
112750130,0irq/25-eth010-21rcuc/000:15:070
112750130,0irq/25-eth00-21swapper/323:06:523
9950120,0irq/24-0000:00:0-21swapper/121:39:481
17006991212,0cyclictest112750irq/25-eth021:15:003
17006991211,0cyclictest6023-21sshd21:29:173
17006991211,0cyclictest11854-21bash23:28:073
17006991211,0cyclictest11854-21bash23:28:073
17006991211,0cyclictest0-21swapper/323:37:113
17006991211,0cyclictest0-21swapper/323:37:103
17006991211,0cyclictest0-21swapper/322:59:463
17006991211,0cyclictest0-21swapper/322:38:313
17006991210,0cyclictest0-21swapper/323:56:483
1700699120,0cyclictest0-21swapper/322:11:553
17005991212,0cyclictest0-21swapper/200:22:252
17005991211,0cyclictest18177-21sshd21:50:362
17005991211,0cyclictest0-21swapper/223:48:292
17005991211,0cyclictest0-21swapper/222:58:252
17005991211,0cyclictest0-21swapper/221:41:032
17005991211,0cyclictest0-21swapper/200:03:362
17005991210,0cyclictest9451-21sshd23:52:132
17005991210,0cyclictest0-21swapper/223:59:532
17005991210,0cyclictest0-21swapper/223:39:472
17005991210,0cyclictest0-21swapper/223:39:472
17005991210,0cyclictest0-21swapper/222:08:222
1700599120,0cyclictest9033-21diskmemload23:19:012
1700599120,0cyclictest1480-21nfsd22:01:522
1700599120,0cyclictest0-21swapper/223:32:482
17004991212,0cyclictest0-21swapper/122:07:491
17004991212,0cyclictest0-21swapper/100:04:051
17004991211,0cyclictest9033-21diskmemload23:22:511
17004991211,0cyclictest16082-21sshd23:09:091
17004991211,0cyclictest0-21swapper/123:36:471
17004991211,0cyclictest0-21swapper/123:36:471
17004991211,0cyclictest0-21swapper/122:47:381
17004991211,0cyclictest0-21swapper/122:01:171
17004991211,0cyclictest0-21swapper/100:26:511
17004991210,0cyclictest0-21swapper/123:45:291
17004991210,0cyclictest0-21swapper/123:19:221
17004991210,0cyclictest0-21swapper/121:40:451
1700499120,0cyclictest0-21swapper/123:26:201
1700499120,0cyclictest0-21swapper/123:26:201
1700499120,0cyclictest0-21swapper/122:44:241
1700499120,0cyclictest0-21swapper/120:20:181
1700499120,0cyclictest0-21swapper/120:20:181
17003991212,0cyclictest0-21swapper/021:26:180
17003991211,0cyclictest817-21sshd00:30:180
17003991211,0cyclictest31226-21bash23:16:110
17003991211,0cyclictest27233-21sshd21:37:190
17003991211,0cyclictest0-21swapper/022:47:440
17003991211,0cyclictest0-21swapper/022:17:250
17003991211,0cyclictest0-21swapper/021:15:020
17003991210,0cyclictest0-21swapper/023:51:300
1700399120,0cyclictest9033-21diskmemload22:20:370
1700399120,0cyclictest0-21swapper/021:31:030
1700399120,0cyclictest0-21swapper/021:10:150
112750120,0irq/25-eth00-21swapper/322:21:123
112750120,0irq/25-eth00-21swapper/123:10:591
41110,0ktimersoftd/09033-21diskmemload22:25:190
17006991111,0cyclictest34-21rcuc/321:30:473
17006991111,0cyclictest0-21swapper/322:50:013
17006991111,0cyclictest0-21swapper/321:19:453
17006991110,0cyclictest36-21ksoftirqd/300:00:323
17006991110,0cyclictest31147-21sshd00:25:113
17006991110,0cyclictest19283-21id00:33:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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