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2026-06-25 - 04:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Thu Jun 25, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750680,0irq/25-eth00-21swapper/119:05:551
112750660,0irq/25-eth00-21swapper/319:05:113
120650500,0irq/26-eth1-rx-0-21swapper/019:05:100
112750420,0irq/25-eth00-21swapper/219:07:552
31836991814,0cyclictest0-21swapper/121:12:561
3183899160,0cyclictest0-21swapper/322:50:223
3183799160,0cyclictest0-21swapper/219:10:152
31836991514,0cyclictest0-21swapper/121:59:381
3183699150,0cyclictest0-21swapper/120:45:151
3183599150,0cyclictest0-21swapper/022:45:180
112750150,0irq/25-eth00-21swapper/000:33:490
31836991413,0cyclictest0-21swapper/121:30:221
3183699140,0cyclictest23737-21diskmemload22:45:191
31835991413,0cyclictest29429-21sshd00:25:500
112750140,0irq/25-eth015910-21sshd23:45:211
351130,0ktimersoftd/30-21swapper/300:11:033
31838991312,0cyclictest0-21swapper/321:16:203
31838991310,0cyclictest0-21swapper/323:49:333
3183899130,0cyclictest0-21swapper/300:04:473
31837991312,0cyclictest0-21swapper/223:00:052
31836991312,0cyclictest0-21swapper/121:42:261
31836991311,0cyclictest0-21swapper/121:26:041
31835991312,0cyclictest23160-21sshd23:29:220
3183599130,0cyclictest0-21swapper/000:14:270
3183599130,0cyclictest0-21swapper/000:02:150
271130,0ktimersoftd/20-21swapper/222:42:462
191130,0ktimersoftd/10-21swapper/123:07:561
41120,0ktimersoftd/031392-21sshd23:09:110
351120,0ktimersoftd/323737-21diskmemload23:40:383
31838991212,0cyclictest0-21swapper/322:27:543
31838991211,0cyclictest0-21swapper/323:35:583
31838991210,0cyclictest0-21swapper/321:56:043
31838991210,0cyclictest0-21swapper/321:48:173
31837991212,0cyclictest0-21swapper/222:47:032
31837991211,0cyclictest9695-21sshd21:20:382
31837991211,0cyclictest22072-21sshd23:46:112
31837991211,0cyclictest0-21swapper/222:51:082
31837991211,0cyclictest0-21swapper/221:32:432
3183799120,0cyclictest0-21swapper/222:22:122
31836991211,0cyclictest0-21swapper/122:31:281
31836991211,0cyclictest0-21swapper/122:08:491
31836991211,0cyclictest0-21swapper/100:06:091
31836991210,0cyclictest0-21swapper/123:30:501
3183699120,0cyclictest0-21swapper/123:41:591
3183699120,0cyclictest0-21swapper/121:38:091
3183699120,0cyclictest0-21swapper/119:10:101
31835991211,0cyclictest21843-21bash22:17:080
31835991211,0cyclictest18284-21sensors_fan22:50:210
31835991211,0cyclictest1480-21nfsd21:33:340
31835991211,0cyclictest0-21swapper/023:12:180
31835991211,0cyclictest0-21swapper/022:29:470
31835991211,0cyclictest0-21swapper/021:25:470
31835991210,0cyclictest0-21swapper/023:40:330
3183599120,0cyclictest0-21swapper/023:02:320
3183599120,0cyclictest0-21swapper/022:55:130
3183599120,0cyclictest0-21swapper/019:10:130
3183599120,0cyclictest0-21swapper/000:21:470
3183599120,0cyclictest0-21swapper/000:17:420
271120,0ktimersoftd/22036-21sshd21:28:112
112750120,0irq/25-eth022957-21sshd21:22:281
112750120,0irq/25-eth012244-21sshd23:23:393
31838991111,0cyclictest20852-21sshd22:12:483
31838991111,0cyclictest0-21swapper/323:27:163
31838991111,0cyclictest0-21swapper/321:39:413
31838991110,0cyclictest27690-21sshd21:52:353
31838991110,0cyclictest20636-21bash22:21:103
31838991110,0cyclictest0-21swapper/323:15:523
31838991110,0cyclictest0-21swapper/300:38:423
3183899110,0cyclictest0-21swapper/323:50:233
3183899110,0cyclictest0-21swapper/322:45:113
3183899110,0cyclictest0-21swapper/300:05:363
31837991111,0cyclictest0-21swapper/221:43:592
31837991110,0cyclictest15936-21bash21:55:152
31837991110,0cyclictest0-21swapper/223:07:232
31837991110,0cyclictest0-21swapper/222:56:002
31837991110,0cyclictest0-21swapper/222:28:572
31837991110,0cyclictest0-21swapper/222:08:432
31837991110,0cyclictest0-21swapper/220:42:462
3183799110,0cyclictest0-21swapper/223:30:112
3183799110,0cyclictest0-21swapper/222:15:282
3183799110,0cyclictest0-21swapper/219:19:562
3183799110,0cyclictest0-21swapper/219:19:552
3183799110,0cyclictest0-21swapper/200:00:212
31836991111,0cyclictest0-21swapper/122:23:551
31836991111,0cyclictest0-21swapper/121:50:131
31836991110,0cyclictest0-21swapper/123:55:351
31836991110,0cyclictest0-21swapper/122:37:581
31836991110,0cyclictest0-21swapper/121:19:061
31836991110,0cyclictest0-21swapper/121:00:231
3183699110,0cyclictest0-21swapper/121:05:121
3183699110,0cyclictest0-21swapper/120:05:481
3183699110,0cyclictest0-21swapper/119:24:051
31835991111,0cyclictest0-21swapper/021:18:480
3183599111,0cyclictest0-21swapper/022:22:020
31835991110,0cyclictest0-21swapper/022:02:010
31835991110,0cyclictest0-21swapper/000:07:090
3183599110,0cyclictest0-21swapper/021:21:290
191110,0ktimersoftd/10-21swapper/122:55:441
112750110,0irq/25-eth00-21swapper/323:02:323
112750110,0irq/25-eth00-21swapper/020:50:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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