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2026-01-15 - 09:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Thu Jan 15, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650610,0irq/26-eth1-rx-0-21swapper/319:09:213
120650600,0irq/26-eth1-rx-0-21swapper/019:05:280
112750600,0irq/25-eth00-21swapper/119:05:221
112750560,0irq/25-eth00-21swapper/219:05:082
3043699170,0cyclictest0-21swapper/222:40:482
30437991514,0cyclictest0-21swapper/323:15:233
3043799150,0cyclictest0-21swapper/300:15:223
3043599150,0cyclictest0-21swapper/100:11:311
30437991413,0cyclictest0-21swapper/300:29:573
3043799140,0cyclictest0-21swapper/322:03:353
30435991413,0cyclictest0-21swapper/123:06:131
3043599140,0cyclictest0-21swapper/121:40:571
30434991411,0cyclictest0-21swapper/023:26:590
351130,0ktimersoftd/330290-21sshd00:04:103
30437991312,0cyclictest0-21swapper/322:56:273
30437991312,0cyclictest0-21swapper/322:22:183
3043799130,0cyclictest31551-21sshd23:53:073
30436991312,0cyclictest7403-21sshd00:22:332
30436991312,0cyclictest0-21swapper/223:56:532
30436991312,0cyclictest0-21swapper/222:56:012
30436991312,0cyclictest0-21swapper/222:31:502
30436991311,0cyclictest0-21swapper/200:32:542
3043699130,0cyclictest9156-21cut21:35:172
30435991312,0cyclictest0-21swapper/121:24:551
3043599130,0cyclictest0-21swapper/121:11:131
3043599130,0cyclictest0-21swapper/100:00:081
30434991311,0cyclictest0-21swapper/022:58:520
3043499130,0cyclictest25920-21sshd21:32:400
191130,0ktimersoftd/10-21swapper/123:42:001
112750130,0irq/25-eth00-21swapper/122:25:121
41120,0ktimersoftd/00-21swapper/023:42:250
30437991212,0cyclictest0-21swapper/321:26:463
30437991211,0cyclictest9822-21bash21:57:403
30437991211,0cyclictest0-21swapper/323:40:153
30437991211,0cyclictest0-21swapper/321:31:103
30437991210,0cyclictest0-21swapper/322:42:593
30437991210,0cyclictest0-21swapper/321:48:023
30437991210,0cyclictest0-21swapper/321:13:043
3043799120,0cyclictest0-21swapper/322:29:043
3043799120,0cyclictest0-21swapper/321:19:543
30436991212,0cyclictest0-21swapper/222:45:482
30436991211,0cyclictest0-21swapper/222:19:382
30436991210,0cyclictest0-21swapper/221:44:412
3043699120,0cyclictest5505-21bash23:15:102
3043699120,0cyclictest0-21swapper/223:25:512
3043699120,0cyclictest0-21swapper/222:26:382
3043699120,0cyclictest0-21swapper/222:23:082
3043699120,0cyclictest0-21swapper/222:11:112
3043699120,0cyclictest0-21swapper/200:26:442
30435991211,0cyclictest0-21swapper/123:38:041
30435991211,0cyclictest0-21swapper/123:00:591
30435991211,0cyclictest0-21swapper/122:42:171
30435991211,0cyclictest0-21swapper/122:37:051
30435991211,0cyclictest0-21swapper/122:37:041
30435991211,0cyclictest0-21swapper/121:29:351
30435991210,0cyclictest0-21swapper/123:14:571
30435991210,0cyclictest0-21swapper/122:09:251
30435991210,0cyclictest0-21swapper/121:56:171
30435991210,0cyclictest0-21swapper/100:09:181
3043599120,0cyclictest19685-21sshd23:45:201
3043599120,0cyclictest112750irq/25-eth023:50:561
3043599120,0cyclictest0-21swapper/123:24:551
3043599120,0cyclictest0-21swapper/121:18:041
3043599120,0cyclictest0-21swapper/100:32:121
30434991211,0cyclictest22464-21diskmemload23:02:210
30434991211,0cyclictest0-21swapper/022:45:100
30434991211,0cyclictest0-21swapper/021:28:300
30434991210,0cyclictest22464-21diskmemload00:19:430
30434991210,0cyclictest13125-21sshd23:16:170
30434991210,0cyclictest0-21swapper/023:47:050
30434991210,0cyclictest0-21swapper/021:23:500
3043499120,0cyclictest0-21swapper/023:59:580
3043499120,0cyclictest0-21swapper/023:50:480
3043499120,0cyclictest0-21swapper/022:20:450
3043499120,0cyclictest0-21swapper/021:12:200
41110,0ktimersoftd/00-21swapper/021:54:310
30437991111,0cyclictest0-21swapper/323:49:253
30437991111,0cyclictest0-21swapper/323:13:383
30437991111,0cyclictest0-21swapper/300:13:423
3043799110,0cyclictest11568-21sshd23:38:293
3043799110,0cyclictest0-21swapper/323:25:173
3043799110,0cyclictest0-21swapper/321:38:383
3043799110,0cyclictest0-21swapper/320:00:483
3043799110,0cyclictest0-21swapper/319:52:193
30436991111,0cyclictest0-21swapper/223:51:252
30436991111,0cyclictest0-21swapper/223:34:492
30436991111,0cyclictest0-21swapper/200:10:012
30436991110,0cyclictest0-21swapper/221:20:032
30436991110,0cyclictest0-21swapper/221:13:132
3043699110,0cyclictest0-21swapper/200:08:022
3043599119,0cyclictest10594-21bash21:46:391
3043599119,0cyclictest0-21swapper/100:28:011
30435991110,0cyclictest22464-21diskmemload23:32:361
30435991110,0cyclictest15012-21sshd22:04:121
30435991110,0cyclictest0-21swapper/122:16:091
30435991110,0cyclictest0-21swapper/121:35:161
30435991110,0cyclictest0-21swapper/120:33:561
3043599110,0cyclictest0-21swapper/119:12:571
3043499119,0cyclictest0-21swapper/019:32:540
30434991111,0cyclictest0-21swapper/022:17:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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