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2026-05-20 - 16:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed May 20, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/307:05:133
112750580,0irq/25-eth00-21swapper/107:07:051
120650450,0irq/26-eth1-rx-0-21swapper/207:09:432
120650450,0irq/26-eth1-rx-0-21swapper/007:06:240
799399211,0cyclictest22961-21sshd10:03:320
799399180,0cyclictest32312-21diskmemload12:23:490
799399170,0cyclictest0-21swapper/011:35:160
799599160,0cyclictest0-21swapper/209:05:162
799599160,0cyclictest0-21swapper/208:30:132
7996991514,0cyclictest112750irq/25-eth011:33:033
799499151,0cyclictest0-21swapper/110:33:071
7996991411,0cyclictest0-21swapper/311:26:323
799699141,0cyclictest0-21swapper/308:30:113
799699140,0cyclictest22334-21sshd11:45:153
7995991411,0cyclictest0-21swapper/211:57:152
799499141,0cyclictest0-21swapper/111:00:101
799399140,0cyclictest0-21swapper/011:02:220
799399140,0cyclictest0-21swapper/009:05:120
112750140,0irq/25-eth00-21swapper/110:02:541
7996991312,0cyclictest18203-21sshd11:53:153
7996991312,0cyclictest0-21swapper/312:08:153
7996991312,0cyclictest0-21swapper/310:14:453
7996991312,0cyclictest0-21swapper/309:49:193
7996991311,0cyclictest0-21swapper/307:55:143
799699130,0cyclictest0-21swapper/312:00:203
799699130,0cyclictest0-21swapper/310:32:183
799699130,0cyclictest0-21swapper/309:05:173
7995991312,0cyclictest0-21swapper/209:51:192
7995991311,0cyclictest0-21swapper/212:21:452
7995991311,0cyclictest0-21swapper/211:52:352
7995991311,0cyclictest0-21swapper/211:35:312
7995991311,0cyclictest0-21swapper/211:00:182
799599130,0cyclictest22995-21bash11:19:562
7994991312,0cyclictest17147-21sshd10:57:521
351130,0ktimersoftd/30-21swapper/310:38:413
112750130,0irq/25-eth00-21swapper/212:13:162
7996991211,0cyclictest3363-21sshd10:26:233
7996991211,0cyclictest0-21swapper/311:42:563
7996991211,0cyclictest0-21swapper/311:01:273
799699121,0cyclictest112750irq/25-eth010:40:203
7996991210,0cyclictest9021-21sshd12:17:323
7996991210,0cyclictest21600-21sshd12:10:353
7996991210,0cyclictest0-21swapper/311:12:503
7996991210,0cyclictest0-21swapper/311:07:093
7996991210,0cyclictest0-21swapper/309:43:443
799699120,0cyclictest0-21swapper/312:39:443
799699120,0cyclictest0-21swapper/311:38:303
799699120,0cyclictest0-21swapper/310:50:193
799699120,0cyclictest0-21swapper/309:15:163
7995991211,0cyclictest25229-21sshd10:03:512
7995991211,0cyclictest0-21swapper/210:47:532
7995991211,0cyclictest0-21swapper/209:58:102
7995991211,0cyclictest0-21swapper/209:35:512
7995991211,0cyclictest0-21swapper/209:12:442
7995991210,0cyclictest0-21swapper/212:06:322
7995991210,0cyclictest0-21swapper/211:08:202
7995991210,0cyclictest0-21swapper/210:10:492
799599120,0cyclictest5080-21sshd09:48:312
799599120,0cyclictest0-21swapper/212:38:152
799599120,0cyclictest0-21swapper/212:19:252
799599120,0cyclictest0-21swapper/212:01:532
799599120,0cyclictest0-21swapper/211:10:392
7994991212,0cyclictest0-21swapper/107:35:151
7994991211,0cyclictest6996-21sshd09:40:161
7994991211,0cyclictest30648-21id11:59:121
7994991211,0cyclictest1479-21nfsd11:41:121
7994991211,0cyclictest1441-21sshd09:14:211
7994991211,0cyclictest10682-21sshd12:17:471
7994991211,0cyclictest0-21swapper/112:24:451
7994991211,0cyclictest0-21swapper/112:06:091
7994991211,0cyclictest0-21swapper/111:23:111
7994991211,0cyclictest0-21swapper/109:45:491
799499120,0cyclictest10612-21sshd10:18:561
799499120,0cyclictest0-21swapper/109:29:201
799499120,0cyclictest0-21swapper/109:17:091
7993991212,0cyclictest0-21swapper/008:35:190
7993991211,0cyclictest0-21swapper/012:33:050
7993991211,0cyclictest0-21swapper/009:23:380
7993991210,0cyclictest0-21swapper/010:47:380
799399120,0cyclictest0-21swapper/011:05:440
41120,0ktimersoftd/04341-21sshd10:05:160
41120,0ktimersoftd/00-21swapper/010:18:350
112750120,0irq/25-eth032312-21diskmemload10:26:011
112750120,0irq/25-eth024754-21sshd11:11:300
112750120,0irq/25-eth01931-21sshd12:20:483
112750120,0irq/25-eth00-21swapper/312:25:063
112750120,0irq/25-eth00-21swapper/112:27:251
112750120,0irq/25-eth00-21swapper/010:40:010
7996991111,0cyclictest0-21swapper/310:58:063
7996991111,0cyclictest0-21swapper/309:56:243
7996991111,0cyclictest0-21swapper/309:28:463
799699110,0cyclictest0-21swapper/310:24:023
799699110,0cyclictest0-21swapper/310:01:033
799599115,0cyclictest0-21swapper/208:48:512
799599115,0cyclictest0-21swapper/208:20:232
799599115,0cyclictest0-21swapper/208:14:062
799599115,0cyclictest0-21swapper/207:52:492
799599115,0cyclictest0-21swapper/207:33:572
799599115,0cyclictest0-21swapper/207:27:072
799599113,0cyclictest0-21swapper/208:57:532
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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