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2026-01-18 - 04:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Jan 18, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750660,0irq/25-eth00-21swapper/119:09:251
120650640,0irq/26-eth1-rx-0-21swapper/319:09:253
112750570,0irq/25-eth00-21swapper/219:07:062
240824621,0sleep00-21swapper/019:06:450
351180,0ktimersoftd/39642-21sshd21:51:543
274499150,0cyclictest0-21swapper/322:10:203
274199150,0cyclictest0-21swapper/022:10:160
274499140,0cyclictest0-21swapper/300:15:123
2743991411,0cyclictest0-21swapper/222:15:222
274399140,0cyclictest0-21swapper/200:15:132
2742991412,0cyclictest0-21swapper/100:33:271
274299140,0cyclictest0-21swapper/123:50:141
2741991413,0cyclictest19707-21rm22:16:020
274199141,0cyclictest0-21swapper/021:10:370
2744991312,0cyclictest12630-21sshd22:31:383
2744991312,0cyclictest0-21swapper/323:07:533
2744991312,0cyclictest0-21swapper/321:35:193
274499130,0cyclictest25471-21diskmemload23:03:153
274499130,0cyclictest1384-21sshd00:27:283
274499130,0cyclictest0-21swapper/323:10:203
274499130,0cyclictest0-21swapper/322:17:423
274499130,0cyclictest0-21swapper/321:46:143
2743991312,0cyclictest30643-21sshd22:57:112
2743991312,0cyclictest0-21swapper/222:29:472
2743991312,0cyclictest0-21swapper/222:05:362
2743991311,0cyclictest1539-21sshd21:37:372
2742991312,0cyclictest0-21swapper/123:47:331
2742991312,0cyclictest0-21swapper/122:02:191
2742991312,0cyclictest0-21swapper/120:05:131
2742991311,0cyclictest0-21swapper/123:02:441
2741991312,0cyclictest18200-21bash22:55:100
2741991312,0cyclictest0-21swapper/023:09:210
2741991311,0cyclictest0-21swapper/023:47:190
2741991311,0cyclictest0-21swapper/021:30:010
274199130,0cyclictest0-21swapper/022:52:580
112750130,0irq/25-eth00-21swapper/122:36:561
2744991211,0cyclictest5942-21sshd22:58:363
2744991211,0cyclictest30782-21cp21:21:563
2744991211,0cyclictest29270-21bash21:27:173
2744991211,0cyclictest19419-21bash23:34:433
2744991211,0cyclictest14680-21sshd00:35:433
2744991211,0cyclictest0-21swapper/322:45:083
2744991210,0cyclictest0-21swapper/322:27:143
2744991210,0cyclictest0-21swapper/300:21:533
2743991212,0cyclictest0-21swapper/221:29:232
2743991211,0cyclictest9360-21bash22:03:112
2743991211,0cyclictest20133-21sshd23:57:072
2743991211,0cyclictest14615-21sshd00:35:422
2743991210,0cyclictest0-21swapper/223:26:002
2743991210,0cyclictest0-21swapper/223:23:332
274399120,0cyclictest16240-21sshd00:30:072
274399120,0cyclictest0-21swapper/222:12:562
274399120,0cyclictest0-21swapper/221:24:012
2742991211,0cyclictest0-21swapper/122:51:141
2742991210,0cyclictest4707-21sshd21:28:451
2742991210,0cyclictest0-21swapper/123:22:001
2742991210,0cyclictest0-21swapper/122:42:101
274299120,0cyclictest0-21swapper/123:58:011
274299120,0cyclictest0-21swapper/123:42:271
274299120,0cyclictest0-21swapper/123:27:071
274299120,0cyclictest0-21swapper/121:12:281
2741991211,0cyclictest6919-21sshd22:08:220
2741991211,0cyclictest25471-21diskmemload21:38:160
2741991211,0cyclictest0-21swapper/021:46:450
2741991211,0cyclictest0-21swapper/021:43:510
274199121,0cyclictest0-21swapper/023:00:160
2741991210,0cyclictest0-21swapper/022:39:150
2741991210,0cyclictest0-21swapper/000:39:160
2741991210,0cyclictest0-21swapper/000:22:180
274199120,0cyclictest434-21bash23:36:530
274199120,0cyclictest0-21swapper/023:50:000
274199120,0cyclictest0-21swapper/000:33:410
112750120,0irq/25-eth08412-21sshd22:36:313
2744991110,0cyclictest14537-21bash21:19:163
2744991110,0cyclictest0-21swapper/323:57:503
2744991110,0cyclictest0-21swapper/323:47:373
2744991110,0cyclictest0-21swapper/323:24:443
2744991110,0cyclictest0-21swapper/321:58:253
274499110,0cyclictest0-21swapper/319:42:583
2743991111,0cyclictest0-21swapper/223:49:212
2743991111,0cyclictest0-21swapper/223:01:502
2743991111,0cyclictest0-21swapper/222:50:202
2743991110,0cyclictest25471-21diskmemload00:24:182
2743991110,0cyclictest0-21swapper/221:45:512
2743991110,0cyclictest0-21swapper/200:27:132
274399110,0cyclictest1640-21sshd21:56:052
274399110,0cyclictest0-21swapper/223:36:142
274399110,0cyclictest0-21swapper/223:11:222
274399110,0cyclictest0-21swapper/222:43:282
274399110,0cyclictest0-21swapper/221:00:202
274399110,0cyclictest0-21swapper/219:19:162
2742991111,0cyclictest25471-21diskmemload00:24:581
2742991111,0cyclictest0-21swapper/121:55:131
2742991111,0cyclictest0-21swapper/121:18:031
2742991111,0cyclictest0-21swapper/120:59:561
2742991111,0cyclictest0-21swapper/120:47:371
2742991111,0cyclictest0-21swapper/119:54:111
2742991111,0cyclictest0-21swapper/119:16:121
2742991111,0cyclictest0-21swapper/100:03:081
2742991110,0cyclictest0-21swapper/100:16:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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