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2026-04-04 - 20:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Apr 04, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/307:07:353
120650650,0irq/26-eth1-rx-0-21swapper/107:05:351
112750620,0irq/25-eth041ktimersoftd/007:05:340
120650440,0irq/26-eth1-rx-0-21swapper/207:09:322
271180,0ktimersoftd/225601-21sshd10:50:522
24453991514,0cyclictest0-21swapper/310:32:203
2445299150,0cyclictest0-21swapper/207:40:162
24450991514,0cyclictest16349-21diskmemload11:55:200
2445099150,0cyclictest26111-21sshd09:25:220
2445099150,0cyclictest0-21swapper/010:48:470
271140,0ktimersoftd/20-21swapper/209:50:342
24453991413,0cyclictest0-21swapper/309:18:413
2445299140,0cyclictest0-21swapper/211:46:092
2445299140,0cyclictest0-21swapper/211:15:222
24451991414,0cyclictest112750irq/25-eth009:22:331
24450991413,0cyclictest0-21swapper/012:09:040
24450991413,0cyclictest0-21swapper/010:57:090
41130,0ktimersoftd/00-21swapper/009:14:060
24453991312,0cyclictest0-21swapper/312:37:063
24453991312,0cyclictest0-21swapper/312:04:423
24453991312,0cyclictest0-21swapper/310:57:123
24453991312,0cyclictest0-21swapper/309:39:503
24453991311,0cyclictest0-21swapper/311:36:283
2445399130,0cyclictest31791-21sshd09:30:533
24452991312,0cyclictest28953-21sshd10:22:442
24452991312,0cyclictest0-21swapper/209:58:062
2445299130,0cyclictest16349-21diskmemload10:56:512
2445299130,0cyclictest0-21swapper/212:27:032
2445299130,0cyclictest0-21swapper/209:25:192
24451991312,0cyclictest0-21swapper/111:18:141
2445199130,0cyclictest0-21swapper/110:09:141
2445199130,0cyclictest0-21swapper/109:40:261
24450991312,0cyclictest32160-21sshd09:50:000
2445099130,0cyclictest0-21swapper/012:22:460
2445099130,0cyclictest0-21swapper/011:14:340
2445099130,0cyclictest0-21swapper/009:57:330
2445099130,0cyclictest0-21swapper/009:44:180
2445099130,0cyclictest0-21swapper/009:22:280
2445099130,0cyclictest0-21swapper/007:40:190
24453991211,0cyclictest14304-21sshd09:47:163
24453991211,0cyclictest0-21swapper/312:29:543
24453991211,0cyclictest0-21swapper/312:11:253
24453991211,0cyclictest0-21swapper/310:54:253
24453991211,0cyclictest0-21swapper/309:10:053
24453991211,0cyclictest0-21swapper/307:28:053
24453991210,0cyclictest0-21swapper/311:33:123
24453991210,0cyclictest0-21swapper/311:25:123
24453991210,0cyclictest0-21swapper/311:25:113
2445399120,0cyclictest0-21swapper/312:33:373
2445399120,0cyclictest0-21swapper/311:08:363
2445399120,0cyclictest0-21swapper/311:04:173
2445399120,0cyclictest0-21swapper/310:16:113
24452991212,0cyclictest0-21swapper/209:43:362
24452991211,0cyclictest0-21swapper/212:34:012
24452991211,0cyclictest0-21swapper/212:23:332
24452991210,0cyclictest0-21swapper/210:26:002
24452991210,0cyclictest0-21swapper/210:13:272
24452991210,0cyclictest0-21swapper/209:49:172
2445299120,0cyclictest13386-21sshd12:01:232
2445299120,0cyclictest0-21swapper/211:21:162
2445299120,0cyclictest0-21swapper/211:00:432
2445299120,0cyclictest0-21swapper/209:17:172
24451991211,0cyclictest25995-21sshd12:12:571
24451991211,0cyclictest16349-21diskmemload12:00:591
24451991211,0cyclictest0-21swapper/111:23:011
24451991210,0cyclictest16429-21sshd11:42:321
24451991210,0cyclictest0-21swapper/110:34:271
2445199120,0cyclictest22291-21bash10:55:141
2445199120,0cyclictest16349-21diskmemload12:35:221
2445199120,0cyclictest0-21swapper/110:10:451
24450991212,0cyclictest0-21swapper/012:36:410
24450991210,0cyclictest13672-21bash09:18:580
24450991210,0cyclictest0-21swapper/011:43:370
2445099120,0cyclictest6038-21sshd11:07:150
2445099120,0cyclictest0-21swapper/010:14:100
112750120,0irq/25-eth00-21swapper/112:15:451
112750120,0irq/25-eth00-21swapper/111:45:251
41110,0ktimersoftd/026290-21sshd12:32:180
41110,0ktimersoftd/00-21swapper/011:28:200
41110,0ktimersoftd/00-21swapper/011:28:200
351110,0ktimersoftd/30-21swapper/310:11:533
271110,0ktimersoftd/20-21swapper/207:30:212
2445399119,0cyclictest0-21swapper/307:50:093
2445399119,0cyclictest0-21swapper/307:39:213
24453991111,0cyclictest0-21swapper/311:57:573
24453991111,0cyclictest0-21swapper/308:00:443
24453991110,0cyclictest9950irq/24-0000:00:10:06:123
2445399110,0cyclictest2469-21sshd10:47:333
2445399110,0cyclictest0-21swapper/308:42:203
2445399110,0cyclictest0-21swapper/307:46:343
24452991111,0cyclictest0-21swapper/211:05:022
24452991111,0cyclictest0-21swapper/208:34:562
24452991110,0cyclictest0-21swapper/212:11:352
24452991110,0cyclictest0-21swapper/211:57:532
2445299110,0cyclictest0-21swapper/211:51:092
2445299110,0cyclictest0-21swapper/211:43:502
2445299110,0cyclictest0-21swapper/209:11:312
2445299110,0cyclictest0-21swapper/207:27:262
24451991111,0cyclictest21463-21sshd10:21:331
24451991111,0cyclictest0-21swapper/110:46:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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