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2026-01-18 - 19:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Jan 18, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750640,0irq/25-eth00-21swapper/107:05:191
112750580,0irq/25-eth00-21swapper/307:06:113
112750560,0irq/25-eth00-21swapper/207:05:322
112750420,0irq/25-eth00-21swapper/007:08:080
1249999211,0cyclictest24100-21sshd09:58:110
1250299160,0cyclictest0-21swapper/307:25:193
12499991410,0cyclictest0-21swapper/009:38:300
12502991312,0cyclictest0-21swapper/312:14:253
12502991312,0cyclictest0-21swapper/310:53:143
12502991312,0cyclictest0-21swapper/310:38:223
1250299131,0cyclictest0-21swapper/307:50:093
1250299130,0cyclictest0-21swapper/312:26:383
12501991312,0cyclictest0-21swapper/210:20:122
12500991312,0cyclictest0-21swapper/111:22:241
12500991312,0cyclictest0-21swapper/109:52:281
12500991311,0cyclictest0-21swapper/108:45:211
1250099130,0cyclictest0-21swapper/111:07:041
12499991312,0cyclictest31820-21diskmemload09:51:160
12499991312,0cyclictest0-21swapper/009:44:590
1249999130,0cyclictest0-21swapper/011:18:100
1249999130,0cyclictest0-21swapper/010:40:180
12502991212,0cyclictest0-21swapper/311:16:563
12502991212,0cyclictest0-21swapper/309:38:103
12502991212,0cyclictest0-21swapper/309:31:543
12502991212,0cyclictest0-21swapper/309:31:543
12502991210,0cyclictest3506-21id09:10:253
12502991210,0cyclictest0-21swapper/312:21:443
12502991210,0cyclictest0-21swapper/311:54:063
1250299120,0cyclictest15398-21sshd10:57:383
1250299120,0cyclictest0-21swapper/311:49:403
1250299120,0cyclictest0-21swapper/310:09:193
12501991211,0cyclictest22939-21bash11:37:542
12501991211,0cyclictest0-21swapper/212:35:032
12501991211,0cyclictest0-21swapper/212:13:062
12501991210,0cyclictest15779-21bash10:52:082
12500991212,0cyclictest0-21swapper/112:36:371
12500991211,0cyclictest5269-21sshd11:01:221
12500991211,0cyclictest0-21swapper/112:17:071
12500991211,0cyclictest0-21swapper/112:07:361
1250099120,0cyclictest0-21swapper/111:45:031
1250099120,0cyclictest0-21swapper/110:40:131
12499991212,0cyclictest0-21swapper/011:31:460
12499991211,0cyclictest0-21swapper/011:35:420
12499991211,0cyclictest0-21swapper/011:29:460
12499991211,0cyclictest0-21swapper/010:32:510
12499991210,0cyclictest0-21swapper/010:49:490
12499991210,0cyclictest0-21swapper/009:16:460
1249999120,0cyclictest0-21swapper/011:14:130
1249999120,0cyclictest0-21swapper/010:19:370
1249999120,0cyclictest0-21swapper/009:10:160
112750120,0irq/25-eth06865-21munin-run12:20:000
112750120,0irq/25-eth00-21swapper/110:23:591
41110,0ktimersoftd/00-21swapper/011:44:280
41110,0ktimersoftd/00-21swapper/011:06:230
351110,0ktimersoftd/30-21swapper/309:59:333
271110,0ktimersoftd/20-21swapper/211:06:222
12502991111,0cyclictest0-21swapper/311:05:323
12502991110,0cyclictest7839-21sshd10:34:173
12502991110,0cyclictest0-21swapper/311:42:503
12502991110,0cyclictest0-21swapper/311:24:353
12502991110,0cyclictest0-21swapper/309:41:193
12501991110,0cyclictest31820-21diskmemload09:25:012
12501991110,0cyclictest13310-21sshd10:57:152
1250199110,0cyclictest22310-21sshd09:52:182
1250199110,0cyclictest0-21swapper/210:40:122
1250199110,0cyclictest0-21swapper/210:25:142
1250099119,0cyclictest0-21swapper/108:35:071
12500991111,0cyclictest0-21swapper/112:34:121
12500991111,0cyclictest0-21swapper/112:14:401
12500991111,0cyclictest0-21swapper/110:56:571
12500991110,0cyclictest4083-21sshd10:33:371
12500991110,0cyclictest0-21swapper/112:29:181
12500991110,0cyclictest0-21swapper/111:12:451
12500991110,0cyclictest0-21swapper/109:45:061
12500991110,0cyclictest0-21swapper/109:37:021
12500991110,0cyclictest0-21swapper/109:24:291
1250099110,0cyclictest0-21swapper/110:37:471
1249999119,0cyclictest0-21swapper/008:55:510
12499991111,0cyclictest0-21swapper/007:10:500
12499991110,0cyclictest32683-21sshd12:01:540
12499991110,0cyclictest0-21swapper/012:05:050
12499991110,0cyclictest0-21swapper/009:28:510
12499991110,0cyclictest0-21swapper/008:15:150
12499991110,0cyclictest0-21swapper/007:52:190
1249999110,0cyclictest0-21swapper/012:26:490
1249999110,0cyclictest0-21swapper/010:52:010
1249999110,0cyclictest0-21swapper/007:45:130
1249999110,0cyclictest0-21swapper/007:21:380
112750110,0irq/25-eth030485-21sshd10:10:150
112750110,0irq/25-eth00-21swapper/212:05:552
112750110,0irq/25-eth00-21swapper/010:22:200
41100,0ktimersoftd/013039-21df08:25:110
41100,0ktimersoftd/00-21swapper/008:04:520
271100,0ktimersoftd/20-21swapper/209:42:232
1250299109,0cyclictest0-21swapper/311:38:243
1250299109,0cyclictest0-21swapper/309:49:273
1250299109,0cyclictest0-21swapper/308:08:433
1250299108,0cyclictest0-21swapper/308:44:163
12502991010,0cyclictest0-21swapper/312:16:523
12502991010,0cyclictest0-21swapper/311:56:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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