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2026-03-04 - 23:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed Mar 04, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750680,0irq/25-eth00-21swapper/107:05:261
112750680,0irq/25-eth00-21swapper/107:05:251
112750660,0irq/25-eth00-21swapper/307:05:113
112750660,0irq/25-eth00-21swapper/307:05:103
1773524720,0sleep00-21swapper/007:07:310
1773524720,0sleep00-21swapper/007:07:310
112750430,0irq/25-eth00-21swapper/207:06:022
112750430,0irq/25-eth00-21swapper/207:06:012
1801099200,0cyclictest0-21swapper/211:16:132
1800999190,0cyclictest8221-21id09:44:061
1800999170,0cyclictest0-21swapper/109:12:541
1800999162,0cyclictest22271-21bash10:40:221
18011991512,0cyclictest0-21swapper/307:50:173
18009991514,0cyclictest0-21swapper/111:44:231
18008991514,0cyclictest0-21swapper/012:30:280
18008991511,0cyclictest0-21swapper/012:03:440
1800899150,0cyclictest0-21swapper/012:17:270
18011991413,0cyclictest15915-21sshd10:14:553
1801199140,0cyclictest2400-21sshd10:52:183
1801199140,0cyclictest0-21swapper/312:09:413
18009991411,0cyclictest31711-21bash09:47:381
18009991411,0cyclictest0-21swapper/111:14:031
18008991412,0cyclictest1479-21nfsd11:59:340
1800899140,0cyclictest0-21swapper/007:15:190
18011991312,0cyclictest28876-21bash12:35:423
18011991312,0cyclictest2680-21sshd10:22:423
18011991312,0cyclictest13421-21sshd12:18:313
18011991312,0cyclictest0-21swapper/309:10:473
18011991311,0cyclictest3596-21sshd12:11:533
1801199130,0cyclictest3100-21sshd11:56:533
1801199130,0cyclictest0-21swapper/307:25:193
18010991313,0cyclictest112750irq/25-eth011:59:322
18010991312,0cyclictest16892-21sshd11:14:282
18010991311,0cyclictest0-21swapper/210:09:522
18009991312,0cyclictest0-21swapper/112:18:321
18009991312,0cyclictest0-21swapper/109:32:251
18009991311,0cyclictest0-21swapper/110:46:521
18009991311,0cyclictest0-21swapper/110:29:351
1800999130,0cyclictest28715-21sshd09:17:391
18008991312,0cyclictest9921-21diskmemload09:39:200
18008991312,0cyclictest0-21swapper/011:12:440
1800899130,0cyclictest0-21swapper/010:14:250
112750130,0irq/25-eth08947-21rm11:37:580
1801199128,0cyclictest31460-21bash09:18:063
18011991211,0cyclictest27550-21sshd09:42:013
18011991211,0cyclictest0-21swapper/310:36:033
18011991210,0cyclictest10546-21sshd12:03:043
18011991210,0cyclictest0-21swapper/312:22:543
1801199120,0cyclictest0-21swapper/309:53:043
18010991211,0cyclictest30099-21bash09:57:142
18010991211,0cyclictest0-21swapper/210:26:582
18010991210,0cyclictest0-21swapper/212:03:442
1801099120,0cyclictest0-21swapper/211:46:592
1801099120,0cyclictest0-21swapper/210:31:292
1801099120,0cyclictest0-21swapper/210:00:222
1801099120,0cyclictest0-21swapper/209:32:492
1801099120,0cyclictest0-21swapper/209:26:052
1801099120,0cyclictest0-21swapper/209:16:192
18009991210,0cyclictest17302-21sshd12:14:061
18009991210,0cyclictest0-21swapper/110:56:521
18009991210,0cyclictest0-21swapper/110:31:041
1800999120,0cyclictest0-21swapper/111:52:311
1800999120,0cyclictest0-21swapper/111:36:571
1800999120,0cyclictest0-21swapper/110:37:081
18008991211,0cyclictest9921-21diskmemload10:52:040
18008991211,0cyclictest7398-21sshd09:53:530
18008991211,0cyclictest15268-21sshd11:09:160
18008991211,0cyclictest0-21swapper/011:00:330
18008991210,0cyclictest0-21swapper/012:12:480
1800899120,0cyclictest0-21swapper/011:47:000
1800899120,0cyclictest0-21swapper/010:05:150
1800899120,0cyclictest0-21swapper/009:29:080
112750120,0irq/25-eth00-21swapper/112:37:341
41110,0ktimersoftd/00-21swapper/012:20:500
41110,0ktimersoftd/00-21swapper/009:20:240
351110,0ktimersoftd/30-21swapper/311:04:103
271110,0ktimersoftd/224597-21wc11:50:152
18011991111,0cyclictest0-21swapper/310:55:333
18011991110,0cyclictest29909-21bash11:31:123
18011991110,0cyclictest12093-21bash09:59:323
18011991110,0cyclictest0-21swapper/312:31:313
18011991110,0cyclictest0-21swapper/311:50:313
18011991110,0cyclictest0-21swapper/311:44:343
18011991110,0cyclictest0-21swapper/311:26:143
18011991110,0cyclictest0-21swapper/310:05:223
18011991110,0cyclictest0-21swapper/309:31:483
18011991110,0cyclictest0-21swapper/309:20:193
1801199110,0cyclictest0-21swapper/308:23:233
1801099119,0cyclictest0-21swapper/207:32:342
18010991111,0cyclictest0-21swapper/212:36:362
18010991111,0cyclictest0-21swapper/212:08:082
18010991110,0cyclictest9891-21sshd11:23:182
18010991110,0cyclictest7248-21bash09:24:172
18010991110,0cyclictest6086-21bash10:23:132
18010991110,0cyclictest28358-21bash11:30:572
18010991110,0cyclictest18413-21bash11:04:482
18010991110,0cyclictest0-21swapper/210:55:312
18010991110,0cyclictest0-21swapper/210:47:182
18010991110,0cyclictest0-21swapper/209:50:532
18010991110,0cyclictest0-21swapper/209:43:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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