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2026-02-25 - 02:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Tue Feb 24, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650650,0irq/26-eth1-rx-0-21swapper/107:07:231
112750640,0irq/25-eth00-21swapper/307:07:223
112750550,0irq/25-eth00-21swapper/207:09:112
112750460,0irq/25-eth00-21swapper/007:07:040
151899180,0cyclictest13414-21sshd10:50:392
1519991512,0cyclictest0-21swapper/310:13:183
1518991514,0cyclictest0-21swapper/212:31:182
151899150,0cyclictest0-21swapper/209:20:132
151799150,0cyclictest0-21swapper/107:35:131
1519991414,0cyclictest112750irq/25-eth012:35:303
1519991413,0cyclictest32470-21sshd11:57:243
1519991412,0cyclictest0-21swapper/311:26:153
151999140,0cyclictest5880-21sshd10:15:163
151999140,0cyclictest0-21swapper/311:18:353
151899140,0cyclictest0-21swapper/212:13:462
151899140,0cyclictest0-21swapper/210:43:022
1517991413,0cyclictest0-21swapper/109:11:181
1517991411,0cyclictest0-21swapper/111:15:151
1516991413,0cyclictest0-21swapper/012:37:450
1516991412,0cyclictest0-21swapper/011:12:290
1516991411,0cyclictest0-21swapper/009:39:460
151699140,0cyclictest0-21swapper/010:37:470
1519991312,0cyclictest0-21swapper/311:37:243
1519991312,0cyclictest0-21swapper/309:39:093
1519991310,0cyclictest7646-21sshd11:24:183
151999130,0cyclictest0-21swapper/311:32:123
151999130,0cyclictest0-21swapper/310:32:223
151999130,0cyclictest0-21swapper/310:32:213
151999130,0cyclictest0-21swapper/307:35:183
1518991312,0cyclictest0-21swapper/212:15:162
151899130,0cyclictest0-21swapper/210:35:572
1517991312,0cyclictest3574-21sshd11:43:141
1517991312,0cyclictest0-21swapper/111:39:461
1517991312,0cyclictest0-21swapper/109:24:121
1517991310,0cyclictest17471-21diskstats11:50:131
151799130,0cyclictest0-21swapper/109:31:451
1516991312,0cyclictest8293-21bash11:04:480
1516991311,0cyclictest0-21swapper/009:29:460
1516991310,0cyclictest0-21swapper/011:42:400
151699130,0cyclictest0-21swapper/009:14:270
112750130,0irq/25-eth00-21swapper/311:09:113
112750130,0irq/25-eth00-21swapper/110:32:231
112750130,0irq/25-eth00-21swapper/110:32:231
41120,0ktimersoftd/00-21swapper/012:26:010
351120,0ktimersoftd/31936-21sshd09:15:553
1519991212,0cyclictest0-21swapper/309:46:283
1519991211,0cyclictest25634-21bash09:44:023
1519991211,0cyclictest0-21swapper/312:30:443
1519991211,0cyclictest0-21swapper/311:51:073
1519991211,0cyclictest0-21swapper/310:46:043
1519991211,0cyclictest0-21swapper/310:20:383
1519991210,0cyclictest0-21swapper/310:39:133
151999120,0cyclictest0-21swapper/312:16:263
151999120,0cyclictest0-21swapper/312:02:093
151999120,0cyclictest0-21swapper/311:45:053
151999120,0cyclictest0-21swapper/309:20:183
1518991211,0cyclictest0-21swapper/212:09:002
1518991211,0cyclictest0-21swapper/210:21:472
1518991211,0cyclictest0-21swapper/207:20:122
1518991210,0cyclictest25324-21sshd10:47:412
1518991210,0cyclictest0-21swapper/210:59:122
1518991210,0cyclictest0-21swapper/209:19:242
151899120,0cyclictest0-21swapper/212:25:022
151899120,0cyclictest0-21swapper/211:52:582
151899120,0cyclictest0-21swapper/210:06:552
151899120,0cyclictest0-21swapper/210:02:022
151899120,0cyclictest0-21swapper/209:11:362
1517991211,0cyclictest0-21swapper/110:27:511
1517991211,0cyclictest0-21swapper/110:18:201
1517991210,0cyclictest23513-21sshd12:20:321
1517991210,0cyclictest0-21swapper/110:58:101
1517991210,0cyclictest0-21swapper/109:19:051
151799120,0cyclictest14352-21sshd12:09:301
151799120,0cyclictest0-21swapper/112:31:481
151799120,0cyclictest0-21swapper/111:58:131
151799120,0cyclictest0-21swapper/111:46:441
1516991211,0cyclictest0-21swapper/012:32:580
1516991211,0cyclictest0-21swapper/010:14:230
1516991210,0cyclictest0-21swapper/011:57:390
1516991210,0cyclictest0-21swapper/010:57:080
1516991210,0cyclictest0-21swapper/010:09:300
1516991210,0cyclictest0-21swapper/009:52:120
151699120,0cyclictest0-21swapper/011:47:540
151699120,0cyclictest0-21swapper/010:21:560
112750120,0irq/25-eth025507-21bash09:19:390
112750120,0irq/25-eth024923-21sshd09:34:103
112750120,0irq/25-eth019943-21missed_timers12:05:163
41110,0ktimersoftd/00-21swapper/012:16:150
41110,0ktimersoftd/00-21swapper/009:31:170
1519991111,0cyclictest0-21swapper/312:11:423
1519991111,0cyclictest0-21swapper/308:00:183
1519991110,0cyclictest30518-21wget08:10:103
1519991110,0cyclictest0-21swapper/311:03:153
1519991110,0cyclictest0-21swapper/310:29:553
151999110,0cyclictest0-21swapper/312:21:133
151999110,0cyclictest0-21swapper/310:08:263
151999110,0cyclictest0-21swapper/308:20:303
1518991111,0cyclictest0-21swapper/211:12:322
1518991111,0cyclictest0-21swapper/209:47:102
1518991110,0cyclictest0-21swapper/210:28:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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