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2022-07-07 - 13:43

x86 Intel Xeon E3-1220L V2 @2300 MHz, Linux 4.4.39-rt50+ (Profile)

Latency plot of system in rack #7, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Thu Jul 07, 2022 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950770,0irq/26-eth1-rx-0-21swapper/319:05:003
110050600,0irq/25-eth00-21swapper/119:05:151
110050550,0irq/25-eth00-21swapper/219:06:542
110050440,0irq/25-eth00-21swapper/019:05:120
9950310,0irq/24-0000:00:0-21swapper/219:10:002
110050280,0irq/25-eth00-21swapper/019:10:010
24547991817,0cyclictest0-21swapper/322:24:283
2454499180,0cyclictest26749-21sshd21:54:460
2454799161,0cyclictest0-21swapper/321:26:013
24546991615,0cyclictest0-21swapper/221:25:122
24547991514,0cyclictest0-21swapper/322:11:273
24546991512,0cyclictest0-21swapper/223:57:372
351140,0ktimersoftd/313845-21bash22:44:203
24546991413,0cyclictest5091-21bash22:32:212
24546991413,0cyclictest0-21swapper/222:41:392
24545991413,0cyclictest26327-21sshd23:03:541
24545991412,0cyclictest32763-21munin-run21:30:001
24544991413,0cyclictest0-21swapper/023:33:260
2454499140,0cyclictest10142-21sshd22:18:170
2454499140,0cyclictest0-21swapper/000:32:550
117950140,0irq/26-eth1-rx-1975-21id22:53:530
110050140,0irq/25-eth09807-21sshd00:24:073
271130,0ktimersoftd/20-21swapper/200:06:542
24547991313,0cyclictest0-21swapper/320:07:383
24547991312,0cyclictest0-21swapper/323:39:363
24547991312,0cyclictest0-21swapper/300:12:163
24547991312,0cyclictest0-21swapper/300:03:263
24547991311,0cyclictest0-21swapper/322:03:403
24547991311,0cyclictest0-21swapper/322:03:403
24546991312,0cyclictest16184-21diskmemload22:37:352
24546991312,0cyclictest12545-21sshd21:20:202
24546991312,0cyclictest0-21swapper/223:31:352
24546991312,0cyclictest0-21swapper/222:48:372
24546991312,0cyclictest0-21swapper/221:14:522
24546991312,0cyclictest0-21swapper/200:35:212
24546991311,0cyclictest0-21swapper/222:50:202
2454699130,0cyclictest0-21swapper/220:45:132
2454699130,0cyclictest0-21swapper/200:26:462
24545991312,0cyclictest0-21swapper/123:43:441
24545991312,0cyclictest0-21swapper/121:36:311
24545991311,0cyclictest0-21swapper/123:29:481
2454599130,0cyclictest0-21swapper/123:31:451
24544991312,0cyclictest6914-21bash00:00:100
24544991312,0cyclictest24610-21sshd21:36:140
24544991312,0cyclictest0-21swapper/023:06:160
110050130,0irq/25-eth031027-21sshd22:09:461
9950120,0irq/24-0000:00:5859-21sshd23:52:300
271120,0ktimersoftd/20-21swapper/222:12:432
24547991211,0cyclictest14406-21bash22:25:573
24547991210,0cyclictest0-21swapper/300:18:253
2454799120,0cyclictest0-21swapper/321:21:093
2454799120,0cyclictest0-21swapper/321:15:423
2454799120,0cyclictest0-21swapper/321:05:003
2454799120,0cyclictest0-21swapper/300:34:133
2454799120,0cyclictest0-21swapper/300:09:013
24546991211,0cyclictest5930-21munin-node23:05:132
24546991211,0cyclictest2356-21bash21:51:542
24546991211,0cyclictest0-21swapper/221:30:392
24546991211,0cyclictest0-21swapper/200:17:152
24546991211,0cyclictest0-21swapper/200:01:542
24546991210,0cyclictest0-21swapper/223:04:392
24545991211,0cyclictest0-21swapper/121:42:001
2454599120,0cyclictest0-21swapper/123:59:251
2454599120,0cyclictest0-21swapper/121:58:231
2454599120,0cyclictest0-21swapper/121:58:221
2454599120,0cyclictest0-21swapper/121:21:181
2454599120,0cyclictest0-21swapper/100:38:551
2454599120,0cyclictest0-21swapper/100:10:341
24544991211,0cyclictest8096-21sshd21:12:380
24544991211,0cyclictest0-21swapper/021:47:440
24544991211,0cyclictest0-21swapper/019:25:180
24544991210,0cyclictest3524-21sshd23:41:130
24544991210,0cyclictest15892-21munin-run19:59:590
2454499120,0cyclictest0-21swapper/023:36:410
2454499120,0cyclictest0-21swapper/021:42:150
110050120,0irq/25-eth00-21swapper/323:12:263
110050120,0irq/25-eth00-21swapper/321:56:143
110050120,0irq/25-eth00-21swapper/321:56:133
110050120,0irq/25-eth00-21swapper/022:45:500
41110,0ktimersoftd/00-21swapper/023:45:520
41110,0ktimersoftd/00-21swapper/020:18:580
41110,0ktimersoftd/00-21swapper/019:16:500
41110,0ktimersoftd/00-21swapper/000:05:020
351110,0ktimersoftd/321981-21sshd22:52:273
351110,0ktimersoftd/30-21swapper/322:32:433
271110,0ktimersoftd/20-21swapper/221:57:092
271110,0ktimersoftd/20-21swapper/221:57:092
24547991111,0cyclictest0-21swapper/323:59:283
24547991111,0cyclictest0-21swapper/323:42:323
24547991111,0cyclictest0-21swapper/321:10:133
2454799110,0cyclictest25894-21sshd21:36:223
2454799110,0cyclictest0-21swapper/323:28:143
2454799110,0cyclictest0-21swapper/321:46:433
2454799110,0cyclictest0-21swapper/321:41:493
24546991111,0cyclictest0-21swapper/221:41:352
24546991111,0cyclictest0-21swapper/220:55:202
24546991110,0cyclictest0-21swapper/223:49:362
24545991111,0cyclictest16184-21diskmemload00:34:301
24545991110,0cyclictest1512-21sshd23:52:051
24545991110,0cyclictest1512-21sshd22:39:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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