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2026-02-28 - 18:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Feb 28, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750660,0irq/25-eth00-21swapper/307:08:173
112750600,0irq/25-eth00-21swapper/107:05:061
120650460,0irq/26-eth1-rx-0-21swapper/007:05:250
120650440,0irq/26-eth1-rx-0-21swapper/207:07:232
24310991813,0cyclictest7899-21sshd09:33:232
2431099150,0cyclictest0-21swapper/208:10:102
24308991514,0cyclictest16330-21diskmemload10:43:510
2430899150,0cyclictest0-21swapper/010:59:590
112750150,0irq/25-eth00-21swapper/311:58:293
24310991413,0cyclictest0-21swapper/212:15:332
24310991413,0cyclictest0-21swapper/209:16:112
24309991413,0cyclictest22478-21sshd12:39:241
24309991413,0cyclictest0-21swapper/109:55:351
24309991413,0cyclictest0-21swapper/109:27:221
41130,0ktimersoftd/00-21swapper/011:41:410
24311991312,0cyclictest0-21swapper/312:33:553
24311991312,0cyclictest0-21swapper/311:43:373
24311991312,0cyclictest0-21swapper/310:33:343
24311991310,0cyclictest0-21swapper/310:35:473
2431199130,0cyclictest7655-21sshd11:47:213
2431199130,0cyclictest0-21swapper/309:42:073
24310991310,0cyclictest0-21swapper/211:40:352
2431099130,0cyclictest0-21swapper/211:55:132
24309991312,0cyclictest22181-21sshd12:34:241
24309991312,0cyclictest0-21swapper/112:18:081
24309991312,0cyclictest0-21swapper/110:41:431
2430999130,0cyclictest25351-21sshd09:45:501
2430999130,0cyclictest0-21swapper/111:31:111
24308991312,0cyclictest3948-21sshd12:21:320
2430899130,0cyclictest0-21swapper/011:59:280
112750130,0irq/25-eth00-21swapper/010:28:070
112750130,0irq/25-eth00-21swapper/010:08:250
41120,0ktimersoftd/010969-21sshd10:18:290
24311991212,0cyclictest0-21swapper/310:56:493
24311991212,0cyclictest0-21swapper/310:05:493
24311991210,0cyclictest0-21swapper/309:20:303
2431199120,0cyclictest0-21swapper/312:38:563
2431199120,0cyclictest0-21swapper/310:53:193
2431199120,0cyclictest0-21swapper/310:40:123
2431199120,0cyclictest0-21swapper/310:12:263
2431199120,0cyclictest0-21swapper/309:46:593
2431199120,0cyclictest0-21swapper/309:34:343
2431199120,0cyclictest0-21swapper/309:14:563
24310991212,0cyclictest0-21swapper/210:16:082
24310991211,0cyclictest28393-21kworker/2:112:26:502
24310991211,0cyclictest1105-21sshd10:11:572
24310991211,0cyclictest0-21swapper/212:31:482
24310991210,0cyclictest0-21swapper/208:05:552
2431099120,0cyclictest16461-21sshd11:03:592
2431099120,0cyclictest0-21swapper/209:45:322
2431099120,0cyclictest0-21swapper/209:22:002
24309991212,0cyclictest0-21swapper/109:38:171
24309991211,0cyclictest191ktimersoftd/111:41:531
24309991211,0cyclictest16330-21diskmemload10:52:511
24309991211,0cyclictest0-21swapper/110:19:531
24309991210,0cyclictest0-21swapper/110:32:531
2430999120,0cyclictest0-21swapper/110:37:181
2430999120,0cyclictest0-21swapper/109:30:161
2430999120,0cyclictest0-21swapper/109:21:471
24308991211,0cyclictest0-21swapper/009:59:420
24308991210,0cyclictest0-21swapper/009:32:240
2430899120,0cyclictest0-21swapper/010:52:470
2430899120,0cyclictest0-21swapper/009:21:010
112750120,0irq/25-eth029831-21sshd11:45:400
112750120,0irq/25-eth00-21swapper/011:52:410
112750120,0irq/25-eth00-21swapper/009:35:070
351110,0ktimersoftd/30-21swapper/308:18:293
351110,0ktimersoftd/30-21swapper/307:40:023
271110,0ktimersoftd/20-21swapper/211:45:072
24311991111,0cyclictest27680-21sshd11:05:313
24311991111,0cyclictest0-21swapper/312:27:263
24311991111,0cyclictest0-21swapper/312:14:393
24311991111,0cyclictest0-21swapper/312:00:363
24311991111,0cyclictest0-21swapper/311:31:113
24311991111,0cyclictest0-21swapper/311:15:443
24311991111,0cyclictest0-21swapper/310:22:463
24311991111,0cyclictest0-21swapper/310:01:113
24311991111,0cyclictest0-21swapper/309:54:193
24311991111,0cyclictest0-21swapper/307:18:463
24311991110,0cyclictest0-21swapper/310:29:103
24311991110,0cyclictest0-21swapper/309:56:313
2431199110,0cyclictest0-21swapper/310:18:353
2431199110,0cyclictest0-21swapper/307:30:303
2431099119,0cyclictest0-21swapper/209:10:232
24310991111,0cyclictest0-21swapper/211:26:242
24310991111,0cyclictest0-21swapper/210:20:192
24310991111,0cyclictest0-21swapper/209:53:352
24310991110,0cyclictest0-21swapper/211:53:292
24310991110,0cyclictest0-21swapper/211:33:222
24310991110,0cyclictest0-21swapper/211:10:122
24310991110,0cyclictest0-21swapper/209:27:352
2431099110,0cyclictest25354-21sshd10:00:412
2431099110,0cyclictest0-21swapper/210:53:182
2431099110,0cyclictest0-21swapper/208:26:282
2431099110,0cyclictest0-21swapper/208:18:342
2431099110,0cyclictest0-21swapper/207:56:232
2431099110,0cyclictest0-21swapper/207:35:012
2430999119,0cyclictest16330-21diskmemload11:10:181
24309991111,0cyclictest0-21swapper/112:02:201
24309991111,0cyclictest0-21swapper/110:02:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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