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2026-06-08 - 18:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Mon Jun 08, 2026 12:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650600,0irq/26-eth1-rx-0-21swapper/107:05:151
120650590,0irq/26-eth1-rx-0-21swapper/307:06:033
120650460,0irq/26-eth1-rx-0-21swapper/207:06:432
120650450,0irq/26-eth1-rx-0-21swapper/007:09:280
41190,0ktimersoftd/025001-21sshd10:37:010
41190,0ktimersoftd/025001-21sshd10:37:000
17336991918,0cyclictest0-21swapper/309:39:193
17333991612,0cyclictest0-21swapper/009:38:580
17334991510,0cyclictest0-21swapper/109:23:401
1733499150,0cyclictest0-21swapper/107:45:141
17336991411,0cyclictest0-21swapper/310:43:273
17336991411,0cyclictest0-21swapper/310:43:273
1733499140,0cyclictest7124-21sshd12:14:461
1733499140,0cyclictest4045-21sshd12:34:241
1733399141,0cyclictest0-21swapper/010:08:420
1733399140,0cyclictest0-21swapper/011:15:200
351130,0ktimersoftd/30-21swapper/312:20:193
17336991312,0cyclictest0-21swapper/310:31:433
17336991312,0cyclictest0-21swapper/310:31:433
1733699130,0cyclictest0-21swapper/311:23:283
17335991312,0cyclictest0-21swapper/211:12:172
1733599130,0cyclictest0-21swapper/212:02:142
17334991312,0cyclictest0-21swapper/111:47:221
17334991312,0cyclictest0-21swapper/109:11:351
17334991311,0cyclictest0-21swapper/109:53:311
1733499130,0cyclictest0-21swapper/112:02:151
1733499130,0cyclictest0-21swapper/110:32:541
1733499130,0cyclictest0-21swapper/110:32:541
17333991312,0cyclictest0-21swapper/010:23:410
112750130,0irq/25-eth05443-21sshd11:39:133
112750130,0irq/25-eth012956-21diskstats10:50:131
112750130,0irq/25-eth00-21swapper/311:15:023
112750130,0irq/25-eth00-21swapper/311:04:423
351120,0ktimersoftd/30-21swapper/311:50:353
17336991211,0cyclictest0-21swapper/311:55:563
17336991211,0cyclictest0-21swapper/310:54:573
17336991211,0cyclictest0-21swapper/310:27:393
17336991211,0cyclictest0-21swapper/310:23:353
17336991210,0cyclictest0-21swapper/309:44:403
1733699120,0cyclictest9808-21sshd12:25:133
1733699120,0cyclictest0-21swapper/311:46:113
1733699120,0cyclictest0-21swapper/310:56:133
1733699120,0cyclictest0-21swapper/310:15:273
1733699120,0cyclictest0-21swapper/310:00:423
17335991211,0cyclictest5162-21sshd10:09:042
17335991211,0cyclictest26892-21bash11:17:232
17335991211,0cyclictest23171-21sshd10:46:432
17335991211,0cyclictest0-21swapper/211:38:392
17335991211,0cyclictest0-21swapper/211:21:132
17335991210,0cyclictest18324-21sshd11:46:042
17335991210,0cyclictest0-21swapper/211:32:292
17335991210,0cyclictest0-21swapper/209:50:152
1733599120,0cyclictest0-21swapper/212:19:532
17334991211,0cyclictest0-21swapper/111:21:271
17334991211,0cyclictest0-21swapper/111:16:211
1733499120,0cyclictest9450-21sshd10:49:451
1733499120,0cyclictest0-21swapper/112:36:451
1733499120,0cyclictest0-21swapper/111:25:181
1733499120,0cyclictest0-21swapper/110:11:041
1733499120,0cyclictest0-21swapper/109:48:111
17333991212,0cyclictest0-21swapper/012:06:440
17333991211,0cyclictest9244-21diskmemload10:43:470
17333991211,0cyclictest9244-21diskmemload10:43:470
17333991210,0cyclictest0-21swapper/012:35:180
17333991210,0cyclictest0-21swapper/011:36:590
1733399120,0cyclictest0-21swapper/012:23:550
1733399120,0cyclictest0-21swapper/010:12:460
1733399120,0cyclictest0-21swapper/009:40:270
1733399120,0cyclictest0-21swapper/009:31:270
112750120,0irq/25-eth023787-21sshd11:46:570
112750120,0irq/25-eth020920-21sshd11:41:280
112750120,0irq/25-eth00-21swapper/011:52:060
41110,0ktimersoftd/010744-21rm09:59:550
41110,0ktimersoftd/00-21swapper/009:18:370
271110,0ktimersoftd/20-21swapper/211:53:522
17336991111,0cyclictest0-21swapper/309:18:253
17336991110,0cyclictest31100-21sshd10:48:013
17336991110,0cyclictest22779-21sshd09:56:383
17336991110,0cyclictest20509-21sshd09:51:173
17336991110,0cyclictest20086-21sshd09:26:233
1733699110,0cyclictest0-21swapper/312:03:233
1733699110,0cyclictest0-21swapper/311:30:153
1733699110,0cyclictest0-21swapper/310:11:233
1733699110,0cyclictest0-21swapper/308:20:053
17335991110,0cyclictest29657-21sshd12:38:202
17335991110,0cyclictest27725-21sshd10:32:252
17335991110,0cyclictest27725-21sshd10:32:252
17335991110,0cyclictest26940-21sshd10:22:212
17335991110,0cyclictest23339-21sshd12:22:132
17335991110,0cyclictest16541-21sshd09:55:362
17335991110,0cyclictest0-21swapper/211:25:032
17335991110,0cyclictest0-21swapper/210:26:522
17335991110,0cyclictest0-21swapper/210:15:472
17335991110,0cyclictest0-21swapper/209:12:092
1733599110,0cyclictest9244-21diskmemload09:44:552
17334991110,0cyclictest29819-21sshd09:42:501
17334991110,0cyclictest11625-21sshd11:30:101
1733499110,0cyclictest9244-21diskmemload09:29:421
1733499110,0cyclictest0-21swapper/108:20:151
1733499110,0cyclictest0-21swapper/107:35:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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