You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-20 - 01:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Thu Feb 19, 2026 12:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/107:06:151
112750660,0irq/25-eth00-21swapper/307:05:113
120650550,0irq/26-eth1-rx-0-21swapper/207:05:132
1308724121,0sleep00-21swapper/007:09:230
1320599150,0cyclictest5231-21diskmemload09:39:512
13206991413,0cyclictest0-21swapper/311:42:333
1320699140,0cyclictest20516-21sshd12:18:483
1320599149,0cyclictest0-21swapper/209:46:422
13205991413,0cyclictest0-21swapper/211:59:432
1320599140,0cyclictest0-21swapper/209:10:172
1320499140,0cyclictest0-21swapper/112:27:111
1320499140,0cyclictest0-21swapper/112:23:141
1320399140,0cyclictest0-21swapper/009:17:390
112750140,0irq/25-eth029358-21cp12:14:443
351130,0ktimersoftd/30-21swapper/311:04:553
13206991312,0cyclictest0-21swapper/312:38:333
13206991312,0cyclictest0-21swapper/310:45:593
13206991310,0cyclictest0-21swapper/311:16:393
1320699130,0cyclictest0-21swapper/310:28:123
13205991312,0cyclictest0-21swapper/210:49:552
1320599130,0cyclictest0-21swapper/210:40:022
1320599130,0cyclictest0-21swapper/210:40:022
1320599130,0cyclictest0-21swapper/210:10:522
13204991312,0cyclictest18011-21sshd11:04:491
13204991312,0cyclictest0-21swapper/111:22:361
13204991311,0cyclictest0-21swapper/111:32:421
1320499131,0cyclictest5231-21diskmemload10:45:461
13203991312,0cyclictest416-21sshd11:35:250
13203991312,0cyclictest0-21swapper/010:55:420
13203991312,0cyclictest0-21swapper/009:39:560
13203991311,0cyclictest0-21swapper/011:11:160
13203991310,0cyclictest0-21swapper/012:09:560
13203991310,0cyclictest0-21swapper/010:42:060
13203991310,0cyclictest0-21swapper/010:42:060
1320399130,0cyclictest5231-21diskmemload12:24:130
41120,0ktimersoftd/00-21swapper/009:25:110
191120,0ktimersoftd/10-21swapper/111:50:291
191120,0ktimersoftd/10-21swapper/111:38:231
13206991212,0cyclictest0-21swapper/311:14:403
13206991211,0cyclictest0-21swapper/311:58:353
13206991211,0cyclictest0-21swapper/311:38:363
13206991211,0cyclictest0-21swapper/311:20:363
13206991210,0cyclictest0-21swapper/311:26:313
13206991210,0cyclictest0-21swapper/309:16:043
1320699120,0cyclictest5231-21diskmemload09:52:193
1320699120,0cyclictest0-21swapper/310:53:393
1320699120,0cyclictest0-21swapper/310:53:393
13205991211,0cyclictest0-21swapper/212:30:022
13205991211,0cyclictest0-21swapper/211:35:202
13205991210,0cyclictest31667-21sshd10:55:362
13205991210,0cyclictest0-21swapper/210:08:542
13205991210,0cyclictest0-21swapper/207:10:142
1320599120,0cyclictest0-21swapper/212:28:052
1320599120,0cyclictest0-21swapper/212:20:102
1320599120,0cyclictest0-21swapper/211:41:292
1320599120,0cyclictest0-21swapper/210:15:122
13204991211,0cyclictest24652-21sshd09:24:271
13204991211,0cyclictest0-21swapper/111:40:501
13204991211,0cyclictest0-21swapper/110:37:381
13204991211,0cyclictest0-21swapper/109:49:121
13204991210,0cyclictest11621-21bash10:12:401
13204991210,0cyclictest0-21swapper/109:14:551
1320499120,0cyclictest8237-21bash12:39:161
1320499120,0cyclictest0-21swapper/111:10:451
1320499120,0cyclictest0-21swapper/110:50:141
1320499120,0cyclictest0-21swapper/110:50:141
13203991211,0cyclictest0-21swapper/010:50:000
13203991211,0cyclictest0-21swapper/010:03:180
13203991210,0cyclictest5231-21diskmemload12:01:470
13203991210,0cyclictest5231-21diskmemload11:41:360
13203991210,0cyclictest5231-21diskmemload10:18:240
13203991210,0cyclictest0-21swapper/012:26:110
1320399120,0cyclictest0-21swapper/011:09:170
1320399120,0cyclictest0-21swapper/009:51:400
112750120,0irq/25-eth020659-21sshd10:31:052
112750120,0irq/25-eth014768-21bash12:12:020
112750120,0irq/25-eth00-21swapper/111:46:241
351110,0ktimersoftd/324359-21bash12:30:323
351110,0ktimersoftd/30-21swapper/310:16:423
271110,0ktimersoftd/20-21swapper/210:21:362
13206991111,0cyclictest0-21swapper/312:06:433
13206991111,0cyclictest0-21swapper/309:13:233
13206991111,0cyclictest0-21swapper/307:10:223
13206991110,0cyclictest0-21swapper/310:07:253
1320699110,0cyclictest21979-21sshd12:24:433
1320699110,0cyclictest0-21swapper/310:13:053
1320699110,0cyclictest0-21swapper/307:55:473
13205991111,0cyclictest0-21swapper/212:05:532
13205991111,0cyclictest0-21swapper/211:25:142
13205991111,0cyclictest0-21swapper/210:03:132
13205991111,0cyclictest0-21swapper/207:57:032
13205991110,0cyclictest0-21swapper/211:15:092
13205991110,0cyclictest0-21swapper/209:56:272
13205991110,0cyclictest0-21swapper/207:51:352
1320599110,0cyclictest0-21swapper/210:26:032
1320599110,0cyclictest0-21swapper/208:07:452
13204991111,0cyclictest0-21swapper/110:57:091
13204991111,0cyclictest0-21swapper/110:27:461
13204991111,0cyclictest0-21swapper/110:06:581
13204991111,0cyclictest0-21swapper/109:17:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional