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2026-02-28 - 05:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Feb 28, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650690,0irq/26-eth1-rx-0-21swapper/119:09:131
112750580,0irq/25-eth00-21swapper/319:08:213
112750560,0irq/25-eth00-21swapper/219:07:562
120650490,0irq/26-eth1-rx-0-21swapper/019:05:580
159199180,0cyclictest481-21jbd2/dm-0-823:21:131
159399160,0cyclictest0-21swapper/321:55:473
1592991512,0cyclictest26028-21diskmemload22:07:112
159199150,0cyclictest0-21swapper/100:35:161
159099150,0cyclictest0-21swapper/022:29:410
1593991413,0cyclictest0-21swapper/323:29:463
1593991413,0cyclictest0-21swapper/322:25:383
159399140,0cyclictest0-21swapper/322:38:183
159299140,0cyclictest0-21swapper/223:29:202
159099149,0cyclictest0-21swapper/000:04:420
1590991412,0cyclictest14189-21sshd00:24:480
1590991411,0cyclictest0-21swapper/022:31:250
1593991312,0cyclictest0-21swapper/321:44:583
1592991312,0cyclictest0-21swapper/223:33:522
159299130,0cyclictest29823-21sshd22:28:352
159299130,0cyclictest0-21swapper/222:24:312
1591991313,0cyclictest0-21swapper/122:19:581
1591991312,0cyclictest30388-21sshd22:58:101
1591991312,0cyclictest0-21swapper/121:40:201
159199130,0cyclictest0-21swapper/122:33:261
159199130,0cyclictest0-21swapper/121:33:571
1590991312,0cyclictest0-21swapper/021:36:010
159099131,0cyclictest26028-21diskmemload21:12:220
159099130,0cyclictest2600-21unixbench_multi21:40:190
159099130,0cyclictest0-21swapper/021:22:320
351120,0ktimersoftd/30-21swapper/323:19:183
1593991211,0cyclictest9329-21sshd23:14:463
1593991211,0cyclictest1921-21sshd00:08:003
1593991211,0cyclictest0-21swapper/323:31:163
1593991211,0cyclictest0-21swapper/323:07:203
1593991211,0cyclictest0-21swapper/321:38:363
1593991211,0cyclictest0-21swapper/319:30:353
1593991211,0cyclictest0-21swapper/300:26:343
1593991210,0cyclictest0-21swapper/322:58:103
1593991210,0cyclictest0-21swapper/300:37:503
1593991210,0cyclictest0-21swapper/300:03:413
159399120,0cyclictest0-21swapper/323:45:193
159399120,0cyclictest0-21swapper/322:31:063
1592991212,0cyclictest0-21swapper/221:32:062
1592991211,0cyclictest0-21swapper/221:38:452
1592991210,0cyclictest0-21swapper/221:29:542
159299120,0cyclictest0-21swapper/223:49:532
159299120,0cyclictest0-21swapper/223:00:592
159299120,0cyclictest0-21swapper/222:51:492
159299120,0cyclictest0-21swapper/222:37:102
159299120,0cyclictest0-21swapper/200:17:042
1591991212,0cyclictest26028-21diskmemload00:14:161
1591991211,0cyclictest0-21swapper/123:48:491
1591991211,0cyclictest0-21swapper/123:11:041
1591991211,0cyclictest0-21swapper/122:14:301
1591991211,0cyclictest0-21swapper/100:27:021
1591991210,0cyclictest0-21swapper/123:52:051
1591991210,0cyclictest0-21swapper/123:33:011
159199120,0cyclictest32066-21sshd22:43:451
159199120,0cyclictest0-21swapper/123:55:201
159199120,0cyclictest0-21swapper/122:04:101
159199120,0cyclictest0-21swapper/100:08:271
159199120,0cyclictest0-21swapper/100:02:391
159099123,0cyclictest0-21swapper/020:10:160
1590991211,0cyclictest30744-21runrttasks22:38:380
1590991211,0cyclictest0-21swapper/023:09:530
1590991210,0cyclictest26028-21diskmemload22:58:430
1590991210,0cyclictest0-21swapper/020:35:160
159099120,0cyclictest8-21rcu_preempt22:14:490
159099120,0cyclictest41ktimersoftd/023:49:360
159099120,0cyclictest32745-21sshd00:07:440
159099120,0cyclictest0-21swapper/022:53:160
159099120,0cyclictest0-21swapper/022:00:040
191110,0ktimersoftd/10-21swapper/121:12:001
1593991111,0cyclictest0-21swapper/321:11:113
1593991111,0cyclictest0-21swapper/319:15:213
1593991111,0cyclictest0-21swapper/319:15:213
1593991110,0cyclictest17176-21sshd22:51:123
1593991110,0cyclictest1359-21sshd23:03:373
1593991110,0cyclictest0-21swapper/323:50:053
1593991110,0cyclictest0-21swapper/323:39:033
1593991110,0cyclictest0-21swapper/322:40:033
1593991110,0cyclictest0-21swapper/320:35:233
159399110,0cyclictest0-21swapper/323:22:133
159399110,0cyclictest0-21swapper/322:14:433
159399110,0cyclictest0-21swapper/320:45:163
159399110,0cyclictest0-21swapper/319:39:173
1592991111,0cyclictest0-21swapper/223:56:242
1592991111,0cyclictest0-21swapper/223:43:232
1592991111,0cyclictest0-21swapper/222:31:432
1592991111,0cyclictest0-21swapper/200:31:362
1592991111,0cyclictest0-21swapper/200:00:422
1592991110,0cyclictest0-21swapper/222:57:162
159299110,0cyclictest3729-21sshd21:16:122
159299110,0cyclictest0-21swapper/223:08:242
159299110,0cyclictest0-21swapper/222:17:042
159299110,0cyclictest0-21swapper/200:35:192
159299110,0cyclictest0-21swapper/200:08:012
159199119,0cyclictest0-21swapper/120:08:481
159199113,0cyclictest0-21swapper/119:30:141
1591991111,0cyclictest0-21swapper/123:07:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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