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2026-08-08 - 22:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Aug 08, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650700,0irq/26-eth1-rx-0-21swapper/307:06:113
120650700,0irq/26-eth1-rx-0-21swapper/307:06:113
9950640,0irq/24-0000:00:0-21swapper/007:05:240
9950640,0irq/24-0000:00:0-21swapper/007:05:240
120650630,0irq/26-eth1-rx-0-21swapper/107:06:591
120650630,0irq/26-eth1-rx-0-21swapper/107:06:591
112750550,0irq/25-eth00-21swapper/207:09:552
112750550,0irq/25-eth00-21swapper/207:09:552
351180,0ktimersoftd/322956-21sshd10:21:473
271180,0ktimersoftd/222955-21sshd10:21:472
1862799160,0cyclictest0-21swapper/210:50:162
18626991615,0cyclictest0-21swapper/110:17:571
18626991612,0cyclictest16871-21hddtemp_smartct12:25:151
1862699160,0cyclictest0-21swapper/110:23:371
18626991513,0cyclictest0-21swapper/111:21:431
18626991512,0cyclictest10531-21diskmemload09:37:031
18626991512,0cyclictest0-21swapper/109:15:471
18625991512,0cyclictest2512-21sshd10:27:300
18628991413,0cyclictest21840-21sshd12:25:503
18628991411,0cyclictest0-21swapper/311:30:183
1862899140,0cyclictest0-21swapper/310:50:233
18627991412,0cyclictest0-21swapper/211:01:412
18625991412,0cyclictest10531-21diskmemload09:34:450
9950130,0irq/24-0000:00:0-21swapper/011:43:530
18628991312,0cyclictest0-21swapper/312:05:093
18628991312,0cyclictest0-21swapper/311:37:513
18628991312,0cyclictest0-21swapper/310:47:193
18628991311,0cyclictest0-21swapper/310:10:093
18628991310,0cyclictest0-21swapper/309:16:003
1862899130,0cyclictest0-21swapper/310:57:463
1862899130,0cyclictest0-21swapper/310:40:143
18627991312,0cyclictest29241-21bash12:01:582
18627991312,0cyclictest13713-21sshd09:47:342
18627991312,0cyclictest0-21swapper/212:37:522
18627991312,0cyclictest0-21swapper/209:50:072
1862799130,0cyclictest22641-21sshd10:09:242
1862799130,0cyclictest0-21swapper/209:43:432
1862699130,0cyclictest10412-21sshd09:55:191
1862699130,0cyclictest0-21swapper/112:18:171
18625991311,0cyclictest0-21swapper/011:01:380
9950120,0irq/24-0000:00:0-21swapper/210:30:462
41120,0ktimersoftd/00-21swapper/009:23:150
351120,0ktimersoftd/30-21swapper/310:02:153
18628991212,0cyclictest112750irq/25-eth009:34:433
18628991211,0cyclictest27798-21sshd12:01:473
18628991211,0cyclictest2382-21rm10:19:153
18628991211,0cyclictest0-21swapper/312:38:303
18628991211,0cyclictest0-21swapper/310:27:003
18628991211,0cyclictest0-21swapper/309:27:173
18627991211,0cyclictest0-21swapper/212:30:542
1862799120,0cyclictest0-21swapper/211:05:242
18626991212,0cyclictest0-21swapper/111:32:381
18626991211,0cyclictest4907-21sshd10:40:151
18626991211,0cyclictest2701-21sshd10:31:391
18626991211,0cyclictest13924-21sshd09:14:311
18626991211,0cyclictest0-21swapper/112:09:001
18626991210,0cyclictest0-21swapper/112:13:381
1862699120,0cyclictest0-21swapper/112:30:571
1862699120,0cyclictest0-21swapper/111:05:191
1862699120,0cyclictest0-21swapper/111:02:111
1862699120,0cyclictest0-21swapper/108:30:151
18625991211,0cyclictest10531-21diskmemload11:19:050
18625991210,0cyclictest0-21swapper/010:09:230
1862599120,0cyclictest0-21swapper/012:35:310
1862599120,0cyclictest0-21swapper/011:52:040
1862599120,0cyclictest0-21swapper/011:26:510
1862599120,0cyclictest0-21swapper/010:04:580
112750120,0irq/25-eth00-21swapper/312:31:183
112750120,0irq/25-eth00-21swapper/311:11:223
112750120,0irq/25-eth00-21swapper/109:26:361
41110,0ktimersoftd/00-21swapper/010:40:310
41110,0ktimersoftd/00-21swapper/010:34:140
351110,0ktimersoftd/322292-21sshd10:34:133
351110,0ktimersoftd/30-21swapper/311:40:533
351110,0ktimersoftd/30-21swapper/309:20:473
18628991111,0cyclictest0-21swapper/312:23:053
18628991111,0cyclictest0-21swapper/311:20:253
18628991110,0cyclictest112750irq/25-eth011:51:163
18628991110,0cyclictest0-21swapper/312:13:093
18628991110,0cyclictest0-21swapper/309:14:443
1862899110,0cyclictest0-21swapper/311:55:203
1862899110,0cyclictest0-21swapper/311:05:223
1862899110,0cyclictest0-21swapper/308:59:253
1862899110,0cyclictest0-21swapper/308:35:423
1862899110,0cyclictest0-21swapper/308:24:123
1862899110,0cyclictest0-21swapper/307:27:593
18627991111,0cyclictest0-21swapper/211:53:092
18627991111,0cyclictest0-21swapper/211:33:242
18627991111,0cyclictest0-21swapper/209:36:042
18627991110,0cyclictest0-21swapper/212:28:342
18627991110,0cyclictest0-21swapper/212:05:202
18627991110,0cyclictest0-21swapper/209:03:042
1862799110,0cyclictest12006-21sshd11:43:162
1862799110,0cyclictest0-21swapper/209:10:592
1862799110,0cyclictest0-21swapper/207:26:462
18626991111,0cyclictest0-21swapper/111:39:071
18626991111,0cyclictest0-21swapper/109:53:401
18626991110,0cyclictest25585-21sshd11:11:501
18626991110,0cyclictest24940-21sshd10:01:201
18626991110,0cyclictest0-21swapper/111:55:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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