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2026-06-21 - 10:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Jun 21, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650580,0irq/26-eth1-rx-0-21swapper/319:07:153
120650580,0irq/26-eth1-rx-0-21swapper/119:07:131
120650460,0irq/26-eth1-rx-0-21swapper/019:06:480
120650450,0irq/26-eth1-rx-0-21swapper/219:09:562
488099160,0cyclictest0-21swapper/319:25:203
488099160,0cyclictest0-21swapper/319:25:203
487999160,0cyclictest0-21swapper/222:45:202
487999160,0cyclictest0-21swapper/220:30:132
4877991512,0cyclictest22469-21bash00:08:400
487799150,0cyclictest0-21swapper/020:30:180
112750150,0irq/25-eth029185-21diskmemload00:34:191
4880991413,0cyclictest0-21swapper/322:30:223
4880991413,0cyclictest0-21swapper/322:30:213
4879991413,0cyclictest0-21swapper/200:01:252
4878991413,0cyclictest0-21swapper/121:48:181
120650140,0irq/26-eth1-rx-0-21swapper/219:23:472
4880991312,0cyclictest15089-21bash21:25:063
4880991312,0cyclictest0-21swapper/323:13:423
4880991312,0cyclictest0-21swapper/321:40:243
4880991311,0cyclictest0-21swapper/300:20:083
488099130,0cyclictest0-21swapper/322:45:143
4879991312,0cyclictest0-21swapper/223:18:192
4879991311,0cyclictest0-21swapper/223:58:582
4878991312,0cyclictest0-21swapper/122:22:141
487899130,0cyclictest29185-21diskmemload22:10:171
487899130,0cyclictest0-21swapper/122:53:291
4877991312,0cyclictest0-21swapper/021:35:260
4877991310,0cyclictest17581-21sshd22:37:570
487799130,0cyclictest0-21swapper/000:39:410
112750130,0irq/25-eth029185-21diskmemload21:45:440
112750130,0irq/25-eth016532-21sshd00:37:561
4880991211,0cyclictest0-21swapper/323:05:483
4880991211,0cyclictest0-21swapper/322:23:583
4880991211,0cyclictest0-21swapper/322:06:043
4880991211,0cyclictest0-21swapper/321:16:563
4880991210,0cyclictest0-21swapper/323:27:173
488099120,0cyclictest27483-21sshd23:04:593
488099120,0cyclictest0-21swapper/322:55:483
488099120,0cyclictest0-21swapper/320:30:183
488099120,0cyclictest0-21swapper/300:27:413
4879991212,0cyclictest0-21swapper/200:32:122
4879991211,0cyclictest813-21id23:05:332
4879991211,0cyclictest13502-21sshd22:58:492
4879991210,0cyclictest0-21swapper/222:29:532
4879991210,0cyclictest0-21swapper/221:14:582
487999120,0cyclictest0-21swapper/221:36:482
4878991211,0cyclictest29185-21diskmemload21:22:381
4878991211,0cyclictest27474-21sshd21:26:361
4878991211,0cyclictest26948-21sshd22:30:291
4878991211,0cyclictest26948-21sshd22:30:281
4878991210,0cyclictest7497-21cp23:19:311
4878991210,0cyclictest0-21swapper/122:55:071
487899120,0cyclictest0-21swapper/120:30:151
487899120,0cyclictest0-21swapper/100:10:441
4877991211,0cyclictest0-21swapper/021:29:240
4877991211,0cyclictest0-21swapper/000:27:010
4877991210,0cyclictest0-21swapper/022:28:460
487799120,0cyclictest2253-21sshd23:14:290
487799120,0cyclictest0-21swapper/022:06:070
487799120,0cyclictest0-21swapper/022:00:130
487799120,0cyclictest0-21swapper/021:17:340
487799120,0cyclictest0-21swapper/000:18:390
351120,0ktimersoftd/30-21swapper/322:16:123
271120,0ktimersoftd/20-21swapper/200:17:482
191120,0ktimersoftd/129185-21diskmemload23:37:591
191120,0ktimersoftd/10-21swapper/123:33:541
191120,0ktimersoftd/10-21swapper/100:28:521
112750120,0irq/25-eth024024-21sshd21:21:563
112750120,0irq/25-eth013640-21sshd23:24:370
112750120,0irq/25-eth00-21swapper/123:43:401
112750120,0irq/25-eth00-21swapper/121:50:251
4880991111,0cyclictest0-21swapper/320:48:233
4880991110,0cyclictest27783-21sshd21:56:263
4880991110,0cyclictest0-21swapper/321:11:093
488099110,0cyclictest0-21swapper/323:36:143
488099110,0cyclictest0-21swapper/322:14:063
488099110,0cyclictest0-21swapper/321:36:423
488099110,0cyclictest0-21swapper/300:36:033
4879991111,0cyclictest0-21swapper/221:30:452
4879991111,0cyclictest0-21swapper/219:46:062
4879991111,0cyclictest0-21swapper/219:30:172
4879991111,0cyclictest0-21swapper/219:10:112
4879991111,0cyclictest0-21swapper/200:25:282
4879991110,0cyclictest23018-21sshd21:21:482
4879991110,0cyclictest18172-21sshd21:46:402
4879991110,0cyclictest0-21swapper/221:58:232
4879991110,0cyclictest0-21swapper/221:52:412
487999110,0cyclictest0-21swapper/222:15:162
487999110,0cyclictest0-21swapper/222:11:462
487999110,0cyclictest0-21swapper/220:52:042
487999110,0cyclictest0-21swapper/220:47:042
487999110,0cyclictest0-21swapper/200:24:392
4878991111,0cyclictest0-21swapper/121:36:351
4878991111,0cyclictest0-21swapper/121:31:351
4878991110,0cyclictest9941-21sshd21:15:481
4878991110,0cyclictest22426-21sshd23:04:181
487899110,0cyclictest0-21swapper/120:42:061
487899110,0cyclictest0-21swapper/100:22:211
4877991111,0cyclictest0-21swapper/022:53:370
487799110,0cyclictest0-21swapper/021:50:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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