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2026-01-28 - 22:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed Jan 28, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/307:05:123
120650650,0irq/26-eth1-rx-0-21swapper/107:05:121
1262324321,0sleep20-21swapper/207:06:232
112750380,0irq/25-eth00-21swapper/007:05:150
1298399211,0cyclictest29448-21sshd09:13:340
1298399211,0cyclictest10422-21sshd11:47:110
41180,0ktimersoftd/00-21swapper/012:29:010
351180,0ktimersoftd/326118-21bash12:29:013
271180,0ktimersoftd/20-21swapper/212:29:012
12986991514,0cyclictest0-21swapper/312:06:073
1298399152,0cyclictest30490-21sshd12:00:100
1298699140,0cyclictest22577-21sshd12:13:413
12985991413,0cyclictest21718-21sshd11:29:202
12985991412,0cyclictest0-21swapper/209:15:242
12984991411,0cyclictest0-21swapper/110:49:351
12986991312,0cyclictest2953-21bash10:08:013
12986991312,0cyclictest0-21swapper/311:48:213
12986991312,0cyclictest0-21swapper/309:24:533
12986991310,0cyclictest0-21swapper/312:39:143
1298699130,0cyclictest0-21swapper/311:15:143
1298699130,0cyclictest0-21swapper/310:43:453
12985991312,0cyclictest0-21swapper/211:21:332
12985991312,0cyclictest0-21swapper/210:12:402
12985991312,0cyclictest0-21swapper/209:13:122
12985991311,0cyclictest7717-21sshd09:39:372
12985991311,0cyclictest0-21swapper/210:46:572
12985991310,0cyclictest0-21swapper/212:24:032
1298599130,0cyclictest0-21swapper/207:55:152
12984991312,0cyclictest0-21swapper/112:13:051
12984991312,0cyclictest0-21swapper/111:52:401
12984991312,0cyclictest0-21swapper/110:42:151
12984991312,0cyclictest0-21swapper/110:08:411
12984991312,0cyclictest0-21swapper/109:11:391
12984991312,0cyclictest0-21swapper/108:50:161
12984991311,0cyclictest0-21swapper/111:01:331
12984991310,0cyclictest0-21swapper/112:00:271
1298499130,0cyclictest5003-21diskmemload11:16:241
1298499130,0cyclictest0-21swapper/110:15:181
12983991312,0cyclictest0-21swapper/011:27:090
12983991310,0cyclictest0-21swapper/012:11:240
112750130,0irq/25-eth00-21swapper/011:57:520
12986991211,0cyclictest10919-21sshd10:53:173
12986991211,0cyclictest0-21swapper/311:05:143
12986991210,0cyclictest0-21swapper/311:43:143
12986991210,0cyclictest0-21swapper/310:38:523
12986991210,0cyclictest0-21swapper/309:34:593
1298699120,0cyclictest0-21swapper/311:27:543
1298699120,0cyclictest0-21swapper/310:46:123
12985991211,0cyclictest0-21swapper/211:58:022
12985991211,0cyclictest0-21swapper/209:42:422
12985991211,0cyclictest0-21swapper/209:30:232
12985991210,0cyclictest0-21swapper/212:00:432
1298599120,0cyclictest0-21swapper/212:11:102
1298599120,0cyclictest0-21swapper/211:39:482
1298599120,0cyclictest0-21swapper/210:17:052
1298599120,0cyclictest0-21swapper/209:57:282
1298599120,0cyclictest0-21swapper/209:53:162
12984991211,0cyclictest5412-21bash10:27:581
12984991211,0cyclictest4639-21bash11:26:381
12984991211,0cyclictest0-21swapper/112:38:531
12984991211,0cyclictest0-21swapper/112:31:061
1298499120,0cyclictest0-21swapper/111:44:521
1298499120,0cyclictest0-21swapper/109:37:121
12983991211,0cyclictest0-21swapper/012:06:180
12983991211,0cyclictest0-21swapper/010:37:260
12983991210,0cyclictest5003-21diskmemload10:34:590
12983991210,0cyclictest0-21swapper/010:08:300
1298399120,0cyclictest0-21swapper/009:55:290
112750120,0irq/25-eth00-21swapper/310:20:533
112750120,0irq/25-eth00-21swapper/310:16:203
9950110,0irq/24-0000:00:6945-21sshd12:21:040
351110,0ktimersoftd/30-21swapper/307:50:113
1298699119,0cyclictest0-21swapper/307:28:563
12986991111,0cyclictest19013-21sshd11:53:273
12986991111,0cyclictest0-21swapper/312:21:143
12986991111,0cyclictest0-21swapper/311:22:483
12986991111,0cyclictest0-21swapper/311:12:353
12986991111,0cyclictest0-21swapper/309:49:163
12986991110,0cyclictest0-21swapper/311:55:533
12986991110,0cyclictest0-21swapper/311:02:483
12986991110,0cyclictest0-21swapper/310:25:243
12986991110,0cyclictest0-21swapper/309:59:373
1298699110,0cyclictest0-21swapper/311:38:083
1298699110,0cyclictest0-21swapper/308:11:213
1298699110,0cyclictest0-21swapper/307:55:143
1298599119,0cyclictest0-21swapper/207:22:502
12985991111,0cyclictest0-21swapper/212:08:292
12985991111,0cyclictest0-21swapper/211:16:262
12985991111,0cyclictest0-21swapper/208:36:012
12985991110,0cyclictest0-21swapper/212:37:112
12985991110,0cyclictest0-21swapper/210:44:302
12985991110,0cyclictest0-21swapper/210:06:032
1298599110,0cyclictest11876-21bash12:16:562
1298599110,0cyclictest0-21swapper/209:08:462
1298599110,0cyclictest0-21swapper/208:09:182
12984991111,0cyclictest0-21swapper/111:21:311
12984991111,0cyclictest0-21swapper/110:04:161
12984991111,0cyclictest0-21swapper/107:48:351
12984991110,0cyclictest0-21swapper/111:49:581
12984991110,0cyclictest0-21swapper/109:16:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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