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2026-01-26 - 10:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Mon Jan 26, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750680,0irq/25-eth00-21swapper/319:05:593
112750610,0irq/25-eth00-21swapper/219:05:292
120650570,0irq/26-eth1-rx-0-21swapper/119:05:061
1376224220,0sleep00-21swapper/019:08:500
1392499170,0cyclictest0-21swapper/322:54:113
1392199170,0cyclictest0-21swapper/023:55:170
13924991615,0cyclictest7763-21sshd21:15:053
1392199160,0cyclictest0-21swapper/021:41:500
13923991513,0cyclictest12206-21sshd22:58:402
13921991514,0cyclictest17895-21bash21:26:160
1392199151,0cyclictest0-21swapper/019:10:160
112750150,0irq/25-eth00-21swapper/000:16:480
13924991412,0cyclictest0-21swapper/323:40:533
13924991412,0cyclictest0-21swapper/322:24:123
1392499140,0cyclictest0-21swapper/321:27:323
13923991413,0cyclictest29953-21cp21:33:032
1392399140,0cyclictest0-21swapper/200:12:472
13922991411,0cyclictest0-21swapper/123:34:051
112750140,0irq/25-eth00-21swapper/321:35:263
13924991311,0cyclictest30510-21bash00:20:023
13924991311,0cyclictest0-21swapper/321:49:433
13924991310,0cyclictest5946-21diskmemload23:33:063
13924991310,0cyclictest25798-21rm21:42:093
13924991310,0cyclictest0-21swapper/323:50:523
13924991310,0cyclictest0-21swapper/322:10:513
13924991310,0cyclictest0-21swapper/300:06:263
1392499130,0cyclictest0-21swapper/323:12:103
13923991312,0cyclictest4963-21sshd23:17:092
13923991312,0cyclictest18685-21sshd23:48:442
13923991312,0cyclictest0-21swapper/222:07:052
13923991312,0cyclictest0-21swapper/222:07:052
13923991311,0cyclictest0-21swapper/200:07:132
1392399130,0cyclictest0-21swapper/222:46:002
1392299130,0cyclictest0-21swapper/122:46:281
1392299130,0cyclictest0-21swapper/121:59:311
13921991313,0cyclictest0-21swapper/022:42:210
13921991312,0cyclictest0-21swapper/021:39:090
13921991311,0cyclictest0-21swapper/000:37:560
1392199130,0cyclictest0-21swapper/021:57:380
13924991211,0cyclictest0-21swapper/322:02:513
13924991211,0cyclictest0-21swapper/321:32:233
13924991210,0cyclictest0-21swapper/323:58:393
13924991210,0cyclictest0-21swapper/322:36:253
13924991210,0cyclictest0-21swapper/322:31:323
13924991210,0cyclictest0-21swapper/321:22:243
13924991210,0cyclictest0-21swapper/319:22:383
1392499120,0cyclictest27515-21sshd00:39:123
1392499120,0cyclictest0-21swapper/323:35:453
1392499120,0cyclictest0-21swapper/323:25:193
1392499120,0cyclictest0-21swapper/323:22:393
1392499120,0cyclictest0-21swapper/322:56:373
1392499120,0cyclictest0-21swapper/322:26:393
1392499120,0cyclictest0-21swapper/321:55:033
1392499120,0cyclictest0-21swapper/320:24:543
1392499120,0cyclictest0-21swapper/320:13:393
1392499120,0cyclictest0-21swapper/319:47:373
1392499120,0cyclictest0-21swapper/319:43:053
1392499120,0cyclictest0-21swapper/300:33:213
13923991212,0cyclictest0-21swapper/221:40:362
13923991211,0cyclictest20243-21sshd21:51:042
13923991211,0cyclictest18684-21smartctl22:15:212
13923991211,0cyclictest18684-21smartctl22:15:202
13923991211,0cyclictest0-21swapper/223:14:282
13923991211,0cyclictest0-21swapper/200:37:322
13923991210,0cyclictest0-21swapper/200:18:222
1392399120,0cyclictest0-21swapper/223:43:382
1392399120,0cyclictest0-21swapper/223:09:082
1392399120,0cyclictest0-21swapper/222:12:402
1392399120,0cyclictest0-21swapper/221:24:262
13922991212,0cyclictest0-21swapper/123:26:031
13922991212,0cyclictest0-21swapper/123:20:441
13922991211,0cyclictest0-21swapper/123:04:411
13922991211,0cyclictest0-21swapper/122:33:481
13922991211,0cyclictest0-21swapper/121:38:361
13922991211,0cyclictest0-21swapper/121:33:441
13922991210,0cyclictest0-21swapper/121:46:231
1392299120,0cyclictest0-21swapper/123:18:041
1392299120,0cyclictest0-21swapper/122:15:481
1392299120,0cyclictest0-21swapper/122:15:471
1392299120,0cyclictest0-21swapper/122:02:121
1392299120,0cyclictest0-21swapper/100:32:521
13921991211,0cyclictest5946-21diskmemload00:26:470
13921991211,0cyclictest20394-21bash22:50:070
13921991211,0cyclictest0-21swapper/023:46:010
13921991210,0cyclictest0-21swapper/022:32:220
1392199120,0cyclictest831-21awk19:49:590
1392199120,0cyclictest5946-21diskmemload23:24:520
1392199120,0cyclictest13382-21sshd21:10:550
1392199120,0cyclictest0-21swapper/023:40:540
1392199120,0cyclictest0-21swapper/022:02:580
1392199120,0cyclictest0-21swapper/000:07:230
120650120,0irq/26-eth1-rx-26-21rcuc/223:55:482
112750120,0irq/25-eth05946-21diskmemload21:45:150
1392499119,0cyclictest0-21swapper/320:40:353
13924991111,0cyclictest0-21swapper/322:16:123
13924991111,0cyclictest0-21swapper/322:16:113
13924991111,0cyclictest0-21swapper/322:05:313
13924991111,0cyclictest0-21swapper/322:05:303
13924991110,0cyclictest1480-21nfsd22:45:543
1392499110,0cyclictest16751-21sshd23:48:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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