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2026-04-15 - 11:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed Apr 15, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650610,0irq/26-eth1-rx-0-21swapper/119:09:471
112750600,0irq/25-eth00-21swapper/319:07:413
112750560,0irq/25-eth00-21swapper/219:06:542
9950520,0irq/24-0000:00:0-21swapper/019:05:260
271180,0ktimersoftd/228967-21sshd22:16:382
11193991514,0cyclictest3100-21diskmemload00:38:133
41140,0ktimersoftd/00-21swapper/023:25:190
1119399140,0cyclictest0-21swapper/320:55:193
11192991413,0cyclictest0-21swapper/223:53:212
11192991413,0cyclictest0-21swapper/221:48:002
11191991413,0cyclictest0-21swapper/123:37:571
11191991413,0cyclictest0-21swapper/123:06:281
41130,0ktimersoftd/00-21swapper/021:24:020
112750130,0irq/25-eth08762-21sshd23:56:111
112750130,0irq/25-eth08469-21sshd00:25:563
112750130,0irq/25-eth030795-21sshd23:50:301
112750130,0irq/25-eth00-21swapper/221:40:272
11193991312,0cyclictest31347-21sshd21:34:413
11193991312,0cyclictest0-21swapper/323:02:443
11193991312,0cyclictest0-21swapper/322:08:293
11193991311,0cyclictest0-21swapper/321:28:323
1119399130,0cyclictest0-21swapper/323:35:453
11192991312,0cyclictest11063-21sshd00:17:522
11191991312,0cyclictest0-21swapper/123:32:571
11191991312,0cyclictest0-21swapper/123:03:141
11191991312,0cyclictest0-21swapper/121:17:581
11191991312,0cyclictest0-21swapper/100:30:561
11191991310,0cyclictest0-21swapper/100:07:561
1119199130,0cyclictest21233-21sshd00:27:401
1119199130,0cyclictest14928-21sshd22:10:281
1119199130,0cyclictest0-21swapper/122:39:461
11190991312,0cyclictest0-21swapper/022:57:320
11190991312,0cyclictest0-21swapper/022:01:260
11190991311,0cyclictest0-21swapper/021:53:320
11190991310,0cyclictest30432-21sshd21:55:310
41120,0ktimersoftd/00-21swapper/022:23:160
41120,0ktimersoftd/00-21swapper/021:42:440
120650120,0irq/26-eth1-rx-15441-21rm22:40:190
112750120,0irq/25-eth01539-21sshd23:23:251
112750120,0irq/25-eth00-21swapper/321:20:313
112750120,0irq/25-eth00-21swapper/122:31:371
112750120,0irq/25-eth00-21swapper/122:05:431
112750120,0irq/25-eth00-21swapper/121:46:331
11193991212,0cyclictest0-21swapper/323:05:593
11193991212,0cyclictest0-21swapper/300:00:433
11193991211,0cyclictest25044-21sshd22:54:293
11193991211,0cyclictest0-21swapper/322:17:263
11193991211,0cyclictest0-21swapper/322:10:143
11193991211,0cyclictest0-21swapper/322:04:323
11193991211,0cyclictest0-21swapper/300:34:583
11193991211,0cyclictest0-21swapper/300:24:593
11193991211,0cyclictest0-21swapper/300:13:293
11193991210,0cyclictest0-21swapper/323:55:563
1119399120,0cyclictest6471-21sshd22:39:163
1119399120,0cyclictest11479-21sshd23:22:293
1119399120,0cyclictest0-21swapper/323:47:283
1119399120,0cyclictest0-21swapper/321:18:113
1119399120,0cyclictest0-21swapper/319:30:173
1119399120,0cyclictest0-21swapper/300:08:433
11192991211,0cyclictest0-21swapper/223:55:052
11192991211,0cyclictest0-21swapper/223:06:112
11192991211,0cyclictest0-21swapper/222:24:212
11192991210,0cyclictest0-21swapper/223:27:552
1119299120,0cyclictest32062-21sshd22:59:402
1119299120,0cyclictest0-21swapper/222:39:142
1119299120,0cyclictest0-21swapper/221:39:512
1119299120,0cyclictest0-21swapper/221:33:432
11191991212,0cyclictest0-21swapper/122:28:361
11191991212,0cyclictest0-21swapper/122:17:401
11191991211,0cyclictest13891-21timerandwakeup20:20:201
11191991211,0cyclictest0-21swapper/100:17:411
11191991210,0cyclictest3100-21diskmemload21:22:091
1119199120,0cyclictest0-21swapper/120:05:221
1119199120,0cyclictest0-21swapper/100:11:101
11190991212,0cyclictest0-21swapper/023:59:270
11190991211,0cyclictest28242-21sshd22:16:320
11190991211,0cyclictest27506-21sshd23:07:320
11190991211,0cyclictest0-21swapper/022:36:520
11190991211,0cyclictest0-21swapper/000:14:430
11190991210,0cyclictest0-21swapper/022:33:090
1119099120,0cyclictest0-21swapper/022:52:330
1119099120,0cyclictest0-21swapper/022:49:180
1119099120,0cyclictest0-21swapper/000:25:420
1119099120,0cyclictest0-21swapper/000:15:440
1119099120,0cyclictest0-21swapper/000:02:420
41110,0ktimersoftd/013630-21sshd22:06:070
271110,0ktimersoftd/213640-21sshd22:06:072
271110,0ktimersoftd/20-21swapper/222:49:482
191110,0ktimersoftd/10-21swapper/123:28:261
191110,0ktimersoftd/10-21swapper/122:43:561
11193991111,0cyclictest0-21swapper/323:40:433
11193991111,0cyclictest0-21swapper/321:01:003
11193991110,0cyclictest0-21swapper/322:24:383
11193991110,0cyclictest0-21swapper/319:20:163
1119399110,0cyclictest0-21swapper/322:47:433
1119399110,0cyclictest0-21swapper/320:16:453
1119299119,0cyclictest0-21swapper/223:39:382
11192991111,0cyclictest3100-21diskmemload22:42:572
11192991111,0cyclictest16764-21sshd00:22:512
11192991111,0cyclictest120650irq/26-eth1-rx-21:20:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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