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2026-07-30 - 17:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Thu Jul 30, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750660,0irq/25-eth00-21swapper/107:05:171
120650590,0irq/26-eth1-rx-0-21swapper/307:05:013
112750560,0irq/25-eth00-21swapper/207:07:282
112750460,0irq/25-eth00-21swapper/007:05:110
2895999170,0cyclictest0-21swapper/211:57:532
28959991615,0cyclictest20852-21diskmemload11:32:402
28959991511,0cyclictest13168-21sshd09:33:302
28959991511,0cyclictest0-21swapper/211:26:172
28959991414,0cyclictest0-21swapper/212:03:002
28959991413,0cyclictest0-21swapper/210:57:362
28959991413,0cyclictest0-21swapper/210:57:352
28959991412,0cyclictest0-21swapper/211:06:042
2895999140,0cyclictest20852-21diskmemload10:05:132
28960991312,0cyclictest31120-21rm09:19:263
28960991312,0cyclictest0-21swapper/312:08:123
28960991311,0cyclictest0-21swapper/312:32:363
28960991311,0cyclictest0-21swapper/310:21:413
2896099130,0cyclictest3513-21sshd10:25:373
2896099130,0cyclictest0-21swapper/312:25:383
2896099130,0cyclictest0-21swapper/309:42:533
2895999138,0cyclictest25243-21timerandwakeup09:10:222
28959991312,0cyclictest32197-21sshd09:23:362
28959991312,0cyclictest0-21swapper/212:10:472
28959991311,0cyclictest0-21swapper/212:37:022
28959991310,0cyclictest0-21swapper/209:28:012
2895999130,0cyclictest0-21swapper/211:36:242
2895999130,0cyclictest0-21swapper/210:30:142
2895999130,0cyclictest0-21swapper/210:15:052
28958991312,0cyclictest0-21swapper/110:20:201
28958991311,0cyclictest0-21swapper/112:20:401
28958991311,0cyclictest0-21swapper/109:41:181
2895899130,0cyclictest24765-21sshd11:38:301
2895899130,0cyclictest0-21swapper/111:44:261
2895899130,0cyclictest0-21swapper/111:11:391
28957991312,0cyclictest0-21swapper/011:38:050
28957991311,0cyclictest20852-21diskmemload09:32:030
28957991311,0cyclictest0-21swapper/011:19:160
28957991311,0cyclictest0-21swapper/011:19:160
2895799131,0cyclictest10-21rcuc/010:42:340
2895799130,0cyclictest0-21swapper/012:38:440
191130,0ktimersoftd/10-21swapper/110:56:341
191130,0ktimersoftd/10-21swapper/110:56:341
351120,0ktimersoftd/332264-21sshd12:00:123
28960991212,0cyclictest0-21swapper/311:18:573
28960991212,0cyclictest0-21swapper/311:18:563
28960991211,0cyclictest0-21swapper/312:16:003
28960991211,0cyclictest0-21swapper/310:30:243
28960991211,0cyclictest0-21swapper/309:13:573
28960991210,0cyclictest0-21swapper/311:29:183
28960991210,0cyclictest0-21swapper/308:25:253
2896099120,0cyclictest0-21swapper/309:32:253
2896099120,0cyclictest0-21swapper/309:24:523
2896099120,0cyclictest0-21swapper/308:17:233
2895999129,0cyclictest0-21swapper/209:53:202
2895999129,0cyclictest0-21swapper/209:40:492
2895999129,0cyclictest0-21swapper/209:39:452
28959991212,0cyclictest0-21swapper/210:38:182
28959991211,0cyclictest0-21swapper/212:33:332
28959991211,0cyclictest0-21swapper/211:44:592
28959991211,0cyclictest0-21swapper/211:03:242
28959991210,0cyclictest0-21swapper/212:07:172
2895999120,0cyclictest0-21swapper/212:26:342
2895999120,0cyclictest0-21swapper/211:22:412
2895999120,0cyclictest0-21swapper/210:54:032
2895999120,0cyclictest0-21swapper/210:48:532
2895999120,0cyclictest0-21swapper/209:55:212
28958991211,0cyclictest5223-21bash12:38:061
28958991211,0cyclictest0-21swapper/109:24:061
2895899120,0cyclictest17155-21sshd09:17:351
2895899120,0cyclictest0-21swapper/111:33:581
2895899120,0cyclictest0-21swapper/111:24:481
2895899120,0cyclictest0-21swapper/111:18:521
2895899120,0cyclictest0-21swapper/111:18:521
2895899120,0cyclictest0-21swapper/110:36:421
2895799129,0cyclictest0-21swapper/011:34:220
28957991211,0cyclictest30539-21sshd10:16:460
28957991211,0cyclictest15631-21sshd09:13:200
28957991211,0cyclictest0-21swapper/012:28:160
28957991211,0cyclictest0-21swapper/012:12:280
28957991211,0cyclictest0-21swapper/011:56:540
28957991211,0cyclictest0-21swapper/010:20:440
28957991211,0cyclictest0-21swapper/010:13:520
28957991210,0cyclictest0-21swapper/012:22:070
28957991210,0cyclictest0-21swapper/011:52:370
28957991210,0cyclictest0-21swapper/010:07:490
28957991210,0cyclictest0-21swapper/008:15:150
2895799120,0cyclictest8-21rcu_preempt11:48:190
2895799120,0cyclictest20852-21diskmemload10:28:360
2895799120,0cyclictest12233-21sshd11:04:020
2895799120,0cyclictest0-21swapper/009:26:350
1799120,0migration/121416-21sshd11:25:371
112750120,0irq/25-eth00-21swapper/112:00:281
112750120,0irq/25-eth00-21swapper/011:07:460
2896099119,0cyclictest0-21swapper/307:48:133
28960991111,0cyclictest0-21swapper/312:36:543
28960991111,0cyclictest0-21swapper/310:14:493
28960991111,0cyclictest0-21swapper/307:22:123
28960991110,0cyclictest21533-21sshd11:58:483
28960991110,0cyclictest0-21swapper/311:03:193
2895999119,0cyclictest0-21swapper/209:49:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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