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2026-02-26 - 20:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Thu Feb 26, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750630,0irq/25-eth00-21swapper/207:06:432
120650600,0irq/26-eth1-rx-0-21swapper/107:06:331
120650580,0irq/26-eth1-rx-0-21swapper/307:06:583
3144123520,0sleep00-21swapper/007:05:020
116899190,0cyclictest0-21swapper/212:26:092
1167991613,0cyclictest1793-21sshd12:19:471
116899150,0cyclictest0-21swapper/210:36:362
1167991514,0cyclictest0-21swapper/111:05:131
1167991512,0cyclictest0-21swapper/110:50:131
116799150,0cyclictest31932-21sshd10:05:121
1166991514,0cyclictest14909-21sshd09:32:550
1169991413,0cyclictest0-21swapper/311:17:393
1169991413,0cyclictest0-21swapper/310:28:243
116899140,0cyclictest0-21swapper/210:05:182
1167991413,0cyclictest25639-21diskmemload10:43:441
1166991413,0cyclictest0-21swapper/011:15:220
1166991413,0cyclictest0-21swapper/009:13:380
116699140,0cyclictest13008-21bash09:37:340
116699140,0cyclictest0-21swapper/012:10:200
116699140,0cyclictest0-21swapper/010:25:180
1169991312,0cyclictest30285-21sshd11:49:073
1169991312,0cyclictest0-21swapper/310:58:563
1168991312,0cyclictest0-21swapper/211:55:442
1168991311,0cyclictest0-21swapper/209:32:012
1168991310,0cyclictest0-21swapper/209:38:522
1168991310,0cyclictest0-21swapper/209:20:032
1167991312,0cyclictest0-21swapper/111:44:221
1167991311,0cyclictest0-21swapper/110:33:511
116799130,0cyclictest0-21swapper/112:25:211
116799130,0cyclictest0-21swapper/109:20:271
1166991312,0cyclictest112750irq/25-eth010:07:400
1166991312,0cyclictest0-21swapper/010:53:110
1166991311,0cyclictest0-21swapper/010:03:000
1166991310,0cyclictest0-21swapper/011:10:090
112750130,0irq/25-eth03347-21sshd11:20:100
112750130,0irq/25-eth00-21swapper/110:00:161
271120,0ktimersoftd/20-21swapper/210:52:032
120650120,0irq/26-eth1-rx-4420-21sshd10:40:272
1169991212,0cyclictest0-21swapper/309:13:483
1169991211,0cyclictest0-21swapper/312:03:173
1169991211,0cyclictest0-21swapper/311:26:273
1169991211,0cyclictest0-21swapper/310:20:293
1169991210,0cyclictest0-21swapper/312:11:393
1169991210,0cyclictest0-21swapper/310:04:413
116999120,0cyclictest29311-21id10:14:473
116999120,0cyclictest0-21swapper/311:55:093
116999120,0cyclictest0-21swapper/310:05:113
1168991212,0cyclictest0-21swapper/212:17:482
1168991211,0cyclictest0-21swapper/210:47:312
1168991211,0cyclictest0-21swapper/210:10:562
1168991211,0cyclictest0-21swapper/209:57:282
1168991210,0cyclictest0-21swapper/211:06:012
1168991210,0cyclictest0-21swapper/210:04:332
116899120,0cyclictest0-21swapper/212:13:432
116899120,0cyclictest0-21swapper/209:28:492
116899120,0cyclictest0-21swapper/208:30:132
1167991210,0cyclictest0-21swapper/112:00:301
1167991210,0cyclictest0-21swapper/109:35:531
116799120,0cyclictest0-21swapper/111:29:151
116799120,0cyclictest0-21swapper/110:46:581
116799120,0cyclictest0-21swapper/110:14:161
116799120,0cyclictest0-21swapper/109:26:351
1166991210,0cyclictest0-21swapper/012:28:190
116699120,0cyclictest23117-21sshd09:49:040
116699120,0cyclictest0-21swapper/009:44:250
112750120,0irq/25-eth00-21swapper/209:52:282
112750120,0irq/25-eth00-21swapper/112:37:341
41110,0ktimersoftd/02633-21sshd12:09:550
41110,0ktimersoftd/00-21swapper/012:31:490
41110,0ktimersoftd/00-21swapper/012:00:170
41110,0ktimersoftd/00-21swapper/011:51:020
41110,0ktimersoftd/00-21swapper/008:54:270
1169991111,0cyclictest0-21swapper/309:27:583
1169991111,0cyclictest0-21swapper/308:30:213
1169991110,0cyclictest27534-21sshd11:23:493
1169991110,0cyclictest16159-21sshd09:52:543
1169991110,0cyclictest15411-21sshd09:47:513
1169991110,0cyclictest13286-21sshd11:06:413
1169991110,0cyclictest11158-21sshd11:11:163
1169991110,0cyclictest0-21swapper/310:50:533
1169991110,0cyclictest0-21swapper/309:41:413
116999110,0cyclictest0-21swapper/312:25:213
116999110,0cyclictest0-21swapper/310:44:113
116999110,0cyclictest0-21swapper/309:23:203
116999110,0cyclictest0-21swapper/308:15:153
1168991111,0cyclictest0-21swapper/211:46:392
1168991111,0cyclictest0-21swapper/211:24:002
1168991110,0cyclictest7155-21sshd12:05:222
1168991110,0cyclictest20577-21perf07:50:002
116899110,0cyclictest0-21swapper/209:15:242
116899110,0cyclictest0-21swapper/208:36:432
116899110,0cyclictest0-21swapper/208:26:502
116899110,0cyclictest0-21swapper/207:40:092
116899110,0cyclictest0-21swapper/207:15:202
1167991111,0cyclictest0-21swapper/110:35:491
1167991111,0cyclictest0-21swapper/109:47:231
1167991111,0cyclictest0-21swapper/109:42:441
116799110,0cyclictest0-21swapper/110:16:041
116799110,0cyclictest0-21swapper/107:31:481
116699119,0cyclictest25639-21diskmemload09:55:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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