You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-14 - 18:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Feb 14, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650650,0irq/26-eth1-rx-0-21swapper/107:08:121
112750640,0irq/25-eth00-21swapper/307:06:323
112750440,0irq/25-eth00-21swapper/207:05:212
112750410,0irq/25-eth00-21swapper/007:07:260
8045991513,0cyclictest29165-21sshd11:07:163
804499150,0cyclictest0-21swapper/209:30:212
8045991413,0cyclictest0-21swapper/311:04:003
804599140,0cyclictest0-21swapper/311:10:223
804599140,0cyclictest0-21swapper/310:31:573
8043991413,0cyclictest0-21swapper/110:31:011
8042991412,0cyclictest0-21swapper/011:00:430
8045991312,0cyclictest112750irq/25-eth011:42:343
8045991312,0cyclictest0-21swapper/311:18:463
8045991311,0cyclictest0-21swapper/311:23:453
804599130,0cyclictest0-21swapper/312:25:473
804599130,0cyclictest0-21swapper/311:39:333
804599130,0cyclictest0-21swapper/309:33:583
8044991312,0cyclictest0-21swapper/210:26:192
8044991311,0cyclictest0-21swapper/210:19:222
804499130,0cyclictest32475-21diskmemload11:00:202
804499130,0cyclictest26835-21sshd12:30:452
804499130,0cyclictest0-21swapper/212:11:202
8043991312,0cyclictest25628-21bash11:16:321
8043991312,0cyclictest0-21swapper/112:21:501
8043991312,0cyclictest0-21swapper/111:53:231
804399130,0cyclictest0-21swapper/111:46:531
804399130,0cyclictest0-21swapper/111:37:351
804399130,0cyclictest0-21swapper/110:44:161
8042991312,0cyclictest11891-21id09:11:370
8042991312,0cyclictest112750irq/25-eth009:32:110
804299130,0cyclictest0-21swapper/011:30:270
804299130,0cyclictest0-21swapper/009:17:480
8045991212,0cyclictest0-21swapper/309:48:153
8045991211,0cyclictest5395-21sshd10:14:303
8045991211,0cyclictest0-21swapper/312:20:203
8045991211,0cyclictest0-21swapper/312:12:053
8045991211,0cyclictest0-21swapper/310:46:283
8045991211,0cyclictest0-21swapper/309:25:513
8045991210,0cyclictest0-21swapper/311:58:503
8045991210,0cyclictest0-21swapper/311:50:363
8045991210,0cyclictest0-21swapper/309:54:403
804599120,0cyclictest316-21sshd11:47:203
804599120,0cyclictest0-21swapper/312:15:153
804599120,0cyclictest0-21swapper/310:37:103
804599120,0cyclictest0-21swapper/310:16:163
8044991211,0cyclictest32475-21diskmemload10:54:332
8044991211,0cyclictest29287-21sshd12:16:202
8044991211,0cyclictest0-21swapper/211:35:202
8044991211,0cyclictest0-21swapper/211:22:192
8044991211,0cyclictest0-21swapper/210:00:252
8044991211,0cyclictest0-21swapper/209:43:142
8044991210,0cyclictest6706-21sshd10:24:352
8044991210,0cyclictest0-21swapper/210:46:332
8044991210,0cyclictest0-21swapper/209:49:362
8043991211,0cyclictest32475-21diskmemload09:59:391
8043991211,0cyclictest32475-21diskmemload09:22:001
8043991211,0cyclictest0-21swapper/110:10:071
8043991211,0cyclictest0-21swapper/109:32:221
8043991210,0cyclictest0-21swapper/109:53:161
804399120,0cyclictest0-21swapper/112:35:221
804399120,0cyclictest0-21swapper/111:13:181
8042991211,0cyclictest2615-21sshd10:19:000
8042991211,0cyclictest0-21swapper/011:41:150
8042991210,0cyclictest18374-21sshd11:10:280
8042991210,0cyclictest0-21swapper/012:04:150
8042991210,0cyclictest0-21swapper/010:49:270
804299120,0cyclictest32475-21diskmemload12:10:590
804299120,0cyclictest0-21swapper/011:20:280
804299120,0cyclictest0-21swapper/011:07:130
804299120,0cyclictest0-21swapper/009:51:140
112750120,0irq/25-eth0893-21sshd10:28:341
112750120,0irq/25-eth00-21swapper/312:04:183
112750120,0irq/25-eth00-21swapper/310:50:323
112750120,0irq/25-eth00-21swapper/210:33:042
112750120,0irq/25-eth00-21swapper/009:46:310
804599119,0cyclictest0-21swapper/308:14:453
804599119,0cyclictest0-21swapper/307:11:333
8045991111,0cyclictest0-21swapper/312:07:053
8045991111,0cyclictest0-21swapper/309:19:423
8045991111,0cyclictest0-21swapper/308:33:203
8045991110,0cyclictest26322-21bash10:07:473
8045991110,0cyclictest0-21swapper/311:28:453
8045991110,0cyclictest0-21swapper/309:37:563
8045991110,0cyclictest0-21swapper/309:21:393
804599110,0cyclictest0-21swapper/310:04:323
804599110,0cyclictest0-21swapper/308:07:483
804599110,0cyclictest0-21swapper/307:37:483
8044991111,0cyclictest0-21swapper/212:09:362
8044991111,0cyclictest0-21swapper/212:02:522
8044991111,0cyclictest0-21swapper/211:52:522
8044991111,0cyclictest0-21swapper/209:10:142
8044991110,0cyclictest0-21swapper/211:12:202
8044991110,0cyclictest0-21swapper/210:07:242
8044991110,0cyclictest0-21swapper/209:37:042
8044991110,0cyclictest0-21swapper/209:24:452
804499110,0cyclictest0-21swapper/210:59:222
804499110,0cyclictest0-21swapper/209:16:242
804399119,0cyclictest30806-21sshd10:37:591
8043991111,0cyclictest0-21swapper/111:05:031
8043991111,0cyclictest0-21swapper/109:46:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional