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2026-05-21 - 05:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Thu May 21, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750600,0irq/25-eth00-21swapper/319:05:003
112750600,0irq/25-eth00-21swapper/119:05:561
1932025721,0sleep00-21swapper/019:08:540
112750560,0irq/25-eth00-21swapper/219:05:232
1947599191,0cyclictest10030-21id23:38:172
271180,0ktimersoftd/215995-21sshd23:56:032
19474991817,0cyclictest0-21swapper/122:47:521
1947699160,0cyclictest0-21swapper/320:05:173
1947399160,0cyclictest0-21swapper/021:52:560
19475991514,0cyclictest0-21swapper/222:15:112
1947499150,0cyclictest7546-21sshd22:21:161
1947499150,0cyclictest0-21swapper/121:45:111
1947499150,0cyclictest0-21swapper/121:45:111
41140,0ktimersoftd/00-21swapper/023:54:330
41140,0ktimersoftd/00-21swapper/023:16:130
19476991413,0cyclictest0-21swapper/323:32:373
19476991413,0cyclictest0-21swapper/322:36:593
19476991411,0cyclictest0-21swapper/323:35:113
19475991413,0cyclictest0-21swapper/223:24:262
19475991410,0cyclictest0-21swapper/222:57:142
19474991413,0cyclictest8903-21sshd23:33:521
19474991413,0cyclictest28323-21sshd22:32:321
1947499140,0cyclictest0-21swapper/121:52:141
19473991413,0cyclictest0-21swapper/021:29:210
112750140,0irq/25-eth00-21swapper/223:05:122
19476991312,0cyclictest25121-21bash22:32:063
19476991312,0cyclictest0-21swapper/300:02:283
19476991311,0cyclictest12287-21latency_hist00:00:013
1947599139,0cyclictest2645-21sshd22:37:392
19475991312,0cyclictest0-21swapper/223:41:012
19475991312,0cyclictest0-21swapper/222:28:322
19475991311,0cyclictest0-21swapper/200:10:192
19474991312,0cyclictest0-21swapper/123:55:151
19474991312,0cyclictest0-21swapper/122:29:591
19474991312,0cyclictest0-21swapper/121:22:511
1947499130,0cyclictest29831-21cp22:03:021
19473991310,0cyclictest112750irq/25-eth022:05:350
1947399130,0cyclictest0-21swapper/020:25:110
1947699122,0cyclictest0-21swapper/321:17:343
19476991212,0cyclictest0-21swapper/300:24:063
19476991211,0cyclictest25822-21sshd23:27:313
19476991211,0cyclictest0-21swapper/323:21:213
19476991211,0cyclictest0-21swapper/323:10:333
19476991211,0cyclictest0-21swapper/322:01:263
19476991211,0cyclictest0-21swapper/321:51:053
19476991211,0cyclictest0-21swapper/320:35:153
19476991211,0cyclictest0-21swapper/300:06:323
19476991210,0cyclictest0-21swapper/323:41:343
19476991210,0cyclictest0-21swapper/323:03:073
19476991210,0cyclictest0-21swapper/322:43:083
19476991210,0cyclictest0-21swapper/321:43:053
19476991210,0cyclictest0-21swapper/321:24:573
1947699120,0cyclictest0-21swapper/322:17:413
19475991212,0cyclictest0-21swapper/222:34:422
19475991211,0cyclictest28494-21sshd00:15:012
19475991211,0cyclictest0-21swapper/223:34:382
19475991211,0cyclictest0-21swapper/221:47:182
19475991211,0cyclictest0-21swapper/221:47:172
19475991211,0cyclictest0-21swapper/221:32:262
19475991210,0cyclictest120650irq/26-eth1-rx-22:53:092
19475991210,0cyclictest0-21swapper/222:23:392
1947599120,0cyclictest30937-21sshd21:16:382
1947599120,0cyclictest0-21swapper/223:29:312
1947599120,0cyclictest0-21swapper/223:04:242
19474991212,0cyclictest0-21swapper/121:26:541
19474991211,0cyclictest3922-21sshd22:50:261
19474991210,0cyclictest11400-21diskmemload21:56:041
19474991210,0cyclictest0-21swapper/123:51:111
1947499120,0cyclictest13527-21hddtemp_smartct00:30:131
1947499120,0cyclictest0-21swapper/122:35:061
1947399129,0cyclictest0-21swapper/000:32:420
19473991211,0cyclictest8913-21irqstats22:00:160
19473991211,0cyclictest0-21swapper/023:36:550
19473991211,0cyclictest0-21swapper/021:30:370
19473991211,0cyclictest0-21swapper/019:22:500
19473991210,0cyclictest0-21swapper/023:24:070
19473991210,0cyclictest0-21swapper/022:24:380
1947399120,0cyclictest32096-21sshd23:02:440
1947399120,0cyclictest0-21swapper/022:38:140
1947399120,0cyclictest0-21swapper/021:24:240
1947399120,0cyclictest0-21swapper/000:36:030
1947399120,0cyclictest0-21swapper/000:05:410
191120,0ktimersoftd/116557-21sshd23:05:011
112750120,0irq/25-eth03394-21sshd22:41:590
112750120,0irq/25-eth015246-21sshd21:27:173
112750120,0irq/25-eth00-21swapper/322:56:583
41110,0ktimersoftd/00-21swapper/023:07:440
41110,0ktimersoftd/00-21swapper/021:36:110
351110,0ktimersoftd/316567-21sshd23:05:013
1947699113,0cyclictest10386-21sshd21:47:483
1947699113,0cyclictest10386-21sshd21:47:473
19476991111,0cyclictest0-21swapper/323:17:453
19476991111,0cyclictest0-21swapper/300:10:373
19476991110,0cyclictest2796-21sshd22:46:053
19476991110,0cyclictest11400-21diskmemload21:38:123
19476991110,0cyclictest0-21swapper/322:20:013
1947699110,0cyclictest17241-21sshd22:09:553
1947699110,0cyclictest17123-21sshd21:14:563
1947699110,0cyclictest112750irq/25-eth000:37:013
1947699110,0cyclictest0-21swapper/323:54:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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