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2026-02-02 - 07:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Mon Feb 02, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650610,0irq/26-eth1-rx-0-21swapper/119:06:521
120650590,0irq/26-eth1-rx-0-21swapper/319:05:333
112750560,0irq/25-eth00-21swapper/219:09:402
2629225124,0sleep00-21swapper/019:07:390
351180,0ktimersoftd/33171-21rm00:08:293
2654399160,0cyclictest0-21swapper/020:15:130
2654599150,0cyclictest0-21swapper/221:25:172
2654499150,0cyclictest0-21swapper/122:28:081
112750150,0irq/25-eth00-21swapper/322:38:253
26546991413,0cyclictest0-21swapper/323:25:203
26545991413,0cyclictest0-21swapper/223:47:562
2654599140,0cyclictest0-21swapper/223:01:432
2654599140,0cyclictest0-21swapper/222:40:122
26544991413,0cyclictest0-21swapper/123:17:171
26544991411,0cyclictest0-21swapper/122:40:001
2654499140,0cyclictest0-21swapper/119:15:131
2654399140,0cyclictest18573-21diskmemload00:00:130
26546991311,0cyclictest14994-21sshd23:16:103
26546991311,0cyclictest0-21swapper/322:56:393
26546991311,0cyclictest0-21swapper/321:00:143
2654699130,0cyclictest0-21swapper/320:30:233
2654699130,0cyclictest0-21swapper/300:13:473
26545991312,0cyclictest16436-21sshd22:17:472
26545991312,0cyclictest0-21swapper/200:25:062
26545991310,0cyclictest0-21swapper/221:58:582
2654599130,0cyclictest0-21swapper/223:28:532
2654599130,0cyclictest0-21swapper/223:10:212
2654599130,0cyclictest0-21swapper/220:30:192
26544991311,0cyclictest18573-21diskmemload23:59:201
26544991311,0cyclictest0-21swapper/122:57:461
26543991312,0cyclictest0-21swapper/023:41:400
26543991312,0cyclictest0-21swapper/021:32:390
26543991312,0cyclictest0-21swapper/000:29:240
2654399130,0cyclictest0-21swapper/022:17:130
41120,0ktimersoftd/00-21swapper/022:38:280
351120,0ktimersoftd/30-21swapper/322:01:283
26546991212,0cyclictest0-21swapper/323:04:333
26546991211,0cyclictest0-21swapper/323:55:473
26546991211,0cyclictest0-21swapper/323:21:373
26546991211,0cyclictest0-21swapper/300:26:333
26546991210,0cyclictest0-21swapper/323:32:473
26546991210,0cyclictest0-21swapper/300:15:453
2654699120,0cyclictest0-21swapper/323:42:113
2654699120,0cyclictest0-21swapper/321:25:073
2654599123,0cyclictest0-21swapper/219:45:142
26545991211,0cyclictest20505-21sshd22:08:442
26545991211,0cyclictest0-21swapper/223:08:052
26545991211,0cyclictest0-21swapper/223:08:052
26545991211,0cyclictest0-21swapper/221:42:222
26545991210,0cyclictest0-21swapper/223:32:362
2654599120,0cyclictest0-21swapper/223:56:052
2654599120,0cyclictest0-21swapper/222:57:592
2654599120,0cyclictest0-21swapper/222:48:062
2654599120,0cyclictest0-21swapper/200:12:192
2654599120,0cyclictest0-21swapper/200:04:122
26544991210,0cyclictest0-21swapper/122:32:061
26544991210,0cyclictest0-21swapper/100:26:241
2654499120,0cyclictest14527-21bash23:21:001
2654499120,0cyclictest11929-21bash21:13:471
2654499120,0cyclictest0-21swapper/121:52:071
2654499120,0cyclictest0-21swapper/121:30:391
2654499120,0cyclictest0-21swapper/100:33:431
26543991211,0cyclictest18573-21diskmemload21:19:350
26543991211,0cyclictest0-21swapper/022:45:330
26543991211,0cyclictest0-21swapper/021:24:290
26543991210,0cyclictest18573-21diskmemload22:25:340
26543991210,0cyclictest0-21swapper/023:59:400
26543991210,0cyclictest0-21swapper/021:46:260
26543991210,0cyclictest0-21swapper/021:41:330
2654399120,0cyclictest0-21swapper/023:05:320
2654399120,0cyclictest0-21swapper/023:05:320
2654399120,0cyclictest0-21swapper/022:10:080
2654399120,0cyclictest0-21swapper/000:17:540
2654399120,0cyclictest0-21swapper/000:07:480
112750120,0irq/25-eth00-21swapper/123:52:011
112750120,0irq/25-eth00-21swapper/023:37:210
112750120,0irq/25-eth00-21swapper/022:05:120
41110,0ktimersoftd/04702-21bash21:37:010
351110,0ktimersoftd/34701-21bash21:37:003
271110,0ktimersoftd/20-21swapper/221:53:382
26546991111,0cyclictest0-21swapper/323:36:303
26546991111,0cyclictest0-21swapper/322:52:423
26546991110,0cyclictest8816-21sshd00:24:073
26546991110,0cyclictest8592-21sshd22:11:423
26546991110,0cyclictest7284-21sshd22:06:393
26546991110,0cyclictest6367-21sshd21:46:533
26546991110,0cyclictest2544-21sshd21:51:093
26546991110,0cyclictest0-21swapper/323:06:313
26546991110,0cyclictest0-21swapper/323:06:313
26546991110,0cyclictest0-21swapper/322:21:063
26546991110,0cyclictest0-21swapper/321:20:133
2654699110,0cyclictest0-21swapper/323:49:513
2654699110,0cyclictest0-21swapper/322:33:113
2654699110,0cyclictest0-21swapper/322:19:083
2654699110,0cyclictest0-21swapper/320:44:273
2654699110,0cyclictest0-21swapper/320:36:393
26545991111,0cyclictest0-21swapper/222:10:412
26545991110,0cyclictest6965-21sshd21:47:002
26545991110,0cyclictest6894-21sshd22:35:432
26545991110,0cyclictest3541-21sshd22:01:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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