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2026-02-22 - 05:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Feb 22, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650650,0irq/26-eth1-rx-0-21swapper/319:06:573
120650630,0irq/26-eth1-rx-0-21swapper/119:08:531
112750600,0irq/25-eth00-21swapper/219:06:242
373024623,0sleep00-21swapper/019:06:240
408799180,0cyclictest5152-21sshd21:20:570
351180,0ktimersoftd/310737-21sshd00:08:443
409099160,0cyclictest0-21swapper/319:55:123
408999160,0cyclictest0-21swapper/222:27:282
4090991514,0cyclictest36-21ksoftirqd/322:06:333
409099140,0cyclictest0-21swapper/322:55:063
4089991412,0cyclictest0-21swapper/223:35:462
408899140,0cyclictest0-21swapper/123:55:181
4087991413,0cyclictest0-21swapper/023:20:190
4087991411,0cyclictest0-21swapper/023:50:510
191140,0ktimersoftd/128542-21diskmemload00:15:211
112750140,0irq/25-eth032219-21sshd21:54:353
4090991312,0cyclictest112750irq/25-eth022:12:413
4090991312,0cyclictest0-21swapper/323:42:583
409099130,0cyclictest0-21swapper/322:04:343
4089991312,0cyclictest27155-21hddtemp_smartct21:05:132
4089991312,0cyclictest19866-21sshd23:25:402
4089991311,0cyclictest0-21swapper/222:43:452
4089991311,0cyclictest0-21swapper/200:39:272
408999130,0cyclictest17140-21sshd23:50:042
408999130,0cyclictest0-21swapper/223:58:122
408999130,0cyclictest0-21swapper/223:21:442
408999130,0cyclictest0-21swapper/222:10:442
4088991312,0cyclictest0-21swapper/123:10:251
4088991312,0cyclictest0-21swapper/123:08:261
408899130,0cyclictest22031-21sshd22:46:431
408899130,0cyclictest0-21swapper/122:56:351
408899130,0cyclictest0-21swapper/122:00:131
4087991312,0cyclictest7501-21sshd23:04:160
4087991312,0cyclictest0-21swapper/000:07:220
4087991311,0cyclictest0-21swapper/022:28:020
408799131,0cyclictest0-21swapper/023:26:270
41120,0ktimersoftd/021861-21sshd00:10:180
4090991212,0cyclictest0-21swapper/323:04:443
4090991211,0cyclictest0-21swapper/322:29:113
4090991210,0cyclictest0-21swapper/321:22:393
409099120,0cyclictest0-21swapper/323:39:003
409099120,0cyclictest0-21swapper/322:45:133
408999124,0cyclictest18115-21bash23:05:432
4089991212,0cyclictest0-21swapper/222:06:342
4089991211,0cyclictest19049-21sshd00:00:102
4089991211,0cyclictest17569-21sshd21:52:162
4089991211,0cyclictest0-21swapper/222:51:392
4089991211,0cyclictest0-21swapper/222:33:382
4089991211,0cyclictest0-21swapper/221:00:212
4089991211,0cyclictest0-21swapper/200:06:202
4089991210,0cyclictest0-21swapper/221:38:132
408999120,0cyclictest0-21swapper/222:45:432
408999120,0cyclictest0-21swapper/222:37:482
408999120,0cyclictest0-21swapper/222:19:072
4088991212,0cyclictest0-21swapper/123:26:261
4088991211,0cyclictest0-21swapper/123:36:321
4088991211,0cyclictest0-21swapper/122:09:471
4088991211,0cyclictest0-21swapper/119:40:501
4088991210,0cyclictest0-21swapper/121:23:251
4088991210,0cyclictest0-21swapper/121:11:211
408899120,0cyclictest28542-21diskmemload22:52:371
408899120,0cyclictest0-21swapper/123:54:471
408899120,0cyclictest0-21swapper/123:46:391
408899120,0cyclictest0-21swapper/123:02:301
408899120,0cyclictest0-21swapper/100:07:061
4087991211,0cyclictest28542-21diskmemload23:08:140
4087991211,0cyclictest0-21swapper/022:00:580
4087991211,0cyclictest0-21swapper/021:38:470
4087991210,0cyclictest0-21swapper/023:38:330
408799120,0cyclictest0-21swapper/021:48:530
408799120,0cyclictest0-21swapper/019:37:300
191120,0ktimersoftd/10-21swapper/100:13:081
112750120,0irq/25-eth00-21swapper/000:30:110
112750120,0irq/25-eth00-21swapper/000:00:270
41110,0ktimersoftd/00-21swapper/021:25:020
409099119,0cyclictest0-21swapper/300:31:103
4090991111,0cyclictest0-21swapper/323:51:063
4090991111,0cyclictest0-21swapper/323:14:503
4090991111,0cyclictest0-21swapper/322:18:523
4090991111,0cyclictest0-21swapper/320:20:083
4090991110,0cyclictest0-21swapper/323:16:503
4090991110,0cyclictest0-21swapper/321:38:253
409099110,0cyclictest0-21swapper/322:51:093
409099110,0cyclictest0-21swapper/319:18:343
409099110,0cyclictest0-21swapper/300:23:003
4089991111,0cyclictest0-21swapper/221:14:032
4089991110,0cyclictest1770-21sshd21:40:122
4089991110,0cyclictest1770-21sshd21:40:112
4089991110,0cyclictest0-21swapper/223:11:362
4089991110,0cyclictest0-21swapper/221:24:102
4089991110,0cyclictest0-21swapper/221:16:022
4089991110,0cyclictest0-21swapper/200:19:212
408999110,0cyclictest0-21swapper/220:02:302
408999110,0cyclictest0-21swapper/200:22:472
4088991111,0cyclictest0-21swapper/122:20:071
4088991111,0cyclictest0-21swapper/120:55:391
4088991111,0cyclictest0-21swapper/120:05:281
4088991110,0cyclictest7247-21sshd21:55:291
4088991110,0cyclictest0-21swapper/122:12:081
4088991110,0cyclictest0-21swapper/120:44:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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