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2026-07-27 - 01:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Jul 26, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650640,0irq/26-eth1-rx-0-21swapper/307:06:303
112750600,0irq/25-eth00-21swapper/107:05:571
120650510,0irq/26-eth1-rx-0-21swapper/207:05:262
112750430,0irq/25-eth00-21swapper/007:05:380
271170,0ktimersoftd/25381-21bash10:11:322
1043299171,0cyclictest34-21rcuc/311:18:203
1043199151,0cyclictest112750irq/25-eth009:33:462
10430991512,0cyclictest0-21swapper/110:57:201
112750140,0irq/25-eth00-21swapper/110:36:581
10432991413,0cyclictest4721-21sshd10:56:293
10432991411,0cyclictest0-21swapper/312:29:323
1043299140,0cyclictest0-21swapper/312:00:513
1043299140,0cyclictest0-21swapper/309:54:543
10431991413,0cyclictest0-21swapper/212:19:042
10431991413,0cyclictest0-21swapper/211:22:292
10429991413,0cyclictest0-21swapper/012:22:420
271130,0ktimersoftd/20-21swapper/211:04:502
112750130,0irq/25-eth02706-21sshd12:34:453
112750130,0irq/25-eth00-21swapper/312:20:553
10432991311,0cyclictest0-21swapper/310:32:413
10432991311,0cyclictest0-21swapper/309:17:023
1043299130,0cyclictest0-21swapper/310:25:553
10431991312,0cyclictest4693-21sshd12:14:252
10431991312,0cyclictest16956-21sshd09:44:282
1043199130,0cyclictest0-21swapper/211:06:132
10430991312,0cyclictest2448-21sshd11:41:161
10430991312,0cyclictest0-21swapper/111:06:381
10430991311,0cyclictest26275-21sshd09:21:021
10430991311,0cyclictest0-21swapper/111:02:001
10430991311,0cyclictest0-21swapper/109:43:551
10429991312,0cyclictest7255-21sshd11:50:100
10429991312,0cyclictest0-21swapper/012:36:370
10429991312,0cyclictest0-21swapper/012:18:030
10429991312,0cyclictest0-21swapper/011:29:300
10429991312,0cyclictest0-21swapper/011:29:290
10429991311,0cyclictest0-21swapper/011:11:560
10429991310,0cyclictest0-21swapper/010:58:000
1042999130,0cyclictest0-21swapper/012:06:260
271120,0ktimersoftd/22346-21diskmemload09:29:492
271120,0ktimersoftd/20-21swapper/210:53:132
112750120,0irq/25-eth08487-21sshd10:24:193
112750120,0irq/25-eth00-21swapper/310:47:543
10432991212,0cyclictest0-21swapper/311:23:053
10432991211,0cyclictest9842-21sshd12:19:123
10432991211,0cyclictest0-21swapper/309:13:263
10432991210,0cyclictest0-21swapper/312:08:503
10432991210,0cyclictest0-21swapper/311:25:243
10432991210,0cyclictest0-21swapper/311:25:243
1043299120,0cyclictest25843-21sshd11:03:183
1043299120,0cyclictest0-21swapper/311:48:103
1043299120,0cyclictest0-21swapper/310:11:103
1043299120,0cyclictest0-21swapper/309:25:313
10431991212,0cyclictest0-21swapper/211:45:292
10431991212,0cyclictest0-21swapper/211:17:502
10431991211,0cyclictest25216-21sshd09:53:372
10431991211,0cyclictest16297-21sshd12:36:222
10431991211,0cyclictest0-21swapper/212:07:272
10431991211,0cyclictest0-21swapper/211:27:092
10431991211,0cyclictest0-21swapper/211:27:082
10431991211,0cyclictest0-21swapper/209:55:572
10431991211,0cyclictest0-21swapper/209:12:582
10431991210,0cyclictest0-21swapper/210:49:592
1043199120,0cyclictest11380-21sshd11:54:482
1043199120,0cyclictest0-21swapper/211:10:532
1043199120,0cyclictest0-21swapper/210:41:572
1043199120,0cyclictest0-21swapper/207:24:562
10430991212,0cyclictest0-21swapper/109:51:561
10430991211,0cyclictest0-21swapper/110:41:181
10430991211,0cyclictest0-21swapper/109:36:571
10430991210,0cyclictest0-21swapper/111:51:361
10430991210,0cyclictest0-21swapper/110:01:141
10430991210,0cyclictest0-21swapper/109:30:481
1043099120,0cyclictest7691-21sshd11:37:521
1043099120,0cyclictest16702-21sshd09:56:351
1043099120,0cyclictest10855-21sshd11:21:511
1043099120,0cyclictest0-21swapper/112:28:321
10429991211,0cyclictest28143-21sshd10:35:000
10429991210,0cyclictest0-21swapper/012:25:000
10429991210,0cyclictest0-21swapper/011:02:400
10429991210,0cyclictest0-21swapper/009:52:220
10429991210,0cyclictest0-21swapper/009:36:060
1042999120,0cyclictest30707-21sshd11:57:080
1042999120,0cyclictest29610-21sshd11:20:110
1042999120,0cyclictest25419-21bash11:07:170
1042999120,0cyclictest0-21swapper/010:14:340
1042999120,0cyclictest0-21swapper/009:15:190
41110,0ktimersoftd/031326-21bash09:58:290
191110,0ktimersoftd/10-21swapper/112:18:471
112750110,0irq/25-eth08-21rcu_preempt12:12:493
10432991111,0cyclictest24285-21bash09:41:123
10432991110,0cyclictest26645-21sshd09:49:453
10432991110,0cyclictest24727-21sshd11:11:163
10432991110,0cyclictest24551-21sshd10:42:393
10432991110,0cyclictest21771-21sshd11:06:493
10432991110,0cyclictest0-21swapper/310:39:243
10432991110,0cyclictest0-21swapper/309:34:003
1043299110,0cyclictest0-21swapper/311:31:063
1043299110,0cyclictest0-21swapper/311:31:053
1043299110,0cyclictest0-21swapper/310:50:573
1043199119,0cyclictest0-21swapper/208:23:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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