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2026-03-04 - 04:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Wed Mar 04, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750650,0irq/25-eth00-21swapper/319:05:213
112750610,0irq/25-eth00-21swapper/119:05:111
112750590,0irq/25-eth00-21swapper/219:09:222
2504024825,0sleep00-21swapper/019:07:390
25292991817,0cyclictest0-21swapper/121:40:431
112750180,0irq/25-eth09615-21cp00:22:112
2529399160,0cyclictest0-21swapper/221:34:282
25292991615,0cyclictest0-21swapper/122:54:291
25291991612,0cyclictest1480-21nfsd22:41:390
25294991512,0cyclictest0-21swapper/323:05:523
2529499140,0cyclictest0-21swapper/300:35:113
25293991411,0cyclictest0-21swapper/221:42:362
2529299140,0cyclictest0-21swapper/121:05:111
2529299140,0cyclictest0-21swapper/100:35:201
2529199142,0cyclictest22766-21sh22:00:140
2529199141,0cyclictest25962-21sshd23:05:140
191140,0ktimersoftd/10-21swapper/100:11:511
351130,0ktimersoftd/312581-21sshd22:53:193
25294991312,0cyclictest0-21swapper/300:22:253
25294991311,0cyclictest12444-21bash21:14:143
2529499130,0cyclictest0-21swapper/322:22:113
25293991312,0cyclictest0-21swapper/221:36:252
25293991311,0cyclictest2933-21sshd22:07:062
2529399130,0cyclictest0-21swapper/222:31:372
2529399130,0cyclictest0-21swapper/221:49:342
2529399130,0cyclictest0-21swapper/221:12:452
25292991312,0cyclictest13018-21sshd22:08:431
25292991311,0cyclictest0-21swapper/121:15:031
25292991311,0cyclictest0-21swapper/121:15:031
2529299130,0cyclictest13915-21bash23:58:081
25291991312,0cyclictest31441-21sshd23:25:540
25291991312,0cyclictest17216-21diskmemload21:15:270
25291991312,0cyclictest17216-21diskmemload21:15:260
25291991312,0cyclictest0-21swapper/021:25:190
25291991312,0cyclictest0-21swapper/000:36:180
2529199131,0cyclictest0-21swapper/023:20:210
2529199130,0cyclictest9826-21id21:58:190
2529199130,0cyclictest8857-21sshd00:27:000
2529199130,0cyclictest22309-21sshd21:40:190
351120,0ktimersoftd/30-21swapper/321:55:003
25294991211,0cyclictest1480-21nfsd00:34:443
25294991211,0cyclictest112750irq/25-eth021:35:423
25294991211,0cyclictest0-21swapper/322:15:413
25294991210,0cyclictest0-21swapper/322:31:573
2529499120,0cyclictest0-21swapper/323:37:493
2529499120,0cyclictest0-21swapper/320:25:123
2529499120,0cyclictest0-21swapper/300:07:473
25293991211,0cyclictest12040-21sshd23:13:052
25293991211,0cyclictest0-21swapper/222:24:532
25293991210,0cyclictest16257-21bash23:58:302
2529399120,0cyclictest16471-21bash22:58:552
2529399120,0cyclictest0-21swapper/223:01:412
2529399120,0cyclictest0-21swapper/222:50:332
2529399120,0cyclictest0-21swapper/222:38:202
25292991212,0cyclictest0-21swapper/123:02:511
25292991212,0cyclictest0-21swapper/120:15:191
25292991211,0cyclictest3035-21sshd00:21:081
25292991211,0cyclictest1480-21nfsd23:09:561
25292991211,0cyclictest0-21swapper/119:30:221
25292991211,0cyclictest0-21swapper/100:33:281
2529299120,0cyclictest0-21swapper/122:19:591
2529299120,0cyclictest0-21swapper/121:30:511
2529199122,0cyclictest29584-21sshd21:31:340
2529199122,0cyclictest24456-21sshd00:19:370
25291991212,0cyclictest0-21swapper/023:49:220
25291991211,0cyclictest5451-21sshd22:27:210
25291991211,0cyclictest0-21swapper/022:15:500
2529199121,0cyclictest9510-21sshd23:17:400
2529199121,0cyclictest0-21swapper/022:39:400
25291991210,0cyclictest0-21swapper/022:52:330
2529199120,0cyclictest10870-21sshd23:42:460
2529199120,0cyclictest0-21swapper/023:34:510
2529199120,0cyclictest0-21swapper/022:58:080
2529199120,0cyclictest0-21swapper/022:06:200
2529199120,0cyclictest0-21swapper/021:50:170
2529199120,0cyclictest0-21swapper/021:48:480
2529199120,0cyclictest0-21swapper/000:03:180
2529499119,0cyclictest610-21bash23:51:043
2529499119,0cyclictest0-21swapper/323:12:573
25294991111,0cyclictest30253-21sshd23:45:363
25294991111,0cyclictest0-21swapper/323:26:193
25294991111,0cyclictest0-21swapper/300:15:063
25294991110,0cyclictest10786-21sshd21:23:523
25294991110,0cyclictest0-21swapper/323:16:333
25294991110,0cyclictest0-21swapper/321:33:453
25294991110,0cyclictest0-21swapper/321:27:503
2529499110,0cyclictest0-21swapper/323:59:293
2529499110,0cyclictest0-21swapper/322:10:143
25293991111,0cyclictest0-21swapper/223:39:272
25293991111,0cyclictest0-21swapper/222:29:532
25293991111,0cyclictest0-21swapper/222:11:522
25293991110,0cyclictest8891-21bash22:47:462
25293991110,0cyclictest10749-21sshd23:22:512
25293991110,0cyclictest0-21swapper/223:52:572
25293991110,0cyclictest0-21swapper/223:46:052
25293991110,0cyclictest0-21swapper/223:08:472
25293991110,0cyclictest0-21swapper/222:43:422
2529399110,0cyclictest0-21swapper/200:35:152
25292991111,0cyclictest0-21swapper/123:35:151
25292991111,0cyclictest0-21swapper/123:20:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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