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2026-02-21 - 17:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Feb 21, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750690,0irq/25-eth00-21swapper/107:05:211
112750630,0irq/25-eth00-21swapper/307:07:593
1290424622,0sleep00-21swapper/007:05:280
120650460,0irq/26-eth1-rx-0-21swapper/207:06:272
13340991715,0cyclictest0-21swapper/109:25:341
13342991616,0cyclictest0-21swapper/310:49:073
1334199160,0cyclictest0-21swapper/212:05:222
13341991515,0cyclictest0-21swapper/211:40:182
13340991513,0cyclictest0-21swapper/111:25:211
1334099150,0cyclictest0-21swapper/112:05:261
13342991413,0cyclictest5361-21diskmemload12:01:253
13342991413,0cyclictest0-21swapper/312:30:003
1334299140,0cyclictest0-21swapper/308:15:193
1334199140,0cyclictest0-21swapper/210:21:122
13340991413,0cyclictest5361-21diskmemload10:24:281
13340991413,0cyclictest0-21swapper/107:30:131
13340991411,0cyclictest5361-21diskmemload09:31:581
13339991413,0cyclictest0-21swapper/011:14:050
1333999140,0cyclictest0-21swapper/012:35:220
13342991312,0cyclictest689-21bash09:14:083
13342991312,0cyclictest5361-21diskmemload10:28:303
1334299130,0cyclictest10160-21bash11:14:023
1334299130,0cyclictest0-21swapper/312:05:223
1334299130,0cyclictest0-21swapper/310:30:183
13341991312,0cyclictest0-21swapper/209:21:362
1334199130,0cyclictest9950irq/24-0000:00:10:57:332
1334199130,0cyclictest0-21swapper/211:22:592
1334199130,0cyclictest0-21swapper/209:14:192
13340991312,0cyclictest24572-21sshd11:40:421
1334099130,0cyclictest0-21swapper/112:25:031
1334099130,0cyclictest0-21swapper/111:09:401
1334099130,0cyclictest0-21swapper/110:39:411
13339991312,0cyclictest0-21swapper/012:16:560
13339991312,0cyclictest0-21swapper/010:52:220
1333999130,0cyclictest0-21swapper/009:30:200
41120,0ktimersoftd/021246-21nfsd411:35:170
41120,0ktimersoftd/00-21swapper/012:10:170
13342991212,0cyclictest0-21swapper/312:39:033
13342991211,0cyclictest26835-21sshd11:31:133
13342991211,0cyclictest16175-21cat08:20:213
13342991211,0cyclictest0-21swapper/311:56:403
13342991211,0cyclictest0-21swapper/310:52:323
13342991210,0cyclictest0-21swapper/309:16:213
1334299120,0cyclictest0-21swapper/311:21:003
1334299120,0cyclictest0-21swapper/311:19:153
1334299120,0cyclictest0-21swapper/310:19:263
1334299120,0cyclictest0-21swapper/308:00:163
13341991211,0cyclictest20749-21id10:50:492
13341991211,0cyclictest0-21swapper/212:35:152
1334199120,0cyclictest0-21swapper/210:10:172
1334199120,0cyclictest0-21swapper/209:41:422
13340991212,0cyclictest0-21swapper/112:22:021
13340991211,0cyclictest0-21swapper/112:12:021
13340991211,0cyclictest0-21swapper/111:48:141
13340991211,0cyclictest0-21swapper/110:53:101
13340991211,0cyclictest0-21swapper/110:42:571
1334099121,0cyclictest112750irq/25-eth010:10:151
13340991210,0cyclictest0-21swapper/109:43:001
1334099120,0cyclictest0-21swapper/112:17:021
1334099120,0cyclictest0-21swapper/110:00:391
13339991212,0cyclictest0-21swapper/011:24:460
13339991211,0cyclictest28644-21bash11:31:300
13339991211,0cyclictest0-21swapper/012:27:580
13339991211,0cyclictest0-21swapper/010:57:210
13339991211,0cyclictest0-21swapper/010:27:510
13339991211,0cyclictest0-21swapper/009:52:170
1333999120,0cyclictest0-21swapper/012:08:420
1333999120,0cyclictest0-21swapper/011:40:210
1333999120,0cyclictest0-21swapper/010:30:170
1333999120,0cyclictest0-21swapper/010:03:340
120650120,0irq/26-eth1-rx-0-21swapper/010:16:500
112750120,0irq/25-eth00-21swapper/209:52:162
41110,0ktimersoftd/07542-21sshd11:53:030
351110,0ktimersoftd/30-21swapper/310:43:573
271110,0ktimersoftd/20-21swapper/212:02:292
271110,0ktimersoftd/20-21swapper/207:31:492
191110,0ktimersoftd/119526-21sshd10:16:071
13342991111,0cyclictest0-21swapper/310:37:323
13342991111,0cyclictest0-21swapper/310:06:253
13342991111,0cyclictest0-21swapper/309:44:493
13342991111,0cyclictest0-21swapper/309:38:123
13342991111,0cyclictest0-21swapper/308:28:583
13342991110,0cyclictest24874-21sshd11:06:173
13342991110,0cyclictest0-21swapper/310:21:383
13342991110,0cyclictest0-21swapper/309:55:373
13342991110,0cyclictest0-21swapper/309:51:123
13342991110,0cyclictest0-21swapper/309:27:233
13342991110,0cyclictest0-21swapper/309:20:453
13341991111,0cyclictest0-21swapper/211:31:282
13341991110,0cyclictest22380-21sshd12:10:092
13341991110,0cyclictest1626-21sshd11:37:172
13341991110,0cyclictest0-21swapper/210:07:572
1334199110,0cyclictest0-21swapper/212:20:092
1334199110,0cyclictest0-21swapper/210:03:462
1334199110,0cyclictest0-21swapper/209:46:072
1334199110,0cyclictest0-21swapper/208:25:512
1334199110,0cyclictest0-21swapper/207:25:542
1334199110,0cyclictest0-21swapper/207:14:372
13340991111,0cyclictest0-21swapper/111:57:311
13340991111,0cyclictest0-21swapper/110:29:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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