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2026-02-03 - 09:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Tue Feb 03, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750660,0irq/25-eth00-21swapper/119:05:231
120650650,0irq/26-eth1-rx-0-21swapper/319:05:233
120650460,0irq/26-eth1-rx-0-21swapper/019:05:080
120650450,0irq/26-eth1-rx-0-21swapper/219:05:532
351180,0ktimersoftd/326233-21cp23:39:093
14460991615,0cyclictest0-21swapper/223:46:222
14460991511,0cyclictest31963-21sshd23:59:372
351140,0ktimersoftd/30-21swapper/323:54:363
1446099140,0cyclictest0-21swapper/220:15:222
1445999140,0cyclictest452-21sshd21:57:391
14458991413,0cyclictest0-21swapper/022:20:560
14458991411,0cyclictest0-21swapper/022:50:200
14461991312,0cyclictest6497-21diskmemload21:34:223
14461991311,0cyclictest13327-21sshd22:33:383
14461991311,0cyclictest0-21swapper/321:47:173
1446199130,0cyclictest0-21swapper/321:28:423
1446199130,0cyclictest0-21swapper/300:01:063
14460991312,0cyclictest112750irq/25-eth021:21:092
14460991312,0cyclictest0-21swapper/223:31:372
14460991312,0cyclictest0-21swapper/222:29:142
14460991312,0cyclictest0-21swapper/221:55:332
14460991312,0cyclictest0-21swapper/200:34:502
14460991311,0cyclictest0-21swapper/223:42:122
14460991310,0cyclictest5702-21sshd23:50:332
14460991310,0cyclictest0-21swapper/222:21:342
1446099130,0cyclictest21415-21sshd22:15:152
1446099130,0cyclictest0-21swapper/221:42:262
14459991312,0cyclictest0-21swapper/123:50:121
14459991312,0cyclictest0-21swapper/123:46:011
14459991311,0cyclictest0-21swapper/121:46:151
14459991311,0cyclictest0-21swapper/121:29:251
1445999130,0cyclictest6497-21diskmemload21:33:221
1445999130,0cyclictest0-21swapper/123:16:451
1445999130,0cyclictest0-21swapper/122:05:181
1445999130,0cyclictest0-21swapper/121:51:571
1445999130,0cyclictest0-21swapper/121:51:571
14458991312,0cyclictest6497-21diskmemload00:10:150
14458991312,0cyclictest0-21swapper/022:56:150
14458991312,0cyclictest0-21swapper/021:26:140
14458991310,0cyclictest0-21swapper/022:26:380
1445899130,0cyclictest0-21swapper/000:01:110
112750130,0irq/25-eth00-21swapper/022:38:220
9950120,0irq/24-0000:00:0-21swapper/021:33:200
351120,0ktimersoftd/30-21swapper/322:22:223
271120,0ktimersoftd/225576-21sshd23:14:332
14461991212,0cyclictest0-21swapper/322:45:153
14461991211,0cyclictest5456-21bash21:58:263
14461991211,0cyclictest18779-21fw_conntrack20:25:153
14461991211,0cyclictest0-21swapper/300:26:323
14461991210,0cyclictest17571-21sshd00:21:533
14461991210,0cyclictest0-21swapper/322:41:183
14461991210,0cyclictest0-21swapper/321:43:343
1446199120,0cyclictest0-21swapper/300:31:113
14460991211,0cyclictest112750irq/25-eth021:49:522
14460991211,0cyclictest0-21swapper/221:15:152
14460991211,0cyclictest0-21swapper/221:11:182
14460991211,0cyclictest0-21swapper/200:39:272
14460991211,0cyclictest0-21swapper/200:23:052
1446099120,0cyclictest0-21swapper/222:31:132
14459991212,0cyclictest0-21swapper/123:41:511
14459991212,0cyclictest0-21swapper/121:38:501
14459991211,0cyclictest6497-21diskmemload22:48:521
14459991211,0cyclictest0-21swapper/123:37:401
14459991211,0cyclictest0-21swapper/122:50:511
14459991210,0cyclictest0-21swapper/100:01:281
1445999120,0cyclictest0-21swapper/123:59:161
1445999120,0cyclictest0-21swapper/122:21:411
1445999120,0cyclictest0-21swapper/119:25:211
14458991211,0cyclictest707-21sshd23:20:250
14458991211,0cyclictest0-21swapper/021:24:140
14458991211,0cyclictest0-21swapper/021:12:230
14458991210,0cyclictest0-21swapper/023:35:100
14458991210,0cyclictest0-21swapper/021:16:210
14458991210,0cyclictest0-21swapper/000:20:010
1445899120,0cyclictest0-21swapper/023:25:230
1445899120,0cyclictest0-21swapper/021:47:140
112750120,0irq/25-eth06497-21diskmemload23:55:020
112750120,0irq/25-eth026224-21sshd22:11:072
112750120,0irq/25-eth010670-21sshd22:42:560
41110,0ktimersoftd/00-21swapper/023:05:010
351110,0ktimersoftd/30-21swapper/323:56:483
191110,0ktimersoftd/10-21swapper/121:17:411
1446199119,0cyclictest0-21swapper/320:04:413
14461991111,0cyclictest0-21swapper/323:18:503
14461991111,0cyclictest0-21swapper/321:16:503
14461991111,0cyclictest0-21swapper/321:14:523
14461991110,0cyclictest6497-21diskmemload00:14:483
14461991110,0cyclictest0-21swapper/322:39:193
14461991110,0cyclictest0-21swapper/322:18:323
1446199110,0cyclictest12325-21sshd23:27:113
1446199110,0cyclictest0-21swapper/320:11:343
14460991111,0cyclictest0-21swapper/222:01:152
14460991111,0cyclictest0-21swapper/221:34:592
14460991110,0cyclictest30022-21sshd22:40:512
14460991110,0cyclictest0-21swapper/223:21:032
14460991110,0cyclictest0-21swapper/221:38:432
14460991110,0cyclictest0-21swapper/220:45:302
14460991110,0cyclictest0-21swapper/200:01:492
1446099110,0cyclictest0-21swapper/219:14:402
1446099110,0cyclictest0-21swapper/200:25:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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