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2026-02-14 - 11:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Feb 14, 2026 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750650,0irq/25-eth00-21swapper/119:05:191
112750630,0irq/25-eth00-21swapper/319:08:453
120650470,0irq/26-eth1-rx-0-21swapper/219:05:262
112750430,0irq/25-eth00-21swapper/019:08:120
5037991514,0cyclictest8905-21sshd23:18:013
5037991514,0cyclictest0-21swapper/322:55:433
5037991514,0cyclictest0-21swapper/322:55:433
503699150,0cyclictest0-21swapper/200:05:202
5035991512,0cyclictest0-21swapper/122:37:231
503599150,0cyclictest0-21swapper/100:00:151
503799140,0cyclictest0-21swapper/321:19:253
503799140,0cyclictest0-21swapper/300:25:153
5035991413,0cyclictest0-21swapper/123:01:061
503599140,0cyclictest0-21swapper/100:07:531
5034991413,0cyclictest29472-21diskmemload21:52:450
5034991413,0cyclictest21225-21sshd22:39:340
5034991411,0cyclictest0-21swapper/021:46:490
9950130,0irq/24-0000:00:0-21swapper/323:38:433
5037991312,0cyclictest20042-21sshd23:14:473
5037991312,0cyclictest1522-21snmpd22:40:173
503799130,0cyclictest0-21swapper/322:06:003
503799130,0cyclictest0-21swapper/321:25:483
5036991312,0cyclictest0-21swapper/223:04:012
5036991312,0cyclictest0-21swapper/200:39:302
503699130,0cyclictest0-21swapper/221:40:132
5035991312,0cyclictest11337-21bash21:17:071
5035991312,0cyclictest0-21swapper/122:30:401
5035991312,0cyclictest0-21swapper/121:34:051
503599130,0cyclictest30357-21sshd23:46:371
503599130,0cyclictest28635-21sshd00:27:101
503599130,0cyclictest112750irq/25-eth023:40:081
5034991312,0cyclictest23543-21sshd22:50:010
503499130,0cyclictest0-21swapper/022:43:030
41130,0ktimersoftd/00-21swapper/020:55:170
112750130,0irq/25-eth00-21swapper/222:25:052
112750130,0irq/25-eth00-21swapper/022:00:200
5037991211,0cyclictest32080-21cp00:32:503
5037991211,0cyclictest16281-21sshd22:23:323
5037991211,0cyclictest0-21swapper/323:21:173
5037991211,0cyclictest0-21swapper/321:10:493
5037991210,0cyclictest4857-21sshd00:13:203
5037991210,0cyclictest0-21swapper/323:01:593
5037991210,0cyclictest0-21swapper/300:08:333
503799120,0cyclictest6184-21sshd23:32:463
503799120,0cyclictest0-21swapper/323:47:183
503799120,0cyclictest0-21swapper/323:26:163
503799120,0cyclictest0-21swapper/321:36:093
5036991211,0cyclictest20264-21bash00:25:472
5036991211,0cyclictest16535-21sshd22:38:472
5036991211,0cyclictest16263-21bash22:43:492
5036991211,0cyclictest0-21swapper/223:40:002
5036991211,0cyclictest0-21swapper/222:55:592
5036991211,0cyclictest0-21swapper/222:55:592
5036991211,0cyclictest0-21swapper/221:13:052
5036991211,0cyclictest0-21swapper/200:04:462
5036991210,0cyclictest0-21swapper/223:33:302
5036991210,0cyclictest0-21swapper/221:57:542
5036991210,0cyclictest0-21swapper/221:39:402
5036991210,0cyclictest0-21swapper/200:16:022
503699120,0cyclictest31310-21sshd00:22:312
503699120,0cyclictest0-21swapper/223:28:412
503699120,0cyclictest0-21swapper/223:17:002
503699120,0cyclictest0-21swapper/222:06:022
5035991211,0cyclictest0-21swapper/122:06:231
5035991210,0cyclictest0-21swapper/100:22:101
503599120,0cyclictest22514-21sshd22:04:241
503599120,0cyclictest17421-21sshd22:18:411
503599120,0cyclictest0-21swapper/123:12:211
503599120,0cyclictest0-21swapper/123:09:061
503599120,0cyclictest0-21swapper/121:42:261
503599120,0cyclictest0-21swapper/119:53:281
503599120,0cyclictest0-21swapper/100:33:551
5034991211,0cyclictest0-21swapper/022:08:470
5034991211,0cyclictest0-21swapper/021:38:280
5034991210,0cyclictest0-21swapper/022:46:320
5034991210,0cyclictest0-21swapper/021:23:420
503499120,0cyclictest18926-21sshd00:00:140
503499120,0cyclictest15223-21sshd23:39:160
503499120,0cyclictest1480-21nfsd23:55:460
503499120,0cyclictest0-21swapper/023:50:470
503499120,0cyclictest0-21swapper/023:19:320
503499120,0cyclictest0-21swapper/021:12:540
271120,0ktimersoftd/20-21swapper/223:51:172
191120,0ktimersoftd/10-21swapper/123:50:071
112750120,0irq/25-eth00-21swapper/122:59:071
112750120,0irq/25-eth00-21swapper/122:59:061
5037991111,0cyclictest0-21swapper/323:06:453
5037991110,0cyclictest5205-21sshd22:26:473
5037991110,0cyclictest3604-21bash00:23:173
5037991110,0cyclictest20041-21bash22:39:223
5037991110,0cyclictest18581-21bash21:58:413
5037991110,0cyclictest11682-21bash00:19:343
5037991110,0cyclictest0-21swapper/321:23:363
503799110,0cyclictest8502-21sshd00:03:463
503799110,0cyclictest0-21swapper/323:50:343
503699115,0cyclictest29472-21diskmemload21:47:132
5036991110,0cyclictest782-21bash22:46:192
5036991110,0cyclictest2971-21bash22:01:112
5036991110,0cyclictest27623-21bash22:20:132
5036991110,0cyclictest24240-21sshd21:29:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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