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2026-02-17 - 08:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Tue Feb 17, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750650,0irq/25-eth00-21swapper/319:08:173
120650600,0irq/26-eth1-rx-0-21swapper/119:06:161
112750550,0irq/25-eth00-21swapper/219:05:572
171123723,0sleep00-21swapper/019:05:530
211299160,0cyclictest0-21swapper/200:20:212
2112991514,0cyclictest0-21swapper/200:14:532
211299140,0cyclictest28096-21sshd21:21:122
211099140,0cyclictest112750irq/25-eth023:31:220
112750140,0irq/25-eth00-21swapper/021:23:410
2113991312,0cyclictest24948-21ps23:35:203
2113991312,0cyclictest15157-21sshd21:19:103
2113991312,0cyclictest0-21swapper/323:26:233
2113991311,0cyclictest0-21swapper/321:43:553
211399130,0cyclictest0-21swapper/323:59:073
211399130,0cyclictest0-21swapper/322:38:593
2112991312,0cyclictest0-21swapper/223:57:472
2112991311,0cyclictest0-21swapper/222:23:562
211299130,0cyclictest3185-21rm21:50:222
2111991312,0cyclictest0-21swapper/122:40:561
2111991312,0cyclictest0-21swapper/122:32:481
2110991312,0cyclictest0-21swapper/023:49:420
2110991310,0cyclictest1007-21sshd23:36:490
211099130,0cyclictest0-21swapper/023:55:250
112750130,0irq/25-eth00-21swapper/223:18:192
2113991212,0cyclictest21620-21bash22:49:533
2113991212,0cyclictest0-21swapper/322:40:573
2113991212,0cyclictest0-21swapper/321:36:163
2113991210,0cyclictest0-21swapper/323:47:593
2113991210,0cyclictest0-21swapper/322:32:493
2113991210,0cyclictest0-21swapper/321:51:353
2113991210,0cyclictest0-21swapper/300:06:333
211399120,0cyclictest31005-21bash23:13:573
211399120,0cyclictest0-21swapper/322:11:073
2112991212,0cyclictest0-21swapper/223:44:412
2112991211,0cyclictest0-21swapper/223:09:562
2112991211,0cyclictest0-21swapper/222:42:112
2112991210,0cyclictest0-21swapper/223:22:502
2112991210,0cyclictest0-21swapper/222:47:382
2112991210,0cyclictest0-21swapper/220:46:072
211299120,0cyclictest0-21swapper/222:32:042
211299120,0cyclictest0-21swapper/220:55:112
211299120,0cyclictest0-21swapper/200:09:112
2111991211,0cyclictest14932-21sshd00:24:181
2111991211,0cyclictest10961-21cp22:53:361
2111991211,0cyclictest0-21swapper/121:59:131
2111991211,0cyclictest0-21swapper/121:35:591
2111991211,0cyclictest0-21swapper/121:18:411
2111991211,0cyclictest0-21swapper/100:12:551
2111991210,0cyclictest0-21swapper/123:19:371
2111991210,0cyclictest0-21swapper/121:45:381
2111991210,0cyclictest0-21swapper/100:38:091
211199120,0cyclictest26539-21diskmemload00:26:181
211199120,0cyclictest0-21swapper/120:59:171
211199120,0cyclictest0-21swapper/100:32:131
2110991211,0cyclictest0-21swapper/023:13:140
2110991211,0cyclictest0-21swapper/022:19:350
2110991211,0cyclictest0-21swapper/021:53:540
2110991211,0cyclictest0-21swapper/021:30:400
2110991211,0cyclictest0-21swapper/000:27:490
2110991210,0cyclictest0-21swapper/022:13:380
2110991210,0cyclictest0-21swapper/000:04:490
211099120,0cyclictest0-21swapper/022:45:280
211099120,0cyclictest0-21swapper/021:38:340
211099120,0cyclictest0-21swapper/000:20:110
112750120,0irq/25-eth00-21swapper/321:46:143
112750120,0irq/25-eth00-21swapper/300:18:253
9950110,0irq/24-0000:00:14119-21sshd21:46:450
351110,0ktimersoftd/30-21swapper/322:23:453
2113991111,0cyclictest0-21swapper/322:09:073
2113991110,0cyclictest0-21swapper/319:22:043
211399110,0cyclictest0-21swapper/320:55:283
211299119,0cyclictest0-21swapper/219:37:412
2112991111,0cyclictest0-21swapper/222:53:062
2112991111,0cyclictest0-21swapper/221:46:252
2112991111,0cyclictest0-21swapper/220:20:202
2112991111,0cyclictest0-21swapper/219:55:222
2112991110,0cyclictest0-21swapper/223:35:302
2112991110,0cyclictest0-21swapper/223:30:022
2112991110,0cyclictest0-21swapper/221:42:282
211299110,0cyclictest0-21swapper/222:56:482
211299110,0cyclictest0-21swapper/221:34:482
211299110,0cyclictest0-21swapper/221:25:152
2111991111,0cyclictest0-21swapper/123:14:091
2111991111,0cyclictest0-21swapper/123:08:281
2111991111,0cyclictest0-21swapper/122:48:081
2111991111,0cyclictest0-21swapper/121:12:591
2111991111,0cyclictest0-21swapper/120:20:011
2111991110,0cyclictest27732-21sshd23:35:461
2111991110,0cyclictest0-21swapper/123:46:401
2111991110,0cyclictest0-21swapper/121:51:201
2111991110,0cyclictest0-21swapper/121:41:411
2111991110,0cyclictest0-21swapper/119:46:341
2111991110,0cyclictest0-21swapper/100:18:381
211199110,0cyclictest0-21swapper/123:54:071
211199110,0cyclictest0-21swapper/122:03:101
211199110,0cyclictest0-21swapper/121:20:391
211199110,0cyclictest0-21swapper/120:40:151
211199110,0cyclictest0-21swapper/120:09:061
211199110,0cyclictest0-21swapper/119:24:091
2110991111,0cyclictest0-21swapper/022:50:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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