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2026-03-01 - 07:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Mar 01, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650640,0irq/26-eth1-rx-0-21swapper/119:09:171
112750620,0irq/25-eth00-21swapper/319:09:173
120650510,0irq/26-eth1-rx-0-21swapper/219:06:512
2392424622,0sleep00-21swapper/019:08:370
2410099191,0cyclictest3442-21cat00:30:152
271180,0ktimersoftd/28843-21rm22:12:132
112750180,0irq/25-eth06593-21cp22:06:542
2409999140,0cyclictest0-21swapper/122:40:181
24098991411,0cyclictest0-21swapper/023:21:460
2409899140,0cyclictest32475-21sshd00:39:480
351130,0ktimersoftd/30-21swapper/321:25:583
24101991312,0cyclictest0-21swapper/300:26:043
24101991311,0cyclictest0-21swapper/322:10:473
2410199130,0cyclictest0-21swapper/321:46:093
24100991312,0cyclictest0-21swapper/222:30:382
24100991312,0cyclictest0-21swapper/222:23:262
24100991312,0cyclictest0-21swapper/200:39:142
24100991311,0cyclictest21234-21diskmemload23:39:032
24100991311,0cyclictest0-21swapper/221:30:002
24100991311,0cyclictest0-21swapper/200:19:142
24099991312,0cyclictest1539-21sshd23:32:131
2409999130,0cyclictest21234-21diskmemload21:13:231
2409999130,0cyclictest15075-21sshd21:58:221
2409999130,0cyclictest10590-21sshd00:16:221
2409999130,0cyclictest0-21swapper/123:58:211
24098991310,0cyclictest0-21swapper/021:28:430
2409899130,0cyclictest0-21swapper/022:30:130
2409899130,0cyclictest0-21swapper/021:51:500
2409899130,0cyclictest0-21swapper/021:13:520
271120,0ktimersoftd/20-21swapper/200:26:202
24101991211,0cyclictest17127-21sshd23:27:493
24101991211,0cyclictest0-21swapper/321:13:523
24101991211,0cyclictest0-21swapper/300:35:113
24101991210,0cyclictest28117-21bash21:30:303
24101991210,0cyclictest0-21swapper/323:53:433
24101991210,0cyclictest0-21swapper/323:53:433
24101991210,0cyclictest0-21swapper/321:56:383
24101991210,0cyclictest0-21swapper/321:42:413
24101991210,0cyclictest0-21swapper/321:19:203
2410199120,0cyclictest6636-21sshd22:26:433
2410199120,0cyclictest0-21swapper/322:41:073
2410199120,0cyclictest0-21swapper/322:09:043
2410199120,0cyclictest0-21swapper/321:23:033
24100991211,0cyclictest9950irq/24-0000:00:21:40:412
24100991211,0cyclictest9270-21bash00:01:142
24100991211,0cyclictest0-21swapper/222:51:112
24100991211,0cyclictest0-21swapper/221:47:392
2410099120,0cyclictest0-21swapper/223:50:192
2410099120,0cyclictest0-21swapper/223:50:192
2410099120,0cyclictest0-21swapper/219:15:002
24099991211,0cyclictest2369-21sshd00:30:111
24099991211,0cyclictest0-21swapper/123:48:151
24099991211,0cyclictest0-21swapper/122:23:131
24099991211,0cyclictest0-21swapper/121:18:521
24099991211,0cyclictest0-21swapper/100:24:161
24099991210,0cyclictest0-21swapper/123:28:161
24099991210,0cyclictest0-21swapper/122:37:371
2409999120,0cyclictest0-21swapper/123:24:191
2409999120,0cyclictest0-21swapper/122:28:401
2409999120,0cyclictest0-21swapper/122:19:441
2409999120,0cyclictest0-21swapper/122:05:341
24098991212,0cyclictest0-21swapper/021:23:030
24098991211,0cyclictest21234-21diskmemload00:05:540
24098991211,0cyclictest0-21swapper/023:25:430
24098991211,0cyclictest0-21swapper/021:19:190
24098991210,0cyclictest0-21swapper/022:25:520
24098991210,0cyclictest0-21swapper/021:34:260
2409899120,0cyclictest0-21swapper/023:53:490
2409899120,0cyclictest0-21swapper/023:53:490
2409899120,0cyclictest0-21swapper/023:43:440
2409899120,0cyclictest0-21swapper/022:35:190
2409899120,0cyclictest0-21swapper/022:00:480
2409899120,0cyclictest0-21swapper/000:21:560
112750120,0irq/25-eth00-21swapper/123:18:031
112750120,0irq/25-eth00-21swapper/023:32:030
24101991111,0cyclictest0-21swapper/321:00:163
24101991111,0cyclictest0-21swapper/319:20:293
24101991110,0cyclictest5316-21sshd23:06:063
24101991110,0cyclictest0-21swapper/323:19:553
24101991110,0cyclictest0-21swapper/322:50:323
24101991110,0cyclictest0-21swapper/321:37:323
2410199110,0cyclictest0-21swapper/323:21:433
2410199110,0cyclictest0-21swapper/300:05:103
24100991111,0cyclictest0-21swapper/221:20:342
24100991110,0cyclictest26097-21bash22:00:042
24100991110,0cyclictest18828-21bash23:33:032
24100991110,0cyclictest18356-21sshd21:19:212
24100991110,0cyclictest18089-21sshd23:23:012
24100991110,0cyclictest0-21swapper/223:08:582
24100991110,0cyclictest0-21swapper/221:00:282
2410099110,0cyclictest0-21swapper/221:05:572
2410099110,0cyclictest0-21swapper/220:49:542
2410099110,0cyclictest0-21swapper/219:26:162
24099991110,0cyclictest21234-21diskmemload22:52:421
24099991110,0cyclictest20399-21sshd23:08:311
24099991110,0cyclictest10109-21sshd00:26:141
24099991110,0cyclictest0-21swapper/121:47:401
24099991110,0cyclictest0-21swapper/100:36:071
24099991110,0cyclictest0-21swapper/100:04:171
2409999110,0cyclictest0-21swapper/121:33:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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