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2026-02-17 - 15:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Tue Feb 17, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650590,0irq/26-eth1-rx-0-21swapper/107:06:031
112750580,0irq/25-eth00-21swapper/307:09:403
112750560,0irq/25-eth00-21swapper/207:07:062
1202925128,0sleep00-21swapper/007:05:090
1419699160,0cyclictest0-21swapper/010:59:460
9950140,0irq/24-0000:00:25072-21id10:36:592
41140,0ktimersoftd/00-21swapper/009:59:070
14199991413,0cyclictest0-21swapper/312:27:443
14199991413,0cyclictest0-21swapper/309:18:163
14199991412,0cyclictest0-21swapper/311:00:083
1419999140,0cyclictest0-21swapper/311:59:163
1419999140,0cyclictest0-21swapper/309:49:573
1419799140,0cyclictest1480-21nfsd12:00:141
1419799140,0cyclictest0-21swapper/111:26:331
14196991413,0cyclictest6225-21diskmemload11:54:210
1419699140,0cyclictest5964-21sshd11:01:440
1419699140,0cyclictest0-21swapper/010:15:200
1419699140,0cyclictest0-21swapper/009:33:550
14199991312,0cyclictest32688-21sshd10:15:533
14199991312,0cyclictest0-21swapper/310:55:153
1419999130,0cyclictest26167-21rm09:24:323
1419999130,0cyclictest0-21swapper/311:45:193
14198991312,0cyclictest0-21swapper/210:24:272
14198991311,0cyclictest0-21swapper/212:15:102
14197991312,0cyclictest0-21swapper/111:06:131
14197991311,0cyclictest0-21swapper/108:50:181
1419799130,0cyclictest32166-21sshd10:32:391
1419799130,0cyclictest25773-21sshd09:24:281
1419799130,0cyclictest0-21swapper/110:39:301
14196991312,0cyclictest3791-21sshd10:33:230
14196991310,0cyclictest14369-21sshd11:31:280
1419699130,0cyclictest0-21swapper/011:49:080
1419699130,0cyclictest0-21swapper/010:47:340
1419699130,0cyclictest0-21swapper/010:38:020
1419699130,0cyclictest0-21swapper/009:21:220
191120,0ktimersoftd/10-21swapper/111:56:101
14199991212,0cyclictest0-21swapper/312:04:293
14199991211,0cyclictest0-21swapper/312:11:273
14199991211,0cyclictest0-21swapper/310:32:013
14199991211,0cyclictest0-21swapper/310:09:013
14199991210,0cyclictest6225-21diskmemload09:54:373
14199991210,0cyclictest0-21swapper/310:29:493
1419999120,0cyclictest2801-21sshd10:38:533
1419999120,0cyclictest0-21swapper/312:21:133
14198991211,0cyclictest0-21swapper/211:37:032
14198991210,0cyclictest28162-21sshd11:50:472
14198991210,0cyclictest0-21swapper/211:19:592
14198991210,0cyclictest0-21swapper/210:45:152
14198991210,0cyclictest0-21swapper/209:48:202
14198991210,0cyclictest0-21swapper/209:34:302
14198991210,0cyclictest0-21swapper/208:25:082
1419899120,0cyclictest0-21swapper/212:04:562
1419899120,0cyclictest0-21swapper/211:07:052
1419899120,0cyclictest0-21swapper/210:14:562
1419899120,0cyclictest0-21swapper/209:44:532
14197991212,0cyclictest0-21swapper/110:04:321
14197991212,0cyclictest0-21swapper/109:57:131
14197991211,0cyclictest26722-21sshd11:39:271
14197991211,0cyclictest0-21swapper/111:24:351
14197991211,0cyclictest0-21swapper/111:24:351
14197991211,0cyclictest0-21swapper/111:13:261
14197991211,0cyclictest0-21swapper/111:13:261
14197991210,0cyclictest0-21swapper/112:27:181
14197991210,0cyclictest0-21swapper/112:15:491
14197991210,0cyclictest0-21swapper/110:44:091
1419799120,0cyclictest6225-21diskmemload12:32:181
1419799120,0cyclictest0-21swapper/111:17:091
1419799120,0cyclictest0-21swapper/110:21:091
14196991211,0cyclictest23936-21sshd11:21:500
14196991211,0cyclictest23936-21sshd11:21:500
14196991211,0cyclictest112750irq/25-eth009:11:440
14196991211,0cyclictest0-21swapper/011:05:130
14196991210,0cyclictest12124-21rm10:12:220
14196991210,0cyclictest0-21swapper/012:23:310
1419699120,0cyclictest0-21swapper/011:18:070
112750120,0irq/25-eth00-21swapper/111:54:121
41110,0ktimersoftd/00-21swapper/008:35:180
191110,0ktimersoftd/10-21swapper/110:27:181
14199991111,0cyclictest0-21swapper/311:20:003
14199991111,0cyclictest0-21swapper/311:10:493
14199991111,0cyclictest0-21swapper/311:10:493
14199991111,0cyclictest0-21swapper/310:48:103
14199991111,0cyclictest0-21swapper/310:22:583
14199991110,0cyclictest0-21swapper/310:52:493
14199991110,0cyclictest0-21swapper/308:54:133
1419999110,0cyclictest28929-21bash10:04:103
1419999110,0cyclictest0-21swapper/311:38:353
1419999110,0cyclictest0-21swapper/307:21:093
14198991111,0cyclictest0-21swapper/212:26:392
14198991111,0cyclictest0-21swapper/212:11:542
14198991111,0cyclictest0-21swapper/210:07:512
14198991111,0cyclictest0-21swapper/209:58:052
14198991111,0cyclictest0-21swapper/209:28:272
14198991111,0cyclictest0-21swapper/209:15:412
14198991110,0cyclictest25934-21sshd10:42:492
14198991110,0cyclictest0-21swapper/211:47:172
14198991110,0cyclictest0-21swapper/210:19:352
14198991110,0cyclictest0-21swapper/207:57:092
1419899110,0cyclictest0-21swapper/210:59:532
1419899110,0cyclictest0-21swapper/210:31:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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