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2026-04-06 - 02:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Mon Apr 06, 2026 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/119:05:171
120650600,0irq/26-eth1-rx-0-21swapper/319:06:323
112750560,0irq/25-eth00-21swapper/219:07:502
2098124220,0sleep00-21swapper/019:07:290
2124699190,0cyclictest1224-21sshd22:57:340
21248991515,0cyclictest0-21swapper/221:52:392
21247991511,0cyclictest19638-21sshd22:45:511
2124999140,0cyclictest25514-21sshd23:01:043
2124999140,0cyclictest10911-21sshd23:37:113
21248991413,0cyclictest0-21swapper/222:21:062
21248991411,0cyclictest0-21swapper/223:28:302
2124899140,0cyclictest0-21swapper/221:30:352
2124799140,0cyclictest0-21swapper/121:31:161
21246991413,0cyclictest31536-21rm23:06:450
21246991411,0cyclictest30145-21sshd22:42:420
21246991411,0cyclictest0-21swapper/000:07:510
21249991312,0cyclictest13171-21diskmemload22:43:313
21249991312,0cyclictest0-21swapper/323:12:053
21249991312,0cyclictest0-21swapper/322:14:153
21249991312,0cyclictest0-21swapper/322:14:143
21249991312,0cyclictest0-21swapper/321:56:153
21249991312,0cyclictest0-21swapper/300:29:563
2124999130,0cyclictest0-21swapper/323:26:093
2124999130,0cyclictest0-21swapper/319:25:153
21248991313,0cyclictest0-21swapper/221:17:422
21248991312,0cyclictest0-21swapper/222:51:542
21248991312,0cyclictest0-21swapper/200:24:432
21248991310,0cyclictest28292-21sshd21:21:242
2124899130,0cyclictest27455-21id23:44:322
2124899130,0cyclictest0-21swapper/221:10:152
21247991312,0cyclictest0-21swapper/123:55:471
21247991312,0cyclictest0-21swapper/122:11:351
21247991312,0cyclictest0-21swapper/122:11:341
2124799130,0cyclictest8333-21sshd22:34:491
21246991312,0cyclictest30652-21sshd23:59:220
21246991312,0cyclictest27728-21sshd00:18:050
21246991312,0cyclictest13171-21diskmemload22:52:130
21246991312,0cyclictest0-21swapper/021:47:320
21246991312,0cyclictest0-21swapper/021:47:310
2124699130,0cyclictest20480-21sshd22:31:400
2124699130,0cyclictest112750irq/25-eth022:23:110
2124699130,0cyclictest0-21swapper/023:48:060
2124699130,0cyclictest0-21swapper/023:19:180
191130,0ktimersoftd/10-21swapper/122:06:201
271120,0ktimersoftd/20-21swapper/221:44:462
2124999129,0cyclictest0-21swapper/323:48:133
21249991212,0cyclictest0-21swapper/321:21:443
21249991212,0cyclictest0-21swapper/300:17:583
21249991211,0cyclictest0-21swapper/322:57:493
21249991210,0cyclictest14409-21sshd21:28:573
21249991210,0cyclictest0-21swapper/322:53:033
21249991210,0cyclictest0-21swapper/322:25:593
2124999120,0cyclictest0-21swapper/322:15:593
2124999120,0cyclictest0-21swapper/321:12:343
21248991211,0cyclictest831-21sshd21:26:522
21248991211,0cyclictest0-21swapper/221:48:572
21248991211,0cyclictest0-21swapper/221:48:562
21248991211,0cyclictest0-21swapper/200:11:012
21248991210,0cyclictest0-21swapper/200:29:582
2124899120,0cyclictest31494-21sshd21:36:032
2124899120,0cyclictest0-21swapper/223:23:442
2124899120,0cyclictest0-21swapper/223:01:392
2124899120,0cyclictest0-21swapper/222:58:252
2124899120,0cyclictest0-21swapper/222:47:092
2124899120,0cyclictest0-21swapper/222:31:212
21247991212,0cyclictest0-21swapper/100:27:581
21247991212,0cyclictest0-21swapper/100:12:301
21247991211,0cyclictest27683-21sshd21:16:381
21247991211,0cyclictest18-21rcuc/100:38:111
21247991211,0cyclictest0-21swapper/123:23:571
21247991211,0cyclictest0-21swapper/122:41:051
21247991210,0cyclictest17508-21sshd23:47:461
21247991210,0cyclictest0-21swapper/121:20:201
2124799120,0cyclictest0-21swapper/123:19:111
2124799120,0cyclictest0-21swapper/121:49:381
2124799120,0cyclictest0-21swapper/121:49:371
2124799120,0cyclictest0-21swapper/119:50:101
21246991212,0cyclictest0-21swapper/022:06:270
21246991211,0cyclictest29950-21sshd23:20:480
21246991211,0cyclictest20568-21bash21:34:380
21246991210,0cyclictest0-21swapper/022:47:280
21246991210,0cyclictest0-21swapper/000:25:030
21246991210,0cyclictest0-21swapper/000:21:340
2124699120,0cyclictest0-21swapper/023:33:350
2124699120,0cyclictest0-21swapper/021:38:200
2124699120,0cyclictest0-21swapper/021:20:000
112750120,0irq/25-eth00-21swapper/222:17:242
112750120,0irq/25-eth00-21swapper/122:03:551
112750120,0irq/25-eth00-21swapper/021:29:070
351110,0ktimersoftd/30-21swapper/300:35:313
21249991111,0cyclictest0-21swapper/323:56:143
21249991111,0cyclictest0-21swapper/300:04:293
21249991110,0cyclictest31450-21rm22:33:233
21249991110,0cyclictest0-21swapper/321:45:193
21249991110,0cyclictest0-21swapper/321:45:183
21249991110,0cyclictest0-21swapper/300:09:293
2124999110,0cyclictest0-21swapper/323:19:533
21248991111,0cyclictest0-21swapper/200:00:472
21248991110,0cyclictest29226-21sshd22:04:242
21247991111,0cyclictest0-21swapper/123:39:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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