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2026-03-05 - 12:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Thu Mar 05, 2026 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750600,0irq/25-eth00-21swapper/319:05:513
112750600,0irq/25-eth00-21swapper/119:05:201
112750530,0irq/25-eth00-21swapper/019:06:220
1472425129,0sleep20-21swapper/219:05:202
1551599211,0cyclictest6372-21sshd23:08:370
15515991514,0cyclictest0-21swapper/000:24:500
15518991411,0cyclictest0-21swapper/300:10:503
15517991413,0cyclictest15381-21latency_hist21:59:592
15517991411,0cyclictest0-21swapper/223:38:172
1551799140,0cyclictest0-21swapper/223:13:112
1551799140,0cyclictest0-21swapper/219:45:142
1551699140,0cyclictest0-21swapper/123:13:161
1551599140,0cyclictest0-21swapper/000:08:280
112750140,0irq/25-eth00-21swapper/322:30:223
15518991312,0cyclictest0-21swapper/321:59:233
15518991312,0cyclictest0-21swapper/321:37:163
1551899130,0cyclictest0-21swapper/321:51:333
1551899130,0cyclictest0-21swapper/300:22:343
15517991312,0cyclictest26480-21id00:07:052
15517991312,0cyclictest21184-21sshd23:25:512
15517991312,0cyclictest0-21swapper/222:02:272
15517991312,0cyclictest0-21swapper/200:19:042
15516991312,0cyclictest24499-21sshd21:22:121
15516991312,0cyclictest0-21swapper/122:26:561
15516991311,0cyclictest0-21swapper/123:54:591
15516991310,0cyclictest0-21swapper/100:25:321
15515991311,0cyclictest14859-21sshd22:34:490
112750130,0irq/25-eth00-21swapper/023:48:490
9950120,0irq/24-0000:00:13622-21sshd00:00:093
15518991211,0cyclictest27077-21sshd23:52:023
15518991211,0cyclictest16130-21sshd21:11:083
15518991211,0cyclictest0-21swapper/323:47:223
15518991211,0cyclictest0-21swapper/323:42:303
15518991211,0cyclictest0-21swapper/321:32:233
15518991210,0cyclictest8772-21bash21:49:143
15518991210,0cyclictest0-21swapper/323:15:263
15518991210,0cyclictest0-21swapper/322:27:063
15518991210,0cyclictest0-21swapper/322:12:563
1551899120,0cyclictest0-21swapper/323:00:483
1551799125,0cyclictest0-21swapper/221:43:272
15517991211,0cyclictest0-21swapper/223:03:122
15517991211,0cyclictest0-21swapper/222:31:142
15517991211,0cyclictest0-21swapper/221:26:052
15517991210,0cyclictest0-21swapper/223:40:432
15517991210,0cyclictest0-21swapper/222:55:532
15517991210,0cyclictest0-21swapper/219:40:232
1551799120,0cyclictest27420-21bash00:32:322
1551799120,0cyclictest0-21swapper/222:07:202
1551799120,0cyclictest0-21swapper/221:19:002
1551799120,0cyclictest0-21swapper/220:10:202
1551799120,0cyclictest0-21swapper/219:20:162
1551799120,0cyclictest0-21swapper/200:25:142
15516991212,0cyclictest0-21swapper/121:46:221
15516991211,0cyclictest7420-21diskmemload23:30:491
15516991211,0cyclictest0-21swapper/100:11:351
15516991210,0cyclictest0-21swapper/122:05:261
1551699120,0cyclictest19300-21bash22:10:191
15515991211,0cyclictest0-21swapper/022:52:080
15515991211,0cyclictest0-21swapper/021:36:570
15515991211,0cyclictest0-21swapper/021:20:070
15515991211,0cyclictest0-21swapper/021:17:410
15515991210,0cyclictest0-21swapper/023:19:260
15515991210,0cyclictest0-21swapper/021:10:350
1551599120,0cyclictest0-21swapper/023:56:300
1551599120,0cyclictest0-21swapper/022:03:340
112750120,0irq/25-eth012759-21sshd21:54:440
112750120,0irq/25-eth00-21swapper/322:05:573
112750120,0irq/25-eth00-21swapper/222:49:572
112750120,0irq/25-eth00-21swapper/122:32:321
41110,0ktimersoftd/012062-21sshd00:15:040
41110,0ktimersoftd/00-21swapper/022:46:320
271110,0ktimersoftd/20-21swapper/222:20:132
271110,0ktimersoftd/20-21swapper/200:39:512
15518991111,0cyclictest0-21swapper/323:59:063
15518991111,0cyclictest0-21swapper/319:59:273
15518991110,0cyclictest28589-21bash21:22:513
15518991110,0cyclictest112750irq/25-eth023:33:293
15518991110,0cyclictest0-21swapper/322:53:293
15518991110,0cyclictest0-21swapper/322:20:013
15518991110,0cyclictest0-21swapper/320:23:373
1551899110,0cyclictest22320-21sshd22:55:553
1551899110,0cyclictest0-21swapper/320:50:563
1551899110,0cyclictest0-21swapper/319:31:273
1551899110,0cyclictest0-21swapper/300:33:223
15517991111,0cyclictest0-21swapper/223:57:342
15517991111,0cyclictest0-21swapper/221:48:032
15517991110,0cyclictest11445-21sshd22:19:172
15517991110,0cyclictest0-21swapper/221:30:572
1551799110,0cyclictest0-21swapper/220:48:332
1551799110,0cyclictest0-21swapper/219:16:542
15516991111,0cyclictest0-21swapper/121:55:551
15516991111,0cyclictest0-21swapper/100:23:191
15516991111,0cyclictest0-21swapper/100:02:041
15516991110,0cyclictest8342-21id22:43:461
15516991110,0cyclictest8342-21id22:43:461
15516991110,0cyclictest0-21swapper/121:43:461
15516991110,0cyclictest0-21swapper/121:15:081
1551699110,0cyclictest7420-21diskmemload23:28:221
1551699110,0cyclictest7420-21diskmemload23:20:491
1551599119,0cyclictest0-21swapper/019:44:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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