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2026-03-21 - 23:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Mar 21, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750600,0irq/25-eth00-21swapper/107:05:201
120650580,0irq/26-eth1-rx-0-21swapper/307:05:533
1840924824,0sleep00-21swapper/007:05:150
112750450,0irq/25-eth00-21swapper/207:08:482
19716991917,0cyclictest507-21sshd11:03:412
1971699180,0cyclictest25884-21sshd12:11:212
19717991413,0cyclictest11654-21diskmemload12:30:143
19717991413,0cyclictest0-21swapper/312:38:503
19716991413,0cyclictest18985-21sshd09:15:102
1971699140,0cyclictest4864-21sshd10:00:112
1971699140,0cyclictest0-21swapper/210:36:532
19715991413,0cyclictest27719-21bash10:50:131
19715991411,0cyclictest0-21swapper/109:31:551
1971599140,0cyclictest20316-21sshd09:15:151
19714991413,0cyclictest0-21swapper/009:49:390
271130,0ktimersoftd/20-21swapper/209:35:362
19717991312,0cyclictest6267-21switchtime08:55:193
19717991312,0cyclictest22298-21bash12:23:513
19717991312,0cyclictest0-21swapper/311:46:543
19717991312,0cyclictest0-21swapper/311:41:133
19717991312,0cyclictest0-21swapper/311:00:193
19717991311,0cyclictest0-21swapper/309:17:523
1971799130,0cyclictest0-21swapper/311:37:303
1971799130,0cyclictest0-21swapper/310:15:153
1971799130,0cyclictest0-21swapper/309:54:423
19716991312,0cyclictest0-21swapper/210:25:052
19716991312,0cyclictest0-21swapper/210:10:002
19716991311,0cyclictest0-21swapper/210:13:572
19716991310,0cyclictest0-21swapper/209:53:092
1971699130,0cyclictest0-21swapper/210:17:542
19715991312,0cyclictest24465-21sshd11:54:061
19715991312,0cyclictest0-21swapper/112:08:381
19715991312,0cyclictest0-21swapper/111:21:281
19715991312,0cyclictest0-21swapper/110:23:161
19715991312,0cyclictest0-21swapper/109:20:251
19715991312,0cyclictest0-21swapper/109:10:391
19715991311,0cyclictest31814-21sshd09:42:221
19714991313,0cyclictest0-21swapper/012:33:270
19714991312,0cyclictest32283-21bash12:03:420
19714991312,0cyclictest0-21swapper/012:12:040
19714991312,0cyclictest0-21swapper/011:39:320
1971499131,0cyclictest0-21swapper/011:50:120
1971499130,0cyclictest11654-21diskmemload09:40:420
1971499130,0cyclictest0-21swapper/009:58:490
1971499130,0cyclictest0-21swapper/008:22:170
112750130,0irq/25-eth010422-21sshd09:52:221
112750130,0irq/25-eth00-21swapper/311:09:373
19717991212,0cyclictest0-21swapper/310:13:173
19717991211,0cyclictest0-21swapper/311:11:153
19717991211,0cyclictest0-21swapper/309:31:493
19717991211,0cyclictest0-21swapper/309:12:593
1971799120,0cyclictest0-21swapper/311:50:213
1971799120,0cyclictest0-21swapper/311:25:233
1971799120,0cyclictest0-21swapper/310:53:073
1971799120,0cyclictest0-21swapper/309:44:003
19716991211,0cyclictest25164-21sshd09:58:372
19716991211,0cyclictest0-21swapper/212:20:132
19716991211,0cyclictest0-21swapper/211:12:362
19716991211,0cyclictest0-21swapper/211:05:102
19716991211,0cyclictest0-21swapper/210:31:362
19716991210,0cyclictest0-21swapper/211:29:412
19715991211,0cyclictest0-21swapper/112:38:221
19715991211,0cyclictest0-21swapper/109:27:571
19715991210,0cyclictest3151-21sshd12:16:591
19715991210,0cyclictest0-21swapper/111:27:091
1971599120,0cyclictest21464-21sshd09:58:061
1971599120,0cyclictest0-21swapper/111:17:461
1971599120,0cyclictest0-21swapper/110:48:281
1971599120,0cyclictest0-21swapper/109:49:351
1971599120,0cyclictest0-21swapper/108:10:151
1971599120,0cyclictest0-21swapper/107:20:181
19714991212,0cyclictest0-21swapper/011:24:120
19714991211,0cyclictest11654-21diskmemload12:16:150
19714991211,0cyclictest11654-21diskmemload09:28:010
19714991211,0cyclictest0-21swapper/011:55:200
19714991211,0cyclictest0-21swapper/011:09:070
19714991211,0cyclictest0-21swapper/009:15:230
19714991211,0cyclictest0-21swapper/007:20:150
1971499120,0cyclictest0-21swapper/012:26:490
1971499120,0cyclictest0-21swapper/010:50:450
1971499120,0cyclictest0-21swapper/010:40:040
1971499120,0cyclictest0-21swapper/010:26:490
1971499120,0cyclictest0-21swapper/009:30:150
112750120,0irq/25-eth011654-21diskmemload11:34:281
112750120,0irq/25-eth010665-21sshd10:09:343
112750120,0irq/25-eth00-21swapper/112:28:151
19717991111,0cyclictest0-21swapper/310:24:263
19717991111,0cyclictest0-21swapper/308:00:163
19717991110,0cyclictest29948-21sshd10:29:123
19717991110,0cyclictest22790-21sshd10:32:273
19717991110,0cyclictest16757-21sshd11:18:413
19717991110,0cyclictest0-21swapper/312:19:413
19717991110,0cyclictest0-21swapper/312:07:213
19717991110,0cyclictest0-21swapper/311:22:243
19717991110,0cyclictest0-21swapper/310:44:113
1971799110,0cyclictest1425-21sshd11:33:473
1971799110,0cyclictest0-21swapper/311:55:023
1971799110,0cyclictest0-21swapper/310:00:093
19716991111,0cyclictest0-21swapper/212:16:032
19716991111,0cyclictest0-21swapper/211:46:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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