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2026-09-19 - 10:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sat Sep 19, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/319:05:133
120650610,0irq/26-eth1-rx-0-21swapper/119:09:061
576824723,0sleep20-21swapper/219:08:312
120650460,0irq/26-eth1-rx-0-21swapper/019:05:270
595699209,0cyclictest13577-21sshd23:46:401
595899198,0cyclictest15571-21bash21:42:023
595799199,0cyclictest19335-1kworker/2:1H21:31:282
595599190,0cyclictest30692-21sshd23:07:020
595899187,0cyclictest6500-21sshd21:14:453
595899187,0cyclictest12560-21bash00:01:443
595899180,0cyclictest6102-21sshd23:15:273
595899180,0cyclictest23246-21sshd22:35:493
595899180,0cyclictest1539-21sshd23:26:013
595799187,0cyclictest29500-21sshd21:13:372
595799187,0cyclictest29400-21sshd23:22:022
5957991818,0cyclictest0-21swapper/222:40:422
595599180,0cyclictest6365-21sshd21:56:060
351180,0ktimersoftd/332758-21sshd22:02:583
271180,0ktimersoftd/217373-21cp21:42:152
5957991717,0cyclictest0-21swapper/223:03:242
595799170,0cyclictest3922-21bash23:11:272
595899167,0cyclictest29978-21sshd23:03:113
595899165,0cyclictest31717-21sshd23:52:353
595899165,0cyclictest31316-21sshd21:21:173
595799167,0cyclictest12001-21sshd23:38:592
595799165,0cyclictest8541-21bash22:34:122
595799165,0cyclictest21939-21sshd22:24:282
5957991616,0cyclictest0-21swapper/223:59:542
5957991615,0cyclictest6930-21sshd22:11:142
5957991615,0cyclictest1479-21nfsd21:16:102
5957991615,0cyclictest0-21swapper/223:53:032
5957991615,0cyclictest0-21swapper/223:05:292
5957991615,0cyclictest0-21swapper/221:51:542
595699166,0cyclictest18721-21sshd22:58:051
5956991615,0cyclictest0-21swapper/121:39:031
595899154,0cyclictest29131-21sshd21:51:093
5958991514,0cyclictest0-21swapper/323:20:073
595899150,0cyclictest24795-21sshd00:18:253
595899150,0cyclictest14988-21sshd21:15:353
595799154,0cyclictest6228-21sshd21:22:122
595799154,0cyclictest15949-21sshd00:28:452
595799154,0cyclictest1539-21sshd00:02:362
5957991515,0cyclictest0-21swapper/222:02:552
5957991515,0cyclictest0-21swapper/200:21:432
595699150,0cyclictest26740-21sshd21:28:221
595699150,0cyclictest17961-21sshd23:20:371
3399150,0migration/314992-21bash00:13:273
112750150,0irq/25-eth04481-21sshd22:18:343
595899148,0cyclictest31246-21rm00:38:083
595899143,0cyclictest13991-21sshd00:28:313
5958991414,0cyclictest0-21swapper/322:56:463
5958991413,0cyclictest31274-21sshd23:10:503
5958991413,0cyclictest0-21swapper/321:29:193
5958991412,0cyclictest0-21swapper/323:09:553
5957991414,0cyclictest0-21swapper/222:15:392
5957991414,0cyclictest0-21swapper/222:09:302
5957991414,0cyclictest0-21swapper/200:07:012
595799140,0cyclictest28678-21sshd00:15:072
5956991414,0cyclictest0-21swapper/122:48:061
5956991413,0cyclictest1539-21sshd23:32:391
5956991413,0cyclictest0-21swapper/122:32:221
595699140,0cyclictest0-21swapper/100:15:151
595599140,0cyclictest4556-21bash22:14:520
595599140,0cyclictest0-21swapper/000:32:150
595599140,0cyclictest0-21swapper/000:15:240
81130,0rcu_preempt9950irq/24-0000:00:23:01:531
595899133,0cyclictest32742-21sshd00:34:323
595899132,0cyclictest20521-21sshd22:43:113
5958991312,0cyclictest19284-21sshd22:05:123
5958991312,0cyclictest0-21swapper/323:41:483
5958991312,0cyclictest0-21swapper/322:50:313
5958991312,0cyclictest0-21swapper/322:28:233
5958991312,0cyclictest0-21swapper/321:49:083
5958991310,0cyclictest0-21swapper/321:57:393
595899130,0cyclictest24768-21sshd23:48:013
595899130,0cyclictest0-21swapper/319:35:143
595799132,0cyclictest7930-21sshd21:56:182
5957991313,0cyclictest0-21swapper/221:45:012
5957991313,0cyclictest0-21swapper/200:35:452
5957991312,0cyclictest0-21swapper/223:27:072
5957991312,0cyclictest0-21swapper/222:55:492
5957991312,0cyclictest0-21swapper/222:53:182
5957991312,0cyclictest0-21swapper/222:28:042
595699136,0cyclictest18450-21sshd23:09:281
5956991312,0cyclictest24505-21sshd23:55:251
5956991312,0cyclictest0-21swapper/100:24:001
5956991310,0cyclictest4365-21sshd22:14:511
595699130,0cyclictest22030-21sshd22:16:461
595699130,0cyclictest0-21swapper/123:15:361
595699130,0cyclictest0-21swapper/122:39:421
595699130,0cyclictest0-21swapper/121:43:241
595599139,0cyclictest463-21sshd00:07:590
595599132,0cyclictest4971-21sshd22:07:160
5955991312,0cyclictest0-21swapper/023:39:300
5955991312,0cyclictest0-21swapper/021:30:050
5955991312,0cyclictest0-21swapper/000:25:510
5955991311,0cyclictest0-21swapper/021:46:500
595599130,0cyclictest30271-21diskmemload00:21:060
595599130,0cyclictest0-21swapper/000:14:060
5958991212,0cyclictest0-21swapper/323:58:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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