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2026-04-05 - 20:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Sun Apr 05, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112750670,0irq/25-eth00-21swapper/107:05:121
120650600,0irq/26-eth1-rx-0-21swapper/307:05:113
112750550,0irq/25-eth00-21swapper/207:09:312
120650420,0irq/26-eth1-rx-0-21swapper/007:07:550
2054199190,0cyclictest28404-21sshd11:50:133
2054199171,0cyclictest0-21swapper/310:10:323
2054199160,0cyclictest0-21swapper/310:57:073
2053999160,0cyclictest0-21swapper/109:19:441
2054099151,0cyclictest0-21swapper/209:56:122
2054099150,0cyclictest0-21swapper/209:45:212
20538991512,0cyclictest0-21swapper/011:23:290
41140,0ktimersoftd/00-21swapper/009:21:450
20541991413,0cyclictest0-21swapper/310:22:453
20540991413,0cyclictest0-21swapper/209:11:502
20539991413,0cyclictest32424-21sed12:00:171
2053999140,0cyclictest0-21swapper/109:23:131
20538991413,0cyclictest0-21swapper/010:31:400
2053899140,0cyclictest0-21swapper/009:45:110
1599140,0watchdog/012440-21diskmemload11:08:370
20541991312,0cyclictest0-21swapper/310:45:173
20541991312,0cyclictest0-21swapper/310:38:113
20541991312,0cyclictest0-21swapper/310:15:523
20541991312,0cyclictest0-21swapper/309:24:463
20541991312,0cyclictest0-21swapper/309:17:473
20541991311,0cyclictest0-21swapper/310:25:313
20541991311,0cyclictest0-21swapper/309:51:013
20540991312,0cyclictest12440-21diskmemload10:20:362
20540991312,0cyclictest0-21swapper/212:02:292
20540991312,0cyclictest0-21swapper/211:37:242
20540991312,0cyclictest0-21swapper/209:28:122
2054099130,0cyclictest3944-21sshd09:22:592
2053999130,0cyclictest9950irq/24-0000:00:11:46:131
2053999130,0cyclictest0-21swapper/111:36:561
20538991312,0cyclictest12440-21diskmemload11:31:020
20538991312,0cyclictest0-21swapper/010:19:010
20538991312,0cyclictest0-21swapper/009:52:390
112750130,0irq/25-eth022776-21sshd09:40:102
20541991212,0cyclictest0-21swapper/309:26:303
20541991211,0cyclictest9984-21sshd09:43:003
20541991211,0cyclictest9916-21rm09:47:463
20541991211,0cyclictest632-21bash11:02:553
20541991211,0cyclictest5220-21sshd10:54:053
20541991211,0cyclictest0-21swapper/311:32:463
2054199121,0cyclictest351ktimersoftd/311:45:053
20541991210,0cyclictest0-21swapper/312:02:113
20541991210,0cyclictest0-21swapper/309:57:313
2054199120,0cyclictest0-21swapper/312:28:403
2054199120,0cyclictest0-21swapper/311:38:503
2054199120,0cyclictest0-21swapper/311:09:463
2054199120,0cyclictest0-21swapper/308:45:163
20540991211,0cyclictest8608-21sshd11:32:512
20540991211,0cyclictest8179-21sshd10:30:282
20540991211,0cyclictest0-21swapper/210:12:152
20540991210,0cyclictest16499-21sshd10:07:562
20540991210,0cyclictest0-21swapper/211:06:502
2054099120,0cyclictest0-21swapper/212:34:402
2054099120,0cyclictest0-21swapper/211:49:592
2054099120,0cyclictest0-21swapper/210:44:522
2054099120,0cyclictest0-21swapper/210:15:012
20539991210,0cyclictest12440-21diskmemload11:33:541
20539991210,0cyclictest0-21swapper/110:31:451
20539991210,0cyclictest0-21swapper/109:26:421
2053999120,0cyclictest0-21swapper/112:06:331
2053999120,0cyclictest0-21swapper/110:26:111
2053999120,0cyclictest0-21swapper/109:54:421
20538991212,0cyclictest0-21swapper/011:14:530
20538991211,0cyclictest11828-21bash09:57:380
20538991211,0cyclictest0-21swapper/012:20:100
2053899120,0cyclictest0-21swapper/012:16:420
2053899120,0cyclictest0-21swapper/011:00:580
2053899120,0cyclictest0-21swapper/009:17:270
2053899120,0cyclictest0-21swapper/009:11:300
112750120,0irq/25-eth026196-21rm09:35:410
112750120,0irq/25-eth00-21swapper/011:49:020
112750120,0irq/25-eth00-21swapper/008:15:120
41110,0ktimersoftd/00-21swapper/010:26:420
2054199111,0cyclictest0-21swapper/312:33:523
20541991110,0cyclictest31517-21sshd09:31:443
20541991110,0cyclictest0-21swapper/312:11:283
20541991110,0cyclictest0-21swapper/310:00:463
20541991110,0cyclictest0-21swapper/308:57:353
20541991110,0cyclictest0-21swapper/307:23:573
2054199110,0cyclictest0-21swapper/312:35:383
2054199110,0cyclictest0-21swapper/308:08:123
2054199110,0cyclictest0-21swapper/308:02:383
2054099119,0cyclictest0-21swapper/211:12:252
2054099115,0cyclictest0-21swapper/208:37:152
2054099115,0cyclictest0-21swapper/208:17:392
2054099115,0cyclictest0-21swapper/208:07:362
2054099115,0cyclictest0-21swapper/207:58:562
2054099115,0cyclictest0-21swapper/207:50:532
2054099115,0cyclictest0-21swapper/207:36:572
2054099115,0cyclictest0-21swapper/207:28:332
2054099115,0cyclictest0-21swapper/207:23:532
2054099115,0cyclictest0-21swapper/207:11:242
20540991111,0cyclictest0-21swapper/210:39:052
20540991111,0cyclictest0-21swapper/209:36:412
20540991111,0cyclictest0-21swapper/208:25:292
20540991110,0cyclictest22264-21sshd09:54:282
20540991110,0cyclictest12440-21diskmemload12:25:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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