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2026-09-14 - 02:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Mon Sep 14, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28437212565,55sleep30-21swapper/319:07:123
28426211756,55sleep20-21swapper/219:07:032
2676928655,26sleep00-21swapper/019:05:090
2833628455,24sleep10-21swapper/119:06:011
2877299477,37cyclictest0-21swapper/323:38:583
28768994210,29cyclictest0-21swapper/123:10:231
28768994112,26cyclictest0-21swapper/122:11:591
28767994116,22cyclictest0-21swapper/021:45:260
28767994116,22cyclictest0-21swapper/021:45:250
28767994115,23cyclictest0-21swapper/000:06:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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