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2025-11-02 - 08:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sun Nov 02, 2025 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1050729649,20sleep00-21swapper/019:09:310
1043829365,23sleep30-21swapper/319:08:383
1022429163,23sleep20-21swapper/219:06:042
1039628557,23sleep10-21swapper/119:08:031
10653995214,35cyclictest0-21swapper/322:45:123
207772470,1sleep331482-21stress23:11:163
141972430,1sleep231482-21stress21:43:512
10651994328,13cyclictest0-21swapper/221:46:272
10651994312,20cyclictest0-21swapper/200:30:242
1064999418,30cyclictest0-21swapper/000:33:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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