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2026-05-14 - 13:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Thu May 14, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29203211251,56sleep20-21swapper/219:06:522
2916029353,35sleep30-21swapper/319:06:253
2936528557,23sleep00-21swapper/019:08:540
2910828454,25sleep10-21swapper/119:05:461
29552994214,22cyclictest0-21swapper/020:45:050
29552994113,22cyclictest0-21swapper/020:41:210
29553994016,21cyclictest0-21swapper/123:49:481
2955299409,24cyclictest0-21swapper/020:05:050
29552994012,21cyclictest0-21swapper/020:30:210
29552993916,17cyclictest0-21swapper/021:05:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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