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2026-07-24 - 19:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Fri Jul 24, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17958211454,55sleep20-21swapper/207:07:142
18049211151,55sleep10-21swapper/107:08:261
18145211051,21sleep00-21swapper/007:09:330
1785429267,20sleep30-21swapper/307:05:593
1828499495,41cyclictest0-21swapper/312:00:153
1828499495,21cyclictest0-21swapper/309:45:303
1828499495,20cyclictest0-21swapper/309:25:303
1828499495,19cyclictest0-21swapper/310:30:213
1828499485,40cyclictest0-21swapper/309:50:293
1828499485,20cyclictest0-21swapper/310:16:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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