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2026-07-21 - 19:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Tue Jul 21, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2572221300,1sleep18979-21stress09:45:331
2572221300,1sleep18979-21stress09:45:331
19893211551,58sleep30-21swapper/307:09:543
19658211555,55sleep20-21swapper/207:06:572
19777211150,56sleep00-21swapper/007:08:270
264721080,0sleep28979-21stress10:07:482
366421050,1sleep28981-21stress12:35:372
19570210550,50sleep10-21swapper/107:05:501
20005994016,21cyclictest0-21swapper/210:58:532
20004994011,27cyclictest0-21swapper/109:12:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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