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2026-06-28 - 10:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sun Jun 28, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3040421170,1sleep016698-21stress00:09:510
27610211754,58sleep10-21swapper/119:05:511
27863210350,48sleep00-21swapper/019:09:000
2773929364,24sleep30-21swapper/319:07:263
2760628448,32sleep20-21swapper/219:05:482
2804499509,38cyclictest0-21swapper/200:14:062
2804499478,36cyclictest0-21swapper/222:02:212
2804499478,36cyclictest0-21swapper/222:02:212
28044994216,24cyclictest0-21swapper/223:53:542
28044994216,24cyclictest0-21swapper/223:53:542
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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