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2026-08-27 - 00:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Wed Aug 26, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3878211653,58sleep10-21swapper/107:06:351
4142211555,55sleep30-21swapper/307:09:383
333129767,23sleep20-21swapper/207:05:242
390529350,38sleep00-21swapper/007:06:550
4271994413,28cyclictest0-21swapper/010:58:520
4271994115,23cyclictest0-21swapper/011:50:130
4271994112,26cyclictest0-21swapper/011:32:560
4271994015,23cyclictest0-21swapper/012:02:070
427399396,22cyclictest0-21swapper/212:05:202
4273993915,21cyclictest0-21swapper/209:14:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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