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2026-02-15 - 02:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sun Feb 15, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2321221160,1sleep222569-21stress23:43:212
3004211453,23sleep00-21swapper/019:08:200
2953211451,58sleep10-21swapper/119:07:391
3002210150,46sleep30-21swapper/319:08:193
313729065,20sleep20-21swapper/219:09:582
187952460,1sleep322567-21stress23:31:073
187952460,1sleep322567-21stress23:31:063
323899416,20cyclictest0-21swapper/022:55:060
323899416,20cyclictest0-21swapper/022:55:060
323999408,21cyclictest0-21swapper/100:35:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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