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2026-09-17 - 05:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Thu Sep 17, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22947212159,56sleep30-21swapper/319:06:303
23046211151,21sleep10-21swapper/119:07:411
23090210457,43sleep20-21swapper/219:08:142
2312528657,24sleep00-21swapper/019:08:400
23336997013,47cyclictest0-21swapper/122:55:321
138302700,1sleep113100-21stress22:21:181
23336996312,41cyclictest0-21swapper/123:59:261
23336996312,37cyclictest0-21swapper/123:10:021
23336996312,37cyclictest0-21swapper/123:10:011
23336995913,43cyclictest0-21swapper/121:50:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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