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2026-06-11 - 23:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Thu Jun 11, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14205211251,56sleep10-21swapper/107:07:231
298721090,1sleep32879-21stress11:36:073
1414429066,20sleep20-21swapper/207:06:372
1409128961,23sleep30-21swapper/307:06:003
1411428254,23sleep00-21swapper/007:06:150
14511994410,22cyclictest0-21swapper/011:45:230
14514994310,31cyclictest0-21swapper/310:24:533
14511994212,21cyclictest0-21swapper/008:25:160
14514994115,24cyclictest0-21swapper/311:41:403
57042405,13sleep30-21swapper/308:00:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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