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2026-05-08 - 11:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Fri May 08, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13450212161,55sleep30-21swapper/319:07:043
13591211757,55sleep20-21swapper/219:08:482
13600211551,59sleep10-21swapper/119:08:551
13568211351,57sleep00-21swapper/019:08:290
187822423,22sleep01617-21stress23:04:550
13782994216,18cyclictest0-21swapper/020:03:430
13783994113,25cyclictest0-21swapper/123:09:241
13783994113,25cyclictest0-21swapper/123:09:241
13782994114,24cyclictest0-21swapper/023:13:070
13782994114,24cyclictest0-21swapper/023:13:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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