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2025-09-18 - 05:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Thu Sep 18, 2025 00:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29689211251,55sleep00-21swapper/019:06:050
29963210950,20sleep10-21swapper/119:09:311
2968629668,23sleep20-21swapper/219:06:032
3000129466,23sleep30-21swapper/319:09:583
199782460,3sleep016407-21stress21:15:320
30103994211,28cyclictest0-21swapper/323:29:013
30103994211,28cyclictest0-21swapper/323:29:003
30103994115,24cyclictest0-21swapper/323:32:373
30103994011,26cyclictest0-21swapper/322:51:403
30103994011,26cyclictest0-21swapper/322:51:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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