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2026-08-20 - 23:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Thu Aug 20, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17720211956,58sleep30-21swapper/307:09:393
17652211856,21sleep10-21swapper/107:08:481
17543211654,57sleep00-21swapper/007:07:320
17535211251,56sleep20-21swapper/207:07:262
17868994528,14cyclictest0-21swapper/211:10:592
17865994413,19cyclictest0-21swapper/012:35:050
17865994313,15cyclictest0-21swapper/009:26:530
17865994311,29cyclictest0-21swapper/010:41:460
1786799429,15cyclictest0-21swapper/110:54:371
17865994213,25cyclictest0-21swapper/012:19:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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