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2026-08-02 - 19:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sun Aug 02, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13475212361,56sleep20-21swapper/207:05:112
2923621060,1sleep14616-21stress11:18:281
2923621060,1sleep14616-21stress11:18:281
1527829151,35sleep10-21swapper/107:08:321
1533028964,20sleep30-21swapper/307:09:103
1389228441,19sleep00-21swapper/007:05:180
160402700,1sleep04612-21stress10:47:490
15498994211,28cyclictest0-21swapper/310:41:533
15498994211,28cyclictest0-21swapper/310:41:533
15498994115,23cyclictest0-21swapper/312:05:543
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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