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2026-05-27 - 18:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Wed May 27, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11434211959,20sleep20-21swapper/207:07:142
11472211855,58sleep30-21swapper/307:07:433
1135329151,35sleep10-21swapper/107:06:171
1138628456,23sleep00-21swapper/007:06:400
11755996713,39cyclictest0-21swapper/111:10:411
191102580,1sleep032283-21stress09:52:200
11755995313,17cyclictest0-21swapper/109:25:321
11755995311,17cyclictest0-21swapper/111:00:331
11755995214,15cyclictest0-21swapper/112:15:271
1175599519,20cyclictest0-21swapper/111:44:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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