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2026-05-02 - 09:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sat May 02, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16919212464,55sleep20-21swapper/219:09:102
16815211553,57sleep00-21swapper/019:07:480
16766211151,21sleep10-21swapper/119:07:121
434521100,1sleep24873-21stress23:36:502
434521100,1sleep24873-21stress23:36:492
16880210446,53sleep30-21swapper/319:08:383
17082994512,30cyclictest0-21swapper/021:27:460
17088994320,20cyclictest0-21swapper/323:22:163
45092397,12sleep10-21swapper/119:51:071
25852399,12sleep10-21swapper/119:49:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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