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2026-08-17 - 22:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Mon Aug 17, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16443212868,20sleep20-21swapper/207:08:042
1754021260,1sleep16038-21stress10:46:521
16492211453,56sleep30-21swapper/307:08:413
16297211451,58sleep10-21swapper/107:06:181
16243210850,20sleep00-21swapper/007:05:410
240272730,1sleep26038-21stress11:00:462
1671099466,27cyclictest0-21swapper/109:55:201
1671099466,27cyclictest0-21swapper/109:55:191
16711994112,26cyclictest0-21swapper/210:25:432
1671099406,17cyclictest0-21swapper/110:35:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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