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2025-07-19 - 06:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sat Jul 19, 2025 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1616529769,23sleep30-21swapper/319:06:513
1630729466,23sleep20-21swapper/219:08:382
1605828352,26sleep00-21swapper/019:05:360
1634328255,23sleep10-21swapper/119:09:061
106182730,2sleep210619-21timerwakeupswit22:40:352
76082720,3sleep13382-21stress21:20:001
16519997210,46cyclictest0-21swapper/023:46:370
1651999718,43cyclictest0-21swapper/000:20:260
16519997014,44cyclictest0-21swapper/000:05:300
16519996914,43cyclictest0-21swapper/023:05:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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