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2026-06-02 - 19:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Tue Jun 02, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15410211855,23sleep30-21swapper/307:06:283
15686211553,57sleep00-21swapper/007:09:490
1541629062,23sleep20-21swapper/207:06:302
1552328557,23sleep10-21swapper/107:07:541
291592590,2sleep14050-21stress11:20:241
149542520,1sleep14052-21stress10:49:161
15801994411,18cyclictest0-21swapper/111:30:311
15801994411,17cyclictest0-21swapper/112:10:231
1580199435,22cyclictest4050-21stress11:25:151
1580199433,25cyclictest4050-21stress10:40:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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