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2026-05-05 - 11:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Tue May 05, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
816521550,1sleep023377-21stress21:49:200
2935621460,1sleep323375-21stress23:51:303
2935621460,1sleep323375-21stress23:51:293
2709212666,55sleep20-21swapper/219:06:162
2665211653,57sleep00-21swapper/019:05:420
601221120,1sleep323375-21stress22:59:583
2754211052,53sleep30-21swapper/319:06:453
272028555,25sleep10-21swapper/119:06:231
231872620,1sleep323375-21stress22:23:573
3154995411,22cyclictest0-21swapper/000:19:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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