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2025-05-09 - 05:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Thu May 08, 2025 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1279621140,1sleep112972-21stress11:34:141
1279621140,1sleep112972-21stress11:34:141
1842729749,17sleep30-21swapper/307:05:163
1877029253,34sleep20-21swapper/207:09:322
1853728948,18sleep00-21swapper/007:06:330
1850228758,24sleep10-21swapper/107:06:101
18925994612,19cyclictest0-21swapper/111:54:471
91082450,1sleep312970-21stress12:36:143
18925994211,28cyclictest0-21swapper/111:04:341
18926994111,27cyclictest0-21swapper/210:26:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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