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2026-11-15 - 04:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sun Nov 15, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21375211454,54sleep30-21swapper/319:07:593
19562211350,57sleep00-21swapper/019:05:040
21527211252,55sleep10-21swapper/119:09:501
2142228959,25sleep20-21swapper/219:08:352
324792510,1sleep112243-21stress21:54:231
21649994413,22cyclictest0-21swapper/322:10:013
21646994314,23cyclictest0-21swapper/019:42:540
21646994119,15cyclictest0-21swapper/019:18:430
21646994118,18cyclictest0-21swapper/019:55:060
21648994016,21cyclictest0-21swapper/200:13:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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