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2026-08-05 - 20:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Wed Aug 05, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
260121440,1sleep229137-21stress12:15:092
188321230,1sleep229139-21stress09:47:482
11850212160,55sleep30-21swapper/307:06:043
12037211552,57sleep10-21swapper/107:08:231
12042211351,57sleep00-21swapper/007:08:270
1216028858,25sleep20-21swapper/207:09:532
12281994312,21cyclictest0-21swapper/110:52:451
12280994320,18cyclictest0-21swapper/010:00:430
12280994320,18cyclictest0-21swapper/010:00:430
1228299417,16cyclictest0-21swapper/211:43:342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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