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2026-07-27 - 19:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Mon Jul 27, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2328021380,1sleep08930-21stress12:09:540
2328021380,1sleep08930-21stress12:09:540
19488211552,58sleep10-21swapper/107:06:321
19432211453,55sleep20-21swapper/207:05:482
19453211351,56sleep30-21swapper/307:06:063
479121100,1sleep08932-21stress10:11:220
56321080,1sleep38930-21stress10:04:503
1952428557,23sleep00-21swapper/007:06:540
19877995630,23cyclictest0-21swapper/010:04:020
19877995421,21cyclictest0-21swapper/010:36:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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