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2026-04-01 - 04:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Wed Apr 01, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14355211852,59sleep00-21swapper/019:05:010
16365211353,20sleep30-21swapper/319:08:173
16278211151,55sleep10-21swapper/119:07:151
1623729267,20sleep20-21swapper/219:06:442
16600995416,16cyclictest0-21swapper/122:20:111
16600995215,17cyclictest0-21swapper/123:08:001
1660099509,21cyclictest0-21swapper/121:50:291
16599994710,34cyclictest0-21swapper/023:29:420
16599994510,32cyclictest0-21swapper/022:06:030
16600994411,17cyclictest0-21swapper/122:43:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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