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2026-10-23 - 21:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Fri Oct 23, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13391211754,58sleep30-21swapper/307:05:043
14969211654,56sleep20-21swapper/207:05:242
15113211150,56sleep00-21swapper/007:07:100
13388211050,55sleep10-21swapper/107:05:031
1545399506,25cyclictest32673-21modprobe10:10:000
1545399472,34cyclictest5737-21stress12:02:490
1545399472,34cyclictest5737-21stress12:02:490
1545399472,30cyclictest5735-21stress11:40:230
15453994717,20cyclictest0-21swapper/009:49:450
1545399463,33cyclictest5735-21stress12:34:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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