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2026-06-21 - 02:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sun Jun 21, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22307211857,20sleep20-21swapper/219:05:112
2390629367,21sleep30-21swapper/319:06:333
2390228453,26sleep00-21swapper/019:06:300
2230628453,26sleep10-21swapper/119:05:101
24291995613,40cyclictest0-21swapper/121:20:321
24291995510,22cyclictest0-21swapper/123:10:101
24291995315,15cyclictest0-21swapper/121:32:531
24291995315,15cyclictest0-21swapper/121:32:531
24291995111,20cyclictest0-21swapper/121:41:341
24291995111,20cyclictest0-21swapper/121:41:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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