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2026-05-30 - 19:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sat May 30, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2303521500,1sleep35972-21stress09:47:493
2303521500,1sleep35972-21stress09:47:493
17546211151,55sleep00-21swapper/007:08:310
1730229364,23sleep20-21swapper/207:05:362
1766228960,23sleep10-21swapper/107:09:581
1732328456,23sleep30-21swapper/307:05:543
17771994614,24cyclictest0-21swapper/110:55:341
1777199454,31cyclictest0-21swapper/112:20:351
17771994512,22cyclictest0-21swapper/112:11:411
17771994512,22cyclictest0-21swapper/112:11:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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