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2026-03-01 - 23:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sun Mar 01, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5881211961,53sleep30-21swapper/307:08:263
5692211351,56sleep00-21swapper/007:06:060
5772210850,20sleep20-21swapper/207:07:002
578128557,23sleep10-21swapper/107:07:081
30362650,2sleep125478-21stress10:50:001
6114994513,19cyclictest0-21swapper/009:15:150
6116994314,27cyclictest0-21swapper/210:26:122
6116994015,22cyclictest0-21swapper/212:17:062
6117993914,22cyclictest0-21swapper/312:38:073
6117993914,22cyclictest0-21swapper/312:38:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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