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2026-07-30 - 19:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Thu Jul 30, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8665212565,20sleep30-21swapper/319:08:513
7590211450,57sleep10-21swapper/119:05:191
8444210250,20sleep00-21swapper/019:06:140
685728459,20sleep20-21swapper/219:05:072
158512750,1sleep230195-21stress23:02:302
158512750,1sleep230195-21stress23:02:302
8871994414,27cyclictest0-21swapper/022:11:270
887199429,30cyclictest0-21swapper/022:52:080
8871994216,24cyclictest0-21swapper/023:17:110
8871994210,14cyclictest0-21swapper/023:50:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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