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2026-08-23 - 23:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sun Aug 23, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21245211050,55sleep10-21swapper/107:09:441
2094429949,44sleep00-21swapper/007:06:100
2095429469,20sleep30-21swapper/307:06:173
2106129367,22sleep20-21swapper/207:07:322
192742570,1sleep110748-21stress09:26:421
112292500,1sleep310748-21stress11:35:233
21375994211,28cyclictest0-21swapper/012:37:050
2137599419,29cyclictest0-21swapper/011:46:470
21375994116,22cyclictest0-21swapper/010:40:060
21375994014,23cyclictest0-21swapper/011:11:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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