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2026-04-15 - 04:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Wed Apr 15, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27623211753,23sleep00-21swapper/019:05:020
27623211753,23sleep00-21swapper/019:05:010
29626211455,54sleep20-21swapper/219:09:262
29626211455,54sleep20-21swapper/219:09:252
29410211454,55sleep10-21swapper/119:06:391
29410211454,55sleep10-21swapper/119:06:391
29531210378,20sleep30-21swapper/319:08:143
29531210378,20sleep30-21swapper/319:08:133
193862720,2sleep217386-21stress22:30:012
29773994928,19cyclictest0-21swapper/321:30:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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