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2024-04-20 - 04:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sat Apr 20, 2024 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20712212158,23sleep30-21swapper/319:07:413
20515212060,55sleep20-21swapper/219:05:322
20894211451,58sleep10-21swapper/119:09:201
20565210450,49sleep00-21swapper/019:06:020
162332447,33sleep20-21swapper/223:32:132
21153994225,14cyclictest0-21swapper/322:25:383
21151994216,23cyclictest0-21swapper/223:40:212
21151994216,23cyclictest0-21swapper/223:40:212
21146994216,23cyclictest0-21swapper/000:11:030
21153994110,28cyclictest0-21swapper/323:12:333
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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