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2026-07-06 - 13:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Mon Jul 06, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31329212364,20sleep20-21swapper/219:07:282
31252211652,23sleep30-21swapper/319:06:293
31471211351,23sleep10-21swapper/119:09:161
3119629150,36sleep00-21swapper/019:05:490
116282880,2sleep120308-21stress00:30:201
31634994016,21cyclictest0-21swapper/022:04:430
31634994015,14cyclictest0-21swapper/000:35:160
31634993918,15cyclictest0-21swapper/020:45:030
31634993815,20cyclictest0-21swapper/023:35:290
31634993815,20cyclictest0-21swapper/023:35:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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