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2026-06-24 - 04:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Wed Jun 24, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19462211650,59sleep00-21swapper/019:05:230
19462211650,59sleep00-21swapper/019:05:220
1321021150,1sleep08955-21stress21:19:550
20017211252,20sleep20-21swapper/219:07:132
20017211252,20sleep20-21swapper/219:07:122
19944211152,20sleep30-21swapper/319:06:183
19944211152,20sleep30-21swapper/319:06:183
2007629452,37sleep10-21swapper/119:07:571
2007629452,37sleep10-21swapper/119:07:571
151732730,1sleep08955-21stress21:22:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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