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2026-08-08 - 20:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sat Aug 08, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3078211957,56sleep30-21swapper/307:08:183
2881211956,58sleep10-21swapper/107:06:081
2857211653,58sleep00-21swapper/007:05:500
3181211351,20sleep20-21swapper/207:09:262
266472630,1sleep124836-21stress09:10:461
196222510,1sleep124836-21stress11:25:001
3344994415,20cyclictest0-21swapper/112:36:391
334499438,25cyclictest0-21swapper/112:30:211
3344994210,22cyclictest0-21swapper/109:57:511
3345994110,28cyclictest0-21swapper/210:05:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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