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2026-09-02 - 01:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Tue Sep 01, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
92421330,0sleep24784-21stress10:12:302
14865212767,55sleep30-21swapper/307:06:543
14993211251,56sleep00-21swapper/007:08:200
15050210949,21sleep10-21swapper/107:09:051
1493528762,20sleep20-21swapper/207:07:422
64392680,1sleep34784-21stress11:36:413
1524099616,36cyclictest0-21swapper/212:40:012
1524099596,41cyclictest0-21swapper/211:40:282
1524099596,41cyclictest0-21swapper/211:40:282
1524099543,40cyclictest0-21swapper/210:40:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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