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2025-09-13 - 10:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sat Sep 13, 2025 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30061211551,59sleep00-21swapper/019:09:540
29879211251,23sleep20-21swapper/219:07:322
29952211151,21sleep30-21swapper/319:08:283
3005228456,23sleep10-21swapper/119:09:481
30168994216,23cyclictest0-21swapper/221:14:012
30169994122,16cyclictest0-21swapper/300:10:053
30169994122,16cyclictest0-21swapper/300:10:053
30168994114,24cyclictest0-21swapper/221:27:192
30168994110,28cyclictest0-21swapper/222:18:252
73362405,13sleep00-21swapper/020:45:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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