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2026-08-30 - 00:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sat Aug 29, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3239221350,1sleep216951-21stress09:44:282
27076211755,20sleep30-21swapper/307:06:573
27051211351,57sleep00-21swapper/007:06:370
2718129567,23sleep20-21swapper/207:08:132
2709629569,21sleep10-21swapper/107:07:111
27431994313,16cyclictest0-21swapper/112:35:221
27433994210,29cyclictest0-21swapper/210:15:102
2743099429,30cyclictest0-21swapper/012:32:420
27430994212,19cyclictest0-21swapper/012:35:180
27433994116,22cyclictest0-21swapper/211:57:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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