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2026-05-24 - 13:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sun May 24, 2026 00:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2871921370,1sleep228872-21stress23:37:032
2871921370,1sleep228872-21stress23:37:032
8095211654,23sleep30-21swapper/319:06:393
8314211453,56sleep10-21swapper/119:09:141
8099211351,20sleep20-21swapper/219:06:422
823128355,23sleep00-21swapper/019:08:120
847799658,41cyclictest0-21swapper/121:19:261
847799657,48cyclictest0-21swapper/122:04:491
847799648,41cyclictest0-21swapper/123:30:231
847799638,44cyclictest0-21swapper/122:27:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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