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2026-10-08 - 19:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Thu Oct 08, 2026 12:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5374212160,56sleep20-21swapper/207:08:102
5300210950,21sleep00-21swapper/007:07:160
2814121080,1sleep327964-21stress11:33:543
5352210075,20sleep30-21swapper/307:07:543
552428456,23sleep10-21swapper/107:09:531
564699466,38cyclictest0-21swapper/310:39:593
564699465,38cyclictest0-21swapper/312:20:173
564699465,19cyclictest0-21swapper/312:35:253
564699465,19cyclictest0-21swapper/309:35:163
564699456,37cyclictest0-21swapper/310:25:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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