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2026-07-18 - 16:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sat Jul 18, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1343021230,1sleep211099-21stress10:25:462
21750211953,61sleep20-21swapper/207:05:402
21911211753,23sleep00-21swapper/007:07:430
21947211652,59sleep10-21swapper/107:08:121
21909211452,56sleep30-21swapper/307:07:423
22203994516,25cyclictest0-21swapper/209:30:242
22201994413,18cyclictest0-21swapper/011:50:160
2220199429,30cyclictest0-21swapper/010:43:420
2220199429,19cyclictest0-21swapper/010:02:560
2220199429,18cyclictest0-21swapper/010:15:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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