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2026-01-18 - 10:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot1.osadl.org (updated Sun Jan 18, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5858211855,23sleep20-21swapper/219:08:092
4142211453,23sleep00-21swapper/019:05:020
5905210950,20sleep10-21swapper/119:08:441
600328964,20sleep30-21swapper/319:09:593
610799666,44cyclictest0-21swapper/100:15:151
610799656,48cyclictest0-21swapper/122:10:211
610799656,43cyclictest0-21swapper/100:03:071
610799636,46cyclictest0-21swapper/122:50:161
610799636,46cyclictest0-21swapper/100:20:211
610799627,44cyclictest0-21swapper/121:20:151
610799627,44cyclictest0-21swapper/121:15:361
610799626,44cyclictest0-21swapper/121:35:231
610799625,46cyclictest0-21swapper/123:50:461
610799616,45cyclictest0-21swapper/123:10:181
610799616,44cyclictest0-21swapper/100:10:181
610799616,37cyclictest0-21swapper/123:30:181
610799616,37cyclictest0-21swapper/123:30:181
610799606,44cyclictest0-21swapper/122:58:131
610799606,44cyclictest0-21swapper/122:58:121
610799606,43cyclictest0-21swapper/122:00:341
610799606,15cyclictest0-21swapper/123:20:131
610799596,42cyclictest0-21swapper/123:35:281
610799595,17cyclictest0-21swapper/122:45:151
610799586,42cyclictest0-21swapper/100:05:331
610799576,41cyclictest0-21swapper/123:05:321
610799555,36cyclictest0-21swapper/122:25:171
610799555,36cyclictest0-21swapper/122:25:171
610799555,17cyclictest0-21swapper/122:40:331
610799549,30cyclictest0-21swapper/100:25:191
610799536,44cyclictest0-21swapper/121:45:191
610799536,44cyclictest0-21swapper/121:45:191
610799536,37cyclictest0-21swapper/123:41:381
610799536,22cyclictest0-21swapper/121:40:121
610799536,22cyclictest0-21swapper/121:40:121
610799535,34cyclictest0-21swapper/122:05:221
610799527,21cyclictest0-21swapper/121:25:111
610799517,41cyclictest0-21swapper/123:29:421
610799517,41cyclictest0-21swapper/123:29:421
610799516,42cyclictest0-21swapper/123:55:161
610799516,42cyclictest0-21swapper/122:35:071
610799516,42cyclictest0-21swapper/122:15:171
610799516,22cyclictest0-21swapper/123:15:161
610799516,22cyclictest0-21swapper/121:30:271
610799516,21cyclictest0-21swapper/123:00:271
610799516,21cyclictest0-21swapper/122:30:141
610799516,20cyclictest0-21swapper/121:10:171
610799506,41cyclictest0-21swapper/123:45:281
610799506,21cyclictest0-21swapper/122:25:011
610799506,21cyclictest0-21swapper/122:25:011
610799486,39cyclictest0-21swapper/121:10:001
610799485,21cyclictest0-21swapper/120:00:061
610799455,23cyclictest0-21swapper/119:15:541
610799446,20cyclictest0-21swapper/121:55:191
610799445,23cyclictest0-21swapper/120:45:541
610799445,23cyclictest0-21swapper/120:15:541
610799445,12cyclictest0-21swapper/120:23:241
610799436,20cyclictest0-21swapper/120:50:221
610799435,36cyclictest0-21swapper/120:40:261
610799435,22cyclictest0-21swapper/120:36:141
610799435,16cyclictest0-21swapper/119:40:211
610799435,12cyclictest0-21swapper/119:37:151
610799435,12cyclictest0-21swapper/119:27:341
610799429,12cyclictest0-21swapper/120:26:401
610799425,16cyclictest0-21swapper/120:10:061
610799425,14cyclictest0-21swapper/119:45:201
610799425,12cyclictest0-21swapper/121:01:541
610799425,12cyclictest0-21swapper/119:59:541
610799425,12cyclictest0-21swapper/119:59:541
610799415,33cyclictest0-21swapper/120:55:221
610799415,16cyclictest0-21swapper/119:30:051
610799415,15cyclictest0-21swapper/119:50:051
610799415,14cyclictest0-21swapper/120:30:061
610799415,14cyclictest0-21swapper/119:23:341
610799405,20cyclictest0-21swapper/121:50:271
610799405,15cyclictest0-21swapper/120:05:321
185472405,14sleep00-21swapper/020:53:290
6109993914,22cyclictest0-21swapper/323:25:133
6109993914,22cyclictest0-21swapper/323:25:133
610799395,17cyclictest0-21swapper/100:35:021
610799395,17cyclictest0-21swapper/100:30:021
610799395,14cyclictest0-21swapper/119:10:201
6106993917,20cyclictest0-21swapper/020:10:220
210842395,14sleep20-21swapper/221:00:412
207542395,14sleep00-21swapper/020:59:470
141702395,14sleep00-21swapper/020:41:300
78012385,12sleep30-21swapper/320:25:583
6108993811,24cyclictest0-21swapper/200:12:302
6108993810,25cyclictest0-21swapper/221:53:232
610699388,24cyclictest0-21swapper/021:00:320
36292385,13sleep30-21swapper/320:16:553
296342384,13sleep20-21swapper/220:00:502
234692383,14sleep30-21swapper/321:09:213
212782383,14sleep30-21swapper/319:41:263
134272383,14sleep20-21swapper/220:40:212
99392375,14sleep00-21swapper/020:31:200
80832375,10sleep20-21swapper/219:14:072
610999378,27cyclictest0-21swapper/300:40:013
37012373,13sleep20-21swapper/220:17:392
275852375,14sleep00-21swapper/019:56:230
275852375,14sleep00-21swapper/019:56:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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