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2026-04-19 - 20:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot1.osadl.org (updated Sun Apr 19, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16948211555,20sleep30-21swapper/307:05:293
273002940,2sleep25020-21stress12:30:272
1728629151,35sleep00-21swapper/007:09:450
1716929166,20sleep20-21swapper/207:08:232
1542128353,24sleep10-21swapper/107:05:031
142942510,3chrt5020-21stress10:45:211
1741599453,31cyclictest30933-21sed10:10:021
1741599453,31cyclictest30933-21sed10:10:021
1741599442,32cyclictest5020-21stress10:55:091
1741599433,31cyclictest5834-21cut07:55:151
1741599433,25cyclictest5020-21stress12:00:181
1741599433,24cyclictest883-21cut09:00:111
1741599432,26cyclictest5022-21stress09:57:561
1741599432,26cyclictest5022-21stress09:57:561
1741599432,26cyclictest5020-21stress11:16:581
1741599432,25cyclictest5020-21stress12:20:181
1741599432,25cyclictest5020-21stress12:20:181
17416994222,18cyclictest0-21swapper/209:23:312
17416994222,18cyclictest0-21swapper/209:23:302
17416994212,27cyclictest0-21swapper/212:24:082
17416994212,27cyclictest0-21swapper/212:24:082
1741599423,24cyclictest5022-21stress11:52:221
1741599423,24cyclictest5022-21stress11:10:021
1741599423,24cyclictest5022-21stress11:10:021
1741599423,24cyclictest5020-21stress10:20:261
1741599422,26cyclictest5022-21stress12:33:011
1741599422,25cyclictest5022-21stress12:26:051
1741599422,25cyclictest5020-21stress11:58:451
1741699419,29cyclictest0-21swapper/212:03:202
1741699416,24cyclictest0-21swapper/210:20:332
17416994111,27cyclictest0-21swapper/212:26:062
1741599413,29cyclictest5022-21stress12:15:071
1741599413,29cyclictest5022-21stress12:15:061
1741599413,27cyclictest5022-21stress09:45:291
1741599413,23cyclictest5022-21stress10:15:281
17415994115,24cyclictest0-21swapper/109:15:221
17415994114,19cyclictest0-21swapper/111:25:301
1741599411,25cyclictest5020-21stress11:45:011
1741699408,29cyclictest0-21swapper/209:48:022
17416994010,27cyclictest0-21swapper/212:38:522
17416994010,27cyclictest0-21swapper/211:40:492
17416994010,27cyclictest0-21swapper/209:25:092
1741599403,25cyclictest18083-21fschecks_count07:10:141
1741599403,23cyclictest5022-21stress09:10:281
1741599403,23cyclictest5020-21stress10:14:091
1741599402,26cyclictest5019-21stress09:20:251
1741599402,26cyclictest5019-21stress09:20:241
1741599402,24cyclictest5022-21stress11:48:441
1741599402,24cyclictest5022-21stress11:48:441
1741599402,24cyclictest5022-21stress10:40:351
17427993911,25cyclictest0-21swapper/310:05:293
17427993911,25cyclictest0-21swapper/310:05:293
1741699398,27cyclictest0-21swapper/211:57:532
1741699398,27cyclictest0-21swapper/210:40:262
17416993914,22cyclictest0-21swapper/210:02:192
17416993914,22cyclictest0-21swapper/210:02:182
17416993910,26cyclictest0-21swapper/212:10:162
1741599393,27cyclictest28960-21cut08:50:011
1741599393,24cyclictest3308-21aten2_r7power_v07:50:131
1741599393,24cyclictest11674-21latency_hist08:10:001
1741599393,23cyclictest12533-21irqstats08:10:161
1741599392,23cyclictest5022-21stress11:10:381
1741599392,23cyclictest5020-21stress10:04:281
1741599392,23cyclictest5020-21stress10:04:281
1741499396,23cyclictest0-21swapper/011:54:450
1741499396,22cyclictest0-21swapper/010:30:230
284812385,13sleep30-21swapper/307:30:403
178532385,13sleep30-21swapper/308:23:063
1742799389,26cyclictest0-21swapper/310:36:553
1742799388,27cyclictest0-21swapper/310:10:153
17427993811,24cyclictest0-21swapper/309:10:143
1741699387,28cyclictest0-21swapper/210:51:412
17416993815,20cyclictest0-21swapper/211:33:092
17416993811,24cyclictest0-21swapper/211:49:442
17416993811,24cyclictest0-21swapper/211:49:442
17416993810,25cyclictest0-21swapper/212:05:052
17416993810,25cyclictest0-21swapper/211:36:462
1741599383,25cyclictest1096-21rs:main1
1741599383,24cyclictest5022-21stress11:39:231
1741599383,24cyclictest5020-21stress11:24:431
1741599383,22cyclictest21184-21expr08:30:201
17415993816,20cyclictest0-21swapper/111:00:211
17415993816,20cyclictest0-21swapper/109:35:311
8442375,11sleep30-21swapper/309:00:073
70032375,14sleep30-21swapper/307:57:003
264382375,11sleep20-21swapper/207:26:422
242172375,11sleep30-21swapper/308:37:253
242172375,11sleep30-21swapper/308:37:253
192522375,11sleep30-21swapper/307:12:003
1742799378,26cyclictest0-21swapper/310:33:003
17427993716,18cyclictest0-21swapper/309:15:243
17427993712,22cyclictest0-21swapper/309:51:063
1741699379,25cyclictest0-21swapper/209:18:002
17416993724,11cyclictest0-21swapper/209:43:502
1741599375,21cyclictest0-21swapper/108:55:181
1741599373,25cyclictest30868-21cron08:55:011
1741599373,24cyclictest1096-21rs:main1
1741599372,21cyclictest5022-21stress12:10:051
17415993717,18cyclictest0-21swapper/109:40:351
17415993716,19cyclictest0-21swapper/110:25:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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