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2026-02-23 - 15:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot1.osadl.org (updated Mon Feb 23, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23774211955,58sleep10-21swapper/107:07:581
23756211452,56sleep00-21swapper/007:07:440
23838211253,20sleep30-21swapper/307:08:473
2368928963,21sleep20-21swapper/207:06:542
24035994310,30cyclictest0-21swapper/111:57:181
24035994310,30cyclictest0-21swapper/111:33:381
24035994310,30cyclictest0-21swapper/111:33:381
2403599417,31cyclictest0-21swapper/110:46:241
24036994013,24cyclictest0-21swapper/210:57:312
24035993915,18cyclictest0-21swapper/109:50:421
24035993915,18cyclictest0-21swapper/109:50:421
24035993912,24cyclictest0-21swapper/110:05:181
24034993911,25cyclictest0-21swapper/009:19:260
217082390,1sleep011063-21stress10:50:170
7112385,13sleep20-21swapper/207:29:242
302262385,13sleep30-21swapper/308:35:263
29242389,10sleep00-21swapper/007:34:430
283712385,13sleep20-21swapper/208:33:372
28332385,13sleep20-21swapper/207:33:412
256742385,13sleep30-21swapper/307:10:243
2403599388,27cyclictest0-21swapper/111:35:161
2403599388,27cyclictest0-21swapper/111:35:161
24035993810,25cyclictest0-21swapper/109:33:241
24034993814,22cyclictest0-21swapper/010:11:460
24034993811,24cyclictest0-21swapper/011:25:580
171502385,13sleep10-21swapper/108:05:241
100762385,13sleep00-21swapper/009:05:220
70822375,13sleep20-21swapper/207:43:082
43052375,13sleep20-21swapper/208:51:212
304262375,13sleep20-21swapper/208:37:462
261062375,13sleep20-21swapper/208:26:432
260902375,13sleep10-21swapper/108:26:301
24036993715,19cyclictest0-21swapper/209:10:572
24036993715,19cyclictest0-21swapper/209:10:562
24036993714,20cyclictest0-21swapper/211:15:122
24036993711,23cyclictest0-21swapper/211:45:272
2403599379,25cyclictest0-21swapper/112:15:151
24035993723,12cyclictest0-21swapper/109:20:111
24035993715,20cyclictest0-21swapper/112:01:101
24035993711,24cyclictest0-21swapper/111:40:171
24035993710,25cyclictest0-21swapper/109:50:001
24035993710,24cyclictest0-21swapper/112:39:061
22852374,13sleep20-21swapper/208:48:032
21512375,13sleep30-21swapper/308:46:213
199462375,13sleep20-21swapper/208:14:442
197362375,13sleep10-21swapper/108:12:011
132432374,13sleep10-21swapper/107:55:301
111852375,13sleep20-21swapper/207:51:172
109682375,13sleep20-21swapper/209:09:492
90122364,13sleep10-21swapper/107:45:401
65042364,13sleep10-21swapper/108:57:041
48092365,12sleep30-21swapper/307:36:263
45202364,13sleep10-21swapper/108:54:011
288852364,13sleep10-21swapper/107:18:561
241302364,13sleep10-21swapper/108:23:411
24036993610,23cyclictest0-21swapper/209:51:562
24036993610,23cyclictest0-21swapper/209:51:562
2403599369,24cyclictest0-21swapper/110:50:111
24035993616,18cyclictest0-21swapper/110:20:331
24035993616,18cyclictest0-21swapper/110:20:331
92052354,13sleep00-21swapper/007:48:070
69812355,12sleep30-21swapper/307:41:483
49882353,13sleep10-21swapper/107:38:461
324862354,13sleep30-21swapper/308:41:563
286382354,13sleep00-21swapper/007:15:510
241222353,13sleep30-21swapper/308:23:353
2403699356,26cyclictest0-21swapper/209:27:382
24036993515,17cyclictest0-21swapper/210:28:102
24036993515,17cyclictest0-21swapper/210:28:102
24036993512,20cyclictest0-21swapper/211:13:532
24036993511,21cyclictest0-21swapper/210:40:042
2403599359,24cyclictest0-21swapper/109:35:141
2403599359,17cyclictest0-21swapper/112:30:331
24035993515,14cyclictest0-21swapper/111:15:161
24035993514,18cyclictest0-21swapper/111:00:321
24035993514,18cyclictest0-21swapper/111:00:321
24035993513,16cyclictest0-21swapper/112:05:481
2403499357,25cyclictest0-21swapper/010:45:230
24034993515,18cyclictest0-21swapper/009:55:150
24034993515,17cyclictest0-21swapper/010:09:310
24034993514,19cyclictest0-21swapper/009:25:320
24034993511,21cyclictest0-21swapper/012:37:210
113682355,13sleep30-21swapper/307:53:403
90042345,12sleep30-21swapper/307:45:343
85612344,12sleep00-21swapper/009:01:170
70462344,13sleep10-21swapper/107:42:381
284042346,10sleep00-21swapper/008:34:030
241722344,12sleep00-21swapper/008:24:110
24037993420,12cyclictest0-21swapper/311:44:343
24036993415,16cyclictest0-21swapper/212:30:292
24036993415,16cyclictest0-21swapper/211:30:492
24036993415,16cyclictest0-21swapper/211:30:482
24036993411,20cyclictest0-21swapper/209:20:132
24035993415,17cyclictest0-21swapper/111:10:141
24035993415,16cyclictest0-21swapper/109:15:361
24035993414,18cyclictest0-21swapper/111:45:241
24035993412,20cyclictest0-21swapper/112:20:291
24035993412,20cyclictest0-21swapper/111:06:221
24035993411,21cyclictest0-21swapper/112:25:091
24034993416,16cyclictest0-21swapper/012:20:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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